École Polytechnique de Montréal

Cadence Layout Tutorial (V1.0)

CMOSP18 technology A. Miled, M. Sawan

GBM8320: Dispositifs Médicaux Intelligents

Janvier 2011

Step 0

Before starting cadence add these lines to the “.cdsinit” file:

setSkillPath(cons( "/CMC/kits/cmosp18.5.2/skill" getSkillPath() ) ) load("/CMC/kits/cmosp18.5.2/skill/CMOSP18init.il" ) hiSetBindKey("Command Interpreter" "<Key>F6" "ddsOpenLibManager()") If the file does not exist, you have to create by yourself. It is a hidden file, be sure that you enabled “show/view hidden file” in the operating system you are using.

The file must be placed in your working directory (from where you start cadence).

Step 1

Start Cadence by taping in your terminal these commands:

% setenv CDS_AUTO_64BIT NONE % stcds % stcdscmp18 your icfb (Fig.1) window should be like this

Fig.1. icfb window

Step 2: Create your library

In the icfb menu bar go to:

Tools->Library Manager to open the library manager (Fig.2)

Fig.2. Library manager window

Then in the Library manager menu bar go to:

File->New->Library

In the Name field tape OpAmp_input_stage as shown in Fig.3 and then OK

Fig.3. New library

Then select attach to an existing techfile then OK (Fig.4)

Fig. 4. New Library second window

Attach the library to the CMOSP18 technology then OK (Fig.5)

Fig. 5. Attach technology file

At this level your library is OpAmp_input_stage is created.

Select OpAmp_input_stage in the library manager by clicking on it (ONLY 1 click) in the library manager (Fig.6).

Fig. 6. Library manager window

Then in the library manager go to File->New->Cell View

Fill all fields as indicated in Fig.7

Fig.7. Cell view creation

At this level you can see your cell view in your created library as shown in Fig. 8

Fig.8. Cell view in the library manager

At the same time the virtuoso layout editor will be opened with and empty work space.

Fig.9. Virtuoso Layout Editor

Step 3: create your layout

Click on “i” shortcut in your keyboard or go to Creat -> Instance through the virtuoso editor menu toolbar (Fig. 10)

Fig.10. Create instance window

By clicking on browse select the instance layout you want to add to your design.

All needed components can be found in CMCpcells library:

- spcnmos: nMOS transistor - spcpmos: pMOS transistor

Somme hints:

1. Gate splitting: useful when your gate length is too big and you want to divide it into several small parts

2. Enable Add substrate well 3. Enable internally connect poly 4. Choose source and drain in the connect S/D to metal

Choose your gate length and width.

Now when you click in any free workspace area of the virtuoso editor your transistor will be instantiated (Fig. 11).

Fig.11. nMOS transistor

Step 4: routing your design

We assume that the design is an inverter. As it is just a tutorial, we will use the default gate length and width and we will not optimize them for a correct behavior of the inverter.

Fig. 12 shows the two transistors p and n.

Fig.12. nMOS and pMOS transistors

to connect the two drains together, add two metal1-metal2 contacts through these following steps.

Go to create->contact

Fig. 13 Create contact window

In contact type choose the contact you want to create (Fig.13).

Example: M2_M1 create a contact between metal 1 and metal 2 layers. (if you have no specific requirement keep the other option in their default selection).

The result is shown in Fig. 14.

Fig. 14. Two instantiated transistors nMOS and pMOS

In the LSW bar (Fig. 15), select metal2. You should have three types (drw, net, pin), select the drw layer. Then by clicking on the keyboard shortcut “r” create your rectangle.

The same process can be done by clicking on the keyboard shortcut “p” (path). The difference between “r” and “p”, is:

- “r” creates simple transistors. - “p” creates a path between point A and B and by using a mouse you can do any

shape.

In this tutorial, the connection between the two drains was made using “r” and the connection between the gates was made using “p”.

Fig. 15 LSW toolbar

The final result is shown in Fig. 16. (You have to connect also the source to the substrate as shown in the same Fig. 16)

Fig. 16 Layout design with connections

Then create your IN/OUT pin:

Go to create->pin…, the window shown in Fig. 17 will appear.

Fig. 17. Create pin window

Don’t forget to enable Display Pin Name if you would like to see the pin name. Add all terminal names placed on the same metal layer. When done go to your workspace and place them in their correct place. Each time you click in the workplace you will place a pin following the order you choose when you wrote then in the terminal names field in the create symbolic Pin (Fig. 17). Do the same with In and Out respectively on poly and metal 2.

Hint. Its not recommended to use Poly metal for connections, thus it is better to go from Poly to metal 1 and then go back to poly.

At this level you finished your layout and you can start verifying your design

Step 5: DRC Design Rule Check.

The design rule check will verify your design and check if it can be manufactured with respecting the foundry rules. This a crucial steps and you MUST fixe ALL errors in your design if you wanted to be fabricated in a standard run. However in this tutorial, we will ignore some errors, as they cannot be removed unless you design the complete chip.

Go to verify->DRC a window like the one shown in Fig. 18 will appear. Set all parameters as shown in Fig.18 and click on OK.

Fig.18. DRC window

If everything is good you will probably have two errors: floating poly and too many layers). If the poly error is related to your inputs you ignore it, for all other poly error you have to fixe them first. Then, fix all other errors. Finally you are supposed to get an icfb window like shown in Fig. 19.

Fig.19. ICFB window after DRC

Then do an extract: go to verify-> extract, a window like the one shown in Fig. 18 will appear. Set all parameters as shown in Fig.20 and click on OK.

Fig.20. Extractor window

Your icfb window should like Fig. 21

Fig.21. ICFB window after extraction

When this step is done successfully, that’s mean that you have finished your layout and not you will start creating your symbol for post layout simulation purpose.

Now in your library you should see

Fig.22 Library manager view after extraction

Open the extracted file that you can find in the view field of the library manager (Fig.23)

Fig. 23. Extraction view

Go to CMC SKILL->Layout/Extract->Clean extracted view. You should see in your icfb “ Completed CMOSP18cleanExtract” (Fig. 24)

Fig. 24 ICFB after clean extract

The next step consists of doing an LVS (Layout versus Schematic comparison to check that your layout corresponds to your circuit schematic. Thus, it is assumed that you circuit is done and functional (schematic level). You must use the same pin name in your layout and schematic otherwise it will be considered as an error. Also remove all power supplies and ground, keep only the connection pins as shown in Fig. 25

Fig.25. Circuit schematic view

Open the extraction view and go to verify->LVS and set all parameters as shown in Fig.26. (It is important to pay attention to the capital letters in your file name).

Then click on Run.

Fig. 26. LVS window view

If everything is fine, you are supposed to have a message telling you that layout matched schematic. Click on Output in Fig.26 to check your LVS report and correct error. If your have only errors related to device does not cross match you can ignore this error in this tutorial. Your LVS report should look to Fig. 27 a and b.

(a)

(b)

Fig. 27. LVS report

Then go to CMC SKILL->Layout/Extract->Generate pin-only schematic. You should get Fig. 28 in your icfb

Fig.28 ICFB after clean extract

Now you have another schematic file added to your view field in your library manager

Fig.29. library manager after creating the schematic

Open the schematic view (Fig. 30)

Fig. 30. Schematic view

go to Design->Create Cellview->From Cellview. Fig. 31 will appear

Fig. 31. Cell view window

Click Ok, then you will have your symbol (Fig32) where you can move your pins and place them wherever you want.

Fig. 32 symbol view

Now you just finished the layout tutorial and you have to test your design.

Create another schematic view in another library and bring your symbol like you do with any other transistors and start your testing.