LAYOUT GENERATION AND

ITS APPLICATION

by

JACOB L. NICKOLOFF

A thesis submitted in partial fulfillment of

the requirements for the degree of

Master of Science in Electrical Engineering

WASHINGTON STATE UNIVERSITY

School of Electrical Engineering and Computer Science

August 2007

ii

To the Faculty of Washington State University:

The members of the Committee appointed to examine the thesis of JACOB L. NICKOLOFF

find it satisfactory and recommend that it be accepted.

Chair

iii

ACKNOWLEDGMENTS

I especially thank my wife, MerrieBeth, for her unwavering support.

I thank my adviser, George La Rue, for his technical renditions, direction, and patience.

I thank Dirk Robinson for his imperative help in applying periodic steady state analysis and

the exploration of noise reduction techniques.

iv

LAYOUT GENERATION AND

ITS APPLICATION

Abstract

by JACOB L. NICKOLOFF, M.S.

Washington State University

August 2007

Chair: George S. La Rue

The extension of the expert design based layout generator, LGen, is examined in detail.

These extensions include the generator being ported to the GNU/Linux platform as well as the

addition of two analog circuit layout generators to the system.

The future of layout generation is discussed. It has been proven in the industry that fully

automated approaches to layout generation in digital circuits, given broad algorithmic or netlist

specifications, is possible and practical. Despite many attempts in academia, this approach has

not been proven in the analog domain. An expert design based layout generator that adequately

captures expert design in a reusable, platform and process independent way, is the answer.

LGen is used in the layout design of a low noise, low power switched capacitor filter. Its

circuit design is also discussed in detail.

The future of expert based layout generators is believed to be in constraint based geome-

try databases. Such a layout generator, properly implemented, would resolve complex layout

interconnectivity automatically, simplifying layout design.

George S. La Rue

v

TABLE OF CONTENTS

Page

Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 History of Layout Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 The Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4 The Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Introducing LGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 The LGen Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 Layout Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3 The Calibre Rule Extractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.4 The GUI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.5 An Early Application of LGen . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 The Extension of LGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Making LGen Platform Independent . . . . . . . . . . . . . . . . . . . . . . . 143.2 Capacitor Array Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.3 Common Centroid FET (CCFet) Generator . . . . . . . . . . . . . . . . . . . 203.4 FET Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

vi

Page

4 Switched Capacitor Filter Application . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 The Surrounding System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.2 The Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 The Future of LGen and Layout Generation . . . . . . . . . . . . . . . . . . . . 31

5.1 The Future of LGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315.2 The Future of Layout Generation . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

List of References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Appendix A: Switched Capacitor Filter Schematics . . . . . . . . . . . . . . . . 39

Appendix B: Switched Capacitor Filter Results . . . . . . . . . . . . . . . . . . 48

vii

LIST OF TABLES

Table Page

4.1 Switched Capacitor Filter Target Specifications . . . . . . . . . . . . . . . . . . . 25

4.2 Switched Capacitor Filter Results Summary . . . . . . . . . . . . . . . . . . . . . 29

viii

LIST OF FIGURES

Figure Page

2.1 Rad Hard By Design FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 LGen standard cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 LGen GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Phase Accumulator Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Main binary weighted capacitor array . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 One quadrant of main capacitor array . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3 Switched Capacitor Filter Application (Whole View) . . . . . . . . . . . . . . . . 20

3.4 Switched Capacitor Filter Application (1st Stage View) . . . . . . . . . . . . . . . 21

3.5 Switched Capacitor Filter Application (Differential Pair) . . . . . . . . . . . . . . 22

A.1 Toplevel Test Bench Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . 40

A.2 Whole 4th Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

A.3 Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

A.4 1st Stage Biquad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

A.5 2nd Stage Biquad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

A.6 Integrator Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

A.7 Low Power Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

ix

Figure Page

A.8 RC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

B.1 Filter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

B.2 Filter Transfer Function (Various Cutoff Frequencies) . . . . . . . . . . . . . . . . 50

B.3 Cutoff vs. Sampling Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

B.4 Output Noise Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

B.5 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

x

NOMENCLATURE

API An Application Program Interface is an interface by which a program can access internal

Operating System methods or other services.

Class A Class is a template by which Objects are instantiated from at runtime in a program. A

class encapsulates data and provides a clean interface for the manipulation of that data.

Geometry Primitive shapes and constructs, such as rectangles, polygons, or ports, that form

mask layout.

GUI A Graphical User Interface is a part of a software program that allows a user to interact

with the software in a graphical manner.

Method Scale A useful measure by which a Layout Generator’s way of implementation can

be classified. On one end of the scale there is Expert Design, on the other Algorithmic.

Object Objects are instances of Classes.

RHBD Rad Hard By Design is a circuit design technique that increases a circuit’s ability to

resist performance degradation or failure while being irradiated.

The Layout Problem The problem with layout is that it is tedious to design due to many

interdependencies between geometric primitives and that it is not very reusable.

1

Chapter 1

Introduction

The design of integrated circuits (IC’s) can be broken up into two major parts. The circuit

design, which is done in schematic, and the translation of that design into a form that can be

understood by the foundry, known as layout.

This thesis is about solving the Layout Problem, which is the tedious and error prone pro-

cess of drawing integrated circuit components. The tedium can be lifted through the exploita-

tion of layout generators. The extension of a such a layout generator is outlined as well as the

insight gained into layout generation that came about through its development.

1.1 Background

The study of layout generation is made more complex by the lack of standardized termi-

nology and classification in the field. This section will prepare the reader for the following

section, ”History of Layout Generation”, by introducing some terminology and background.

Layout generators are also known as silicon compilers or even analog/digital CAD frame-

works. All generators tend to fall between two extreme methods of implementation, algorith-

mic and expert designed. This scale will be from now on referred to as the method scale.

Algorithmic techniques rely on analytic equations and/or various optimization techniques to

transform user specifications to layout. This transformation can include various parameters

such as device sizing, component placement and routing, and topology selection to name a

2

few. Expert designed techniques rely on capturing expert designer knowledge in a useful, re-

producible, and reusable way. This method tends to include a lot of initial set up and designing

on the experts part, but afterwards, can be reused many times.

Layout generators also have varying levels of circuit synthesis capabilities. Although this

thesis tries to focuses on layout generation only, some tools’ circuit synthesis is so closely

connected with the layout generator that it is hard to focus on one and not the other. This is

especially true of digital layout generation.

The method scale along with synthesis level gives a tool varying automation capabilities,

ranging from netlist in-layout out, to manual geometry specification with parameterized values.

It is much more difficult to automate analog layout design then digital as analog layout is

more sensitive to composition. Different analog circuits are sensitive in different ways, but

some examples of analog issues for layout generators are crosstalk, resistance in the wires, and

imperfections in the manufacturing process that can lead to component mismatches. Mitigating

these effects are usually up to an expert designer, which is hard for a computer to emulate.

1.2 History of Layout Generation

Layout generators did not gain much interest until the early eighties, when advancements

in digital VLSI technology started to bring to light some of the deficiencies in the CAD tools

of the time. Practically all of the layout generators of this time were for digital circuits, and

included both extremes of the method scale [1–4]. Digital layout generators have continued to

advance over the years with different implementations under the hood and eventual standard-

ized hardware description language front ends, such as VHDL or Verilog, for user specification

input. The Synopsys IC Compiler is an example of this methodology being implemented suc-

cessfully in the industry.

Analog layout generators did not see wide spread development until the late eighties and

early nineties. Generators from both sides of the method scale were developed at about the

3

same time. Papers at this time described more automated design, algorithmic based genera-

tors [5–11] then expert based [12–14], with some falling in the middle [15–18]. These gen-

erators usually employed expert based analog leaf cell generation with algorithmic place and

route or leaf cell selection. Several specialized analog layout generators were also developed.

These generators usually sacrificed the generality of the generator in order to better enhance its

automation [19–21]. It is much easier to create algorithms for a well defined application space,

then for a general one.

Generators from all over the method scale have seen several different re-implementations

right up to the present (2007). These developments included different algorithmic approaches

in the various design pipelines of the generators [16,22–24], to different ways of storing expert

knowledge [14].

1.3 The Problem

At least two major factors in layout design contribute to its design time; the shear com-

plexity of layout interdependencies and the lack of re-usability of completed layout. These two

factors can be thought of as the core problems that plague layout. If they can be adequately

solved then layout design would become much more efficient.

Due to the nature of the current industry standard layout editors, it is very difficult to change

one thing while leaving the rest of the layout alone. Layout tends to be interconnected and

making one modification tends to cascade into many. Lack of layout reuse tends to dupli-

cate previous work, and this happens especially when migrating from one process to another.

The foundry design rules that govern spacing and geometric composition in layout differ from

process to process. Due to the previously mentioned difficulty of post layout modification,

migrating from process to process is a time consuming task.

Although layout generators can solve the core problems, their implementation causes most

of them to deviate from an ideal solution. Some of these non-ideal aspects will be highlighted

and discussed in the following paragraphs.

4

Time and effort could be saved in generator development through the sharing of ideas, not

only at the top-level, but also at the lower level implementations, such as source code, that are

never conveyed in any meaningful detail in papers. Open sourcing layout generators not only

makes them widely available to the public, but allows users to customize and add on to them.

This openness also reduces the re-implementation of ideas. Practically all tools developed

in academia are closed to the public. Although there are reasons that layout generators in

academia and proprietary design environments are closed source, because of this these tools

can not be customized, adapted, or built upon according to the needs of customers.

Expert based layout generators have found their way into the IC industry through the Men-

tor and Cadence IC design environments. The extreme cost of proprietary tools in layout

generation makes their overall solution less portable, which also makes their created layout

less re-usable. If a Pcell is created using Cadence’s layout generator it only remains useful as

long as all interested parties using that Pcell, have Cadence. The cost of these tools also bars

many from even making use of these solutions.

Many proprietary layout generators are not process independent, forcing designers to rewrite

their generators to migrate to different processes. There are many layout generators in academia

that are process independent.

1.4 The Solution

A properly implemented and licensed layout generator can solve the Layout Problem. Of

the two extremes on the Method Scale it is believed that expert based is the best solution, and

this is due mostly to its flexibility. The premises behind this conclusion and the advantages and

disadvantages of these extremes of generator implementation will now be discussed.

At the present fully automated, algorithmic based layout design and circuit synthesis widely

exists for digital circuits, with limited automated support for analog layout design. It is interest-

ing to note that, even though automated analog layout generation has been developed and used

in limited academia circles for more then a decade and a half, that the ideas they implement to

generate analog layout have not made it into mainstream, industry standard software.

5

The downfall of many expert based layout generators is that even though hierarchy is ex-

ploited, and even special languages developed for them [25], the creation of the generator be-

comes supremely complicated. This is because many constraints have to be taken into account

in a parameterized layout generator. It is here that the interconnectivity of geometric primitives

in layout design can expand the generators time to completion prohibitively, even though the

generator is heavily reusable. It is believed that this is the reason analog layout generators have

been restricted to simple circuit building blocks, such as capacitors and transistors in industry

standard IC environments, and not used to capture expert design in more complex circuits.

Expert based layout generators have the advantage of being able to cope with changes in

technology much easier then their algorithmic based counter parts. For instance, as CMOS

technology scales lower, digital layout is starting to see several constraints on its design [26],

making its design complexity like that of analog layout. When these advances in technology

happen, algorithmic layout generators must augment their current algorithms and add addi-

tional ones to cope with the added layout design difficulty. But because expert based generators

only worry about capturing expert design, and not actually doing it, they can cope easier with

technology change.

In the digital domain it is believed that an expert based layout design system would be

desirable in certain situations. A plethora of tools in this domain create more possibilities

of mixing and matching tools to attain layout solutions. Expert based layout generation can

be applied to digital domain through the building of expert designed, digital leaf cell layout

generators. A router and placer can then be used to construct layouts according to broad user

specifications, such as hardware description languages. This method would increase portability

of the generator over fully automated approaches, as place and route tools are found in every

industry standard design environment. This method is more complex then the fully automated

approaches to digital design, but offers the designer full control and show cases expert based

layout generator flexibility.

An expert based digital/analog layout generator, has been developed at Washington State

University by professor George La Rue. This generator, named LGen for Layout Generator, has

6

qualities that solve many of the problems with layout design and previous layout generators.

Some of LGen’s general qualities are stated below.

• LGen will be released under an open-source license and be uploaded to www.sourceforge.net,

a popular open-source project repository where it will get plenty of exposure. These two

factors will help prevent the before stated problem of re-implementation of common

ideas. This also makes LGen more useful as anyone can download, customize, and mod-

ify it to fit their specific needs.

• LGen is created with free, platform independent programming languages (ISO C++ and

Java). That combined with the previous item makes LGen highly portable, granting the

layout generators created with it the ability to be used anywhere by anyone.

• LGen can be used to create re-usable, process independent analog layout generators. Re-

ducing process migration problems and saving layout design time through layout reuse.

• LGen leverages hierarchical layout design to break up complex layout into more man-

ageable, modules. Good hierarchical design simplifies geometry interconnectivity.

7

Chapter 2

Introducing LGen

LGen is an expert design based layout generator for analog and digital layout. This chapter

will focus on the basic LGen system and the state of LGen before it was extended. LGen can

be broken up into a few distinct components.

• The LGen core

• Layout generators

• GUI interface

• Calibre rule extractor

These components will be discussed in more detail in the following sections.

2.1 The LGen Core

The LGen core is a collection of C++ functions and classes, all contained in a single source

and header file, that provide a geometry database for temporary storage of geometric primitives

and the ability to translate that database into a standard layout interchange format called CIF.

This file format can be read by all industry standard layout editors and tools. By utilizing a

simple interface to the database, and basing the dimensions of geometry on foundry design

rules, the developer (expert designer) can create mostly process independent layout genera-

tors. Re-usability of the generators is accomplished by generalizing them through the use of

parameters, such as wire widths or FET types.

LGen uses hierarchy much like that of popular layout editors. Layout geometry is encap-

sulated in a cell, and that cell can be referred to and placed in any other cell as many times

8

as is desired. Cells may also be rotated or mirrored across the x or y-axis. In layout creation

connections to and from any given cell are communicated through the use of ”ports”, which are

abstractions that assign string names to a coordinate and layer in a cell. This allows connec-

tions to be communicated through the hierarchy. The LGen database is capable of storing cells,

placing instances of them, and keeping track of ports. There is another way of keeping track of

cell interconnectivity in LGen. The port abstractions may be utilized, or the layout generator

which is generating the cell can keep track. This latter approach places all responsibility of

knowing the connections to and from the cell on the generator.

2.2 Layout Generators

Generators are created in C++ programs with the LGen database’s functional interface

included as a header file. A header file holding externally linked variables containing the

foundry design rules is also included. The LGen core and the design rule variables are separate

translation units and are usually statically linked with the generator binary. Externally declaring

the design variables in a header file guarantees that each translation unit can use the variables,

but that only one instance of them actually exists when all of the units are linked together.

Layout generators may be implemented as a function or a class. C++ classes are great

mechanisms for encapsulating and manipulating data related to a particular layout generator.

They allow a generator to, not only pass parameterized geometry to the database, but also to

keep track of various aspects of that geometry, such as but not limited to, cell interconnectivity.

On the other hand, generators implemented as functions have no elegant way of keeping track

of this information so the developer must use LGen’s interface to the database to recall ports

and thus connections to and from the cell.

Some early layout generators will now be discussed in more detail, all of them created by

Professor La Rue.

The FET generator is a C++ class that creates MOSFET layout. It was originally created

to support the development of a digital standard cell library. The generator was originally

implemented as a function, but moved to a C++ class to more adequately encapsulate FET

9

related data, such as cell interconnectivity and geometric translation. The generated FETs are

completely customizable. The width, length, and number of fingers of the generated FET can

all be set. Several special input methods also exist that simplify the code in the generators that

make up the digital standard cell library.

Annular, also known as ringed source or drain, and Gate-Around-Source/Gate-Around-

Drain (GAS/GAD) FETs are an application of radiation hard by design (RHBD) techniques

which refer to the radiation hardening of circuits through circuit design rather then through

special processes. These two generators have been developed in order to facilitate the creation

of well characterized RHBD FETs of fixed width and length. Due to the annular FETs circular

geometry and design rule minimum clearances, it is limited in how small of a width to length

ratio it can create. GAS/GAD FETs are of a slightly different design that allow small width

to length ratios without sacrificing radiation tolerance (See Fig. 2.1). These generators were

then used to create a rad hard library of digital standard cells that were in turn used in the

construction of a phase accumulator. This phase accumulator is discussed in more detail in

section 2.5.

(a) (b)

Figure 2.1: Annular (a) and Gate-Around-Source/Gate-Around-Drain (GAS/GAD) FETs (b).

Examples of Radiation Hard By Design (RHBD) techniques.

10

Examples of some digital gates in the normal and RHBD digital standard cell libraries can

be seen in Fig. 2.2.

(a) (b)

Figure 2.2: Standard cell NAND gates of varying width(a) and a RHBD latch (b)

2.3 The Calibre Rule Extractor

This facet of LGen is a terminal, command line program written in C++ that reads the user’s

Calibre DRC rule file and attempts to extract design rule values to fill LGen’s default design

rule variables. The program is not perfect and if it can not find a value for a particular design

rule variable, it will prompt the user to enter it in. Because CMOS processes are mostly alike

the default design rule variables cover mostly, if not all, required design rules for any given

process. The Calibre rule extractor makes it easier to switch to different processes and for new

users to take advantage of LGen by avoiding the tedium and error associated with entering in

every design rule manually.

11

2.4 The GUI Interface

After the initial generators were created a GUI was developed to provide layout designers

easy access to the expert designed layout generators. This would allow layout designers to

make use of LGen generators without knowledge of C++ programming or LGen’s internals.

It also allows the easy execution of peripheral programs like the Calibre Rule Extractor. The

GUI is written in Java and communicates with the C++ based LGen through a simple file API.

Once the generator is selected, the appropriate parameters entered, and the ”Generate” button

clicked, a script file is written by the GUI and is then interpreted by a C++ program which

passes the parameters to an appropriate generator. A screen shot of the GUI can be seen in

Fig. 2.3.

Figure 2.3: LGen GUI provides easy access to generators and the Calibre rule extractor.

2.5 An Early Application of LGen

One of the earlier applications of LGen was in the layout of a phase accumulator for a high-

speed direct digital frequency synthesizer (DDFS). DDFSs provide sinusoidal waveforms over

12

a wide range of frequencies up to the Nyquist rate with fast frequency hopping, high spectral

purity and high frequency resolution, which are required by many modern wireless commu-

nication systems [27]. The DDFS was intended for space-based applications, which require

both low power as well as radiation-tolerant circuitry. In the standard implementation of a

DDFS, the phase accumulator (PA) usually addresses a ROM look-up table to convert phase

to digital amplitude and then a digital-to-analog converter (DAC) was used to convert this to

an analog output signal. The design specifications were for a radiation-hard 32 bit PA oper-

ating near 2 GHz with less than 100 mW power dissipation using Jazz Semiconductors 0.18µ

BiCMOS process. The phase accumulator can be seen fully fabricated in Fig. 2.4. To address

the radiation requirements, RHBD techniques were used, including annular FETs and guard

rings. Triple-mode redundancy (TMR) with majority-voting circuitry was added to mitigate

the effects of single-event upsets (SEUs).

13

Figure 2.4: Phase accumulator manufactured in Jazz 0.18µ process. Early application of LGen

Rad Hard By Design FETs.

14

Chapter 3

The Extension of LGen

Three major modifications are made to LGen to support the layout design of two research

projects. Each modification will be discussed in turn in the following sections.

3.1 Making LGen Platform Independent

LGen was originally created with Microsoft Visual Studio. The decision to port LGen to a

GNU/Linux system was mostly based on preference. GNU/Linux was the preferred platform

to code in and there were only GNU/Linux workstations in the lab at the time. The closest

Microsoft Windows computers were in a public lab elsewhere in the building. In the process

of porting LGen to GNU/Linux all Microsoft only extensions to the C++ standard library and

language were removed while not introducing GNU/Linux extensions, making LGen more,

if not completely, ISO C++ compliant, and thus platform independent. LGen’s platform in-

dependence combined with its open-source license allows anyone, running any platform, to

download and use LGen when it is released as open-source software.

The LGen core was the most challenging piece of LGen to port. The goal was to port the

LGen core with as little change as possible. The porting process began with correcting header

file names by removing several ”.h” extensions and replacing ”string.h” with ”cstring”. There

were also a few header files exposing the Microsoft Windows API to the program; these were

all removed. Several minor replacements were made in the source file, which include changing

BOOL, FALSE, and TRUE to lower case, and replacing ”CString” to ”char*”.

15

The next problem to solve was the replacement of Microsoft specific containers such as

CObArray and CMapStringToOb with containers from the Standard Template Library (STL).

The STL is a subset of the sprawling ISO Standard C++ Library. The CObArray container is

an array of CObject pointers. The CObject class is a permanent base class in the Microsoft

Foundation Class Library (MFC). It extends a few helpful things to all classes that derive

from it, like serialization support and access to internal object diagnostic information [28]. All

containers in C++ must contain objects of the same type. By deriving classes from CObject

class, it is possible to make containers of type CObject and place in them any object one

desires. This freedom however comes at a price. It defeats C++ type checking and thus forces

the programmer to check the type of any object in the container manually and then dynamic

cast the object of type CObject to the appropriate type. Once this is done methods of the

derived type can be called and the object used as normal. This CObject class does not exist on

a GNU/Linux platform, so a bare bones CObject class was created and all classes in the LGen

core derived from it. Now any objects of these classes could be placed in a container of type

CObject pointer.

Once this was done STL containers ”vector” and ”map” were chosen to replace CObArray

and CMapStringToOb respectively. Vector contained pointers of type CObject and the map

contained types string and a CObject pointer. The map and CMapStringToOb containers are

also known as dictionary containers. They index their contents with hashable types, such as

integers or strings. In this particular instance given a string the container returns the corre-

sponding CObject pointer.

A simple ”C” array of CObArray containers were used in the Ccell class to keep track of all

items placed in that cell, including child cell instances. Three maps were used to hold various

attributes of the cell as well as a way of associating cell names to their object instantiations.

The attributes were indexed by their string names and used to store various characteristics of

the cell. They could contain coordinates, points, or an integer number.

16

The STL containers have a different interface then their Microsoft counterparts, so once

the STL containers were inserted, various parts of the program had to be rewritten to properly

interface with the new containers.

Once the core could compile cleanly on a GNU/Linux system, the rest of LGen was ported

as needed, and proved to be much easier to port then the core.

3.2 Capacitor Array Generator

The purpose of this generator is to create common centroid capacitor arrays for a high

accuracy, fully differential, 16-bit, charge redistribution, successive approximation analog-to-

digital converter (ADC). The main binary weighted array consists of a total of 163.8 pF for

each leg, 327.7 pF total. The total capacitance for the array is actually larger then this because,

in order to achieve capacitances lower then the minimum set by the process, many capacitors

had to be put in series. The ADC also has several calibration arrays for calibrating bits 7

through 16 in the main array. The generator is used to create the layout for all of these arrays.

The calibration, or trimming, array generators were created first. It was believed at the time

that an object oriented approach would be the best way to break up the design into more man-

ageable chunks of layout such as capacitors and quadrants. All tools pertaining to the wiring

and placing of the capacitors in the array could also be contained in the top-level capacitor

array class. A cell wrapper class was constructed that allowed cells to be placed and translated

easily in the new object oriented framework.

This framework only allowed capacitors to be placed within certain spacing requirements.

The spacing requirements were calculated to allow a single wiring channel between each ca-

pacitor. A method was added to the top level capacitor array class that wired the top or bottom

of any of the four sides of a capacitor on the grid, to any wiring channel metal layer. Once this

was done another method could be called that aided in the manual routing of that wire within

capacitor array’s wiring channels. Methods were also created that wired capacitors in the grid

in parallel or in series without disrupting the wiring channels.

17

The above helper methods in the generator helped simplify array creation, but even so,

large amounts of information had to be communicated to the capacitor array object, such as

where each capacitor goes along with where each wire went to connect the capacitors together.

If traditional object oriented techniques were followed, all this information would be located

outside of the object, with clean interfaces for adding this data to the object. Given the large

amounts of data needing to be communicated, all this information was contained inside the

capacitor array and quadrant classes. This sort of distortion of object oriented techniques sim-

plified the whole generator, as the data could be inserted where it made sense, at the cost of

code duplication when making new arrays. All capacitors and wiring that could be mirrored

into all four quadrants could be placed in the quadrant class. And all top-level wiring and

capacitors were placed in the main capacitor array class.

For this array a bit number could be given which would cause the generator to place the

correct common centroid arrangement of only the required capacitors for that bit number. Bit

11 placed all capacitors down, bit 10 placed all but the 11th bit capacitors, and so on. Dummy

capacitors were placed around the capacitors for every bit.

To create the main, differential array for the ADC the trimming capacitor array generator

was copied and modified. The application called for capacitors to be arranged around a centroid

and then that array mirrored around one common centroid. This resulted in four centroids

around one common one. This double centroid technique had the added ability to cancel out

not just first order, but some second order process gradients.

The added complexity of this generator actually fit well into the generators setup, and

little modification was needed to create this array. The generator, which consisted of 9072

capacitors, was completed in just two weeks. The whole array can be seen in Fig. 3.1, with a

zoom of one quadrant shown in Fig. 3.2.

It was found afterwards that a procedural, as apposed to object oriented, approach would

have been better for designing the capacitor array generators. The LGen database has a func-

tional interface. In order to deploy object oriented techniques this interface had to be wrapped,

resulting in code complication. A more elegant solution would have been to keep track of each

18

Figure 3.1: Main binary weighted capacitor array containing 9072 capacitors. Used for a fully

differential 16-bit ADC.

19

Figure 3.2: One quadrant of the main capacitor array of Fig. 3.1.

20

level of capacitor array data (capacitor widths, capacitor and wire locations within quadrants)

in C structs and create functions to modify and act on that data, rather then trying to encapsu-

late it completely in a class. This would also greatly reduce code duplication as the functions

would stay the same, only the data contained in each struct would change between each newly

constructed capacitor array.

3.3 Common Centroid FET (CCFet) Generator

This generator creates matched, common centroid FETs. Matched FETs are used in many

analog circuits such as op-amps, and primarily appear in differential circuits. This generator is

used to generate three pairs of FETs in op-amps that are in turn used in a 4th order, Butterworth,

low pass, low noise, switched capacitor filter. The design of this filter is discussed in detail in

chapter 4. The finished layout can be seen in Figs. 3.3 and 3.4. A close up of one of the input

pair, differential FETs to one of the four op-amps used in the filter can be seen in Fig. 3.5.

Figure 3.3: Entire layout of low pass, switched capacitor filter.

The creation of this generator posed many design challenges. To increase re-usability sev-

eral aspects are parameterized, greatly complicating the amount of constraints which need to

be taken into account to create layout that passes foundry design rule checks. As this generator

is not communicating connectivity with another generator, it is function based. This expedited

its completion in a timely manner. The generator takes the following parameters:

• Cell name (String identification for the LGen database)

• Fet type, ’p’, ’n’ or ’a’ for PFET, NFET, or Annular

• Diffusion width

21

Figure 3.4: The first of two stages of the filter shown in Fig. 3.3. The bias circuit can be seen

at the far left.

22

Figure 3.5: An input differential pair in one of the two op-amps shown in Fig. 3.4

23

• Gate length

• Number of fingers

• Drain and source wire widths

• Gate wire widths

To lower the overall complexity of the generator a grid of vertical and horizontal channels

are used by wires and FETs. Once the grid is established at the beginning of the program, the

rest is mostly just laying down geometry.

The generator uses the FET class to make the FETs in each mirrored quadrant around the

centroid. A simple interface is utilized between the two generators to simplify code construc-

tion and maintenance in each module.

3.4 FET Generator

The original FET generator was modified to be able to construct RHBD annular FETs. An

interface was also added to communicate with the CCFet generator. This allowed the CCFet

generator to be able to construct annular or normal FETs without having to know much about

the FET Class or how they were actually constructed. The interface consisted of methods that

returned coordinates of the top or bottom of gates and drains, and the top, bottom, left, and

right sides of the diffusion. Methods were also added to ”build” and ”draw” the FET. The first

method calculated all distances required for the interface and the second one actually relayed

the geometry to the database. This was done so that translation of the drawn geometry to the

database could be done by calling one method and without effecting geometry placement in

the parent cell. Because LGen utilizes a global translation scheme for all geometry uploaded

to it, this method was able to set the global translation, draw/build the FET and then undo the

global translation.

Annular FET characteristics are set in the same way as normal FETs, they just have slightly

different meanings. The type of FET is declared in the constructor of the class and the width,

length, and number of fingers are set by one method. For annular FETs the width parameters

24

sets how much longer the annular finger is then its minimum size. This has the effect of

stretching the annular FET finger. The length parameter is the same as a normal FET, setting

the width of the gate oxide. The number of fingers control how many annular gates are placed

on one diffusion.

Careful attention had to be given to the placement of the variable width, annular gate with-

out violating process design rules. The algorithm that achieves this takes into account the

minimum 45◦ bend length of smaller processes.

25

Chapter 4

Switched Capacitor Filter Application

4.1 The Surrounding System

A filter was designed as part of a second generation receiver chain for the ADC for which

the capacitor arrays were created in section 3.2. The original active, continuous filter had a

cutoff of 7kHz and worked to prevent anti-aliasing in a track and hold. The cutoff frequency

includes all the interesting frequencies of the biomedical signal that the filter was designed to

filter. The second generation’s primary purpose remains the same.

The goals of the new generation filter is lower noise, area, and power requirements then the

previous generation. The ADC has an input signal swing of +/- 2 volts. The cut-off is desired

to be sharper, so a 4th order filter will be created. In Table 4.1 a set of specifications for the

new filter is inferred from schematic simulations of the old one.

SNR is used to measure the noise between implementations as it is a better measure then

strait integrated noise given that the new filter is fully differential and has a better signal swing.

The target power requirements are higher then the previous generation because a 4th order

1st Gen. Target

Power (µW) 186.54 250

Area (mm2) .146 < .146

SNR (dB/bits) 40.74/6.48 = or >

Total Harmonic Distortion (bits) 11.31 > 12

Table 4.1: Target specifications for the next generation system.

26

system is desired. It should be noted that the target power is well below twice that of the

previous generation.

4.2 The Design

The full schematic design of the SC filter can be seen in Appendix A.

It should be noted that in order for a switched capacitor (SC) filter to perform as an anti-

aliasing filter, a continuous RC filter should be placed before, with a cut-off frequency at

Nyquist. This filters out noise above Nyquist that would alias into the passband by the fil-

ters sampling. For this design the sampling frequency was set to 500kHz to provide a high

Nyquist frequency, and thus lowering the area of the single pole RC filter.

A switched capacitor scheme was chosen to lower area and to enable a slightly tunable

cut-off frequency for the filter by adjusting the sampling frequency. Both filters were designed

to have a low cutoff of 7kHz. With such a low cutoff the advantages of a SC system over

continuous time in providing virtual, large resistors can be seen.

Typical design techniques were followed to design each biquad in the filter. Given the

sampling and cutoff frequencies and Q the capacitances of all capacitors in the circuit could

be found. The Q was set for each biquad according to a 4th order butterworth filter. What

is typically referred to as ”low Q” biquads were used for both stages. In order to produce a

maximally flat frequency response one Q is higher then the other. The high Q biquad amplifies

the signal around the cutoff, while the low Q attenuates below 0 dB. A by product of this is that

the high Q also amplifies the noise. Because of this the low Q biquad is usually placed after

the high Q to attenuate the noise. This was not done in this design because a 1st stage high Q

amplifies a full scale signal, increasing distortion at the cutoff frequency. The ramifications of

this decision can be seen in the noise spectrum in Fig. B.4, where a slight hump is seen at the

cutoff frequency of 7kHz.

The phasing of the switches in the biquads were arranged to reduce settling time by sepa-

rating or ”decoupling” the opamps. Thus charge is only applied to the succeeding integrator

once the intermediate capacitors are fully settled.

27

It was found that most of the components comprising the integrator could be placed into a

reusable symbol, simplifying the schematic. Switch sharing is utilized between the SC Com-

mon Mode Feed Back (CMFB) circuit and the following switched capacitor. The integration

capacitors are placed outside the symbol so that they can be varied without creating four differ-

ent subcircuits. The integration capacitors were set to 5 pF except in the 2nd stage of the first

biquad, where it was set to 2 pF. This second stage had the most capacitance to charge. Because

all switched capacitors in the second stage are computed relative to the integrator capacitor, by

setting it lower the required capacitance the opamp had to charge lowered as well.

The opamp was designed to be low power, have a SC CMFB, have a gain of 80 dB, and

have high enough bandwidth to provide enough settling time when charging capacitors in the

SC network. A folded cascode opamp was the chosen architecture. It was found that by

increasing the width of the input differential pair past 100µm increased the noise contribution

of the opamp. It was hoped that by increasing the width, the FET area and gm would increase

and thus lower 1/f and thermal noise. Reducing the gate resistance by increasing the fingers

also reduced their noise contribution.

A noise reduction technique called ”chopping” was utilized to lower the low frequency

noise contributions of the opamp to the rest of the filter. Chopping is implemented in the

circuit by swapping the inputs and outputs of any stage of a fully differential opamp at the

end of the sampling clock frequency. This is implemented with FET switches and another

pair of differential clocks that are set to half the sampling frequency and to change when both

sampling clocks are low. It was found that by utilizing chopping total integrated output noise

for the filter improved by 39.4%. By chopping only the 1st stage of the opamp, as opposed to

chopping the whole opamp, it was found that the total noise was reduced the most.

A single pole RC filter with a cutoff of 15kHz was placed at the end of the filter to filter out

high frequency noise. This improved the output noise as the filter output was sampled with an

ideal sample and hold.

28

4.3 Results

Cadence schematic simulations of both generations of filters were used for comparison. As

the second generation filter is SC, a typical AC and NOISE analysis will not be effective in

computing the periodic transfer function and noise. Thus Spectre’s PSS, PAC, and PNOISE

analysis were used. PSS analysis linearizes the circuit about the periodically time-varying

operating point. The PAC and PNOISE analysis then use this operating point to find the circuit

behavior when stimulated by a small sinusoidal signal of any frequency. Parallels can be seen

between PSS, PAC, and PNOISE and the typical DC, AC, and NOISE analysis respectively.

An ideal-sample-and-hold on the output was a requirement of the PNOISE analysis.

The following Spectre analysis were used to find each specification for the new filter in

Table 4.2.

PSS Periodic Steady State; precursor analysis to PNOISE or PAC.

PNOISE Computes periodic noise. Used to find the output noise spectrum and the integrated

noise.

PAC Periodic AC analysis. Used to find the transfer function of the filter. Which in turn is

used to find the passband gain and cutoff frequency.

TRAN Transient analysis. Used to check settling time throughout the filter. Total harmonic

distortion was computed from the transient output voltage. Total average current for the

filter was also found from this analysis.

The power requirement was almost met by the 2nd generation filter. Consider that by

cascading the 1st generation filter to make it 4th order, it would consume 31.4% more power

then this design.

The 2nd generation passband gain and the cutoff frequency for the filter’s nominal 500kHz

sampling frequency are shown in Fig. B.1. The filter transfer function for various sampling

frequencies can be seen in Fig. B.2. A graph of the cutoff vs sampling frequency can be

seen in Fig. B.3. It was found that at 1 MHz the output signal only settled to about one time

29

1st Gen. 2nd Gen.

Power (µW) 186.54 255.9

Cutoff (kHz) 6.88 6.85

Passband Gain (mdB) .14 54.3

Area (mm2) .146 .113

Noise(

µV√Hz

)71.2 104.8

SNR (dB/bits) 40.74/6.48 42.8/6.82

Total Harmonic Distortion (bits) 11.31 12.76

PSRR VDD (Hz/dB) 10/-101 250k/-21 10/-187 250k/-245

PSRR VSS (Hz/dB) 10/-115 250k/-64 10/-180 250k/-213

Table 4.2: Compared specifications between the old and new filter generations. These results

were gathered from plots that can be found in Appendix B.

30

constant. Because the filter was designed for low power, the filter has enough settling time for

the designed sampling frequency of 500kHz, but not over. Realistically the sampling frequency

can not be adjusted above 500kHz, limiting the adjustment of the cutoff frequency to below

7kHz. Designing the opamp with higher power requirements would provide higher sampling

frequencies, and thus higher cutoff frequency ranges.

The output noise spectrum is shown in Fig. B.4. The SNR was computed for each filter by

using its full scale RMS voltage for the input signal. The full scale voltage for the 1st and 2nd

generations were 1.3 and 2 Volts respectively.

The PSRR for each rail was found for both filters up to 250kHz. It is not surprising that the

2nd generation’s fully differential design has a much better PSRR.

In conclusion, the 2nd generation filter adhered well or surpassed its targeted specifications.

Although better noise performance was desired.

31

Chapter 5

The Future of LGen and Layout Generation

In this chapter the various future improvements to LGen will be discussed as well as what

is believed to be the ideal layout generation system.

5.1 The Future of LGen

Before LGen is ready for public release a few things must happen. First of all its documen-

tation must be updated. Good documentation is of utmost importance to a layout generator or

any project. It increases the likelihood of someone else successfully using the generator and

decreases the amount of time spent learning how to use it.

Secondly some of the newer aspects of LGen must be tested more extensively and also

made more robust, such as the Calibre Rule Extractor and the Java GUI interface.

It is also desired that design rule checking and possibly more automation, such as wire rout-

ing, be incorporated into LGen before its initial release. To accomplish this LGen’s geometry

database must gain the ability to find and modify geometric primitives. Right now the database

is a one-way street, with geometry going in and not being retrieved. When LGen was being

created this design made sense as generators would be executed, give geometry to the database,

request its output in CIF, and then terminate.

The longterm goals of this project are to improve the existing generators and to add more

complicated ones such as op-amp generators.

32

5.2 The Future of Layout Generation

It was argued in section 1.2 that an expert based system is the best road to travel towards

solving the Layout Problem. But an expert design based system is not enough, many details that

effect its performance and adoption in an industry environment must be properly implemented.

Some key aspects of a good expert based layout generator are listed below.

• Ability to integrate well into current integrated circuit design pipelines in the industry.

• The generator is known and accessible to those who need it.

• It is easy to adapt existing and new expert designed layout to new technology nodes and

perhaps completely new technologies and materials.

• The generator itself is easy to add on to and maintain.

• The generator and its expert designed layout is portable across many computer architec-

tures and operating systems.

• It captures expert design easily and efficiently and it is reusable.

The last item entails a lot. The word ”reusable” implies that the captured expert layout

design is portable across processes and can be changed and added to easily post design. Most

expert based layout generators implement this aspect well by their very nature.

Easily and efficiently implies that an expert designer can design the layout without being

too encumbered with menial details. The downfall of many expert based layout generators,

as mentioned in section 1.4, is that the creation of these generators becomes prohibitively

complicated. LGen tries to mitigate this problem by leveraging hierarchical layout design to

break up complex layout into more manageable, simpler modules.

It is believed that expert based generator design could be simplified further if a system was

developed that could take care of the small details, such as the foundry design rules, and leave

the designer free to think more on top-level design such as how to arrange the clock lines to

minimize feed-through. It is believed that such a system should focus on the resolution of

foundry design rules, with a narrow selection of what else to automate (such as wire routing),

33

to increase its generality. This will allow the system to adapt easier to new design rules in lower

technologies nodes.

After creating several expert design based layout generators it is my belief that a constraint

based geometry database is the best avenue for this field. In this system there would be relative

spacing between each primitive represented by a construct called a constraint. Constraints are

elastic spacers between geometric primitives which would contain the appropriate minimum

or maximum spacing requirements between those primitives. The constraint would receive

this information at insertion from a separate database object containing all relevant foundry

design rules for that technology. The constraint would not allow spacing to fall below the min-

imum spacing requirements as given in the design rules. The constraints would be collectively

resolved in a compaction algorithm at the end of the design.

Constraints could be inserted manually as directed by the expert designer, or automatically

through more general commands. Such a system could make use of broad functions to facilitate

layout, such as overlap the group ”FET1” by n-implant, without overly complicated code.

The complete design of a system of this magnitude falls outside the scope of this thesis,

and thus, not all design flaws and hurdles can be foreseen and corrected. However I see two

hurdles that need to be overcome in order for this system to be viable.

One hurdle is how to handle hierarchical layout design in an efficient manner during com-

paction. A hierarchical based system is desired as it is a good way of encapsulating portions

of layout for reuse in larger layout designs. It would also allow the system to compact a cell

by itself and then that compacted cell not be touched by the algorithm again in the rest of the

layout, increasing the speed of compaction. This methodology gives rise to the problem of

how to handle interfacing between whole cells and the rest of the layout, be that other cells or

geometric primitives. The constraints between geometric primitives in the cell and other lay-

out would change each time the cell is inserted into another portion of the layout. This could

be remedied by letting each constraint, which attaches to a primitive in a cell, know the cell

type and name. This way the same cell can be used throughout the layout and the compaction

algorithm can differentiate between each cell and its surrounding layout.

34

Another hurdle to overcome is in how the compaction algorithm will know and resolve

constraints interdependencies. It is known from experience that in layout several constraints

can be interdependent and that, when resolving them, all must be considered at one time. The

algorithm will have to go through the layout first and find these constraint dependencies before

compaction can begin.

It is believed that these hurdles can be overcome and that constraint based layout generation

can be a viable solution.

35

Chapter 6

Conclusions

Throughout integrated circuit history layout generators have been used to ease the burden

of layout design. Most of these generators either did not make it far from the labs of their

invention, or were far from ideal solutions, and this was due to several factors discussed in

section 1.3, such as lack of exposure, licensing that did not serve the customer, cost, and many

other factors that effected geometry reuse, such as generator portability and lack of process

independence.

In order for a generator or any layout tool to solve the Layout Problem in any sort of

meaningful, industry wide way, these detrimental factors must be solved. No layout generator

is perfect, but with LGen, many of these issues have been dealt with.

Several valuable extensions were made to LGen. Its portability was increased by porting it

to a GNU/Linux platform, and by doing so, making it ISO C++ compliant. Another generator

was created that aides in the completion of capacitor array layout, which is used in many

analog-to-digital and digital-to-analog converters, as well as tunable filters.

A common centroid FET generator was added to LGen, a critical component used in the

layout of many differential, analog circuits. This generator was then used to aid in the layout

design of a SC filter, of which its circuit design successfully met specifications.

36

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[28] Visual C++ Developer Center. Microsoft Corporation. http://msdn2.microsoft.com/en-us/library/7k3448yy(VS.80).aspx, July 2007.

39

Appendix A:Switched Capacitor Filter Schematics

40

Figure A.1: Toplevel test bench circuit diagram.

41

Figure A.2: The entire 4th order filter design.

42

Figure A.3: Bias circuit for opamp and opamp’s reference SC CMFB voltage

43

Figure A.4: 1st stage biquad which has the lowest Q.

44

Figure A.5: 2nd stage biquad which has the highest Q.

45

Figure A.6: Integrator unit which contains the opamp and part of the SC CMFB circuit.

46

Figure A.7: Low power opamp with only the continuous time part of the SC CMFB included.

47

Figure A.8: Last stage RC filter used to filter out noise before the ideal sample and hold.

48

Appendix B:Switched Capacitor Filter Results

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Figure B.1: Transfer function of the filter. The passband gain and cutoff frequency for the filter

is shown.

50

Figure B.2: Filter transfer function when using various sampling frequencies.

51

Figure B.3: The cutoff frequency vs. the sampling frequency.

52

Figure B.4: The output noise spectrum in dB (Top) and Volts (Bottom).

53

Figure B.5: Power supply rejection ratio for the positive and negative rails.