LAYOUT DESIGN RULES

EMT251

LAYERS

DESIGN RULES

DESIGN RULES

DESIGN RULES

DESIGN RULES

DESIGN RULES

DESIGN RULES

Design Rule Checkers (DRC)

Goal: identify design rule violations General approach: “scanline” algorithm Computationally intensive, especially for

large chips

Design Rule Checkers (DRC)

poly_not_fet to all_diff minimum spacing = 0.5 lambda.

Layout Versus Schematic (LVS)

Goal: Compare layout, schematic netlistsCompare transistors, connections (ignore

parasitics) Issue error if two netlists are not equivalent Important for large designs

Layout Versus Schematic (LVS)

.subckt inv in outMN1 Out In GND GND n L=0.4u W=1u MN2 Out In VDD VDD p L=0.4u W=1u.ends inv=

InOut

VDD

GND

Area Estimation

In

Out

GND VDD

Length

Width

Area = Length x Width

The Challenge of Design Start: higher level (spec) Finish: lower level (implementation) Must meet design criteria and constraints

Design time - how long did it take to ship a product?

Performance - how fast is the clock?Cost - NRE (Non-Recurring Engineering) +

unit cost CAD tools - essential in modern design