Lattice Mico32
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Transcript of Lattice Mico32
Technical Seminar Tour 2006 - Page 1LatticeMico32
Technical Seminar Tour 2007
LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS
LatticeMico32
Technical Seminar Tour 2006 - Page 2LatticeMico32
LatticeMico32
Agenda
Architecture and Peripherals
Development tools
Software Deployment
Tool Flow
Demo
Technical Seminar Tour 2006 - Page 3LatticeMico32
Introducing the LatticeMico32
Flexible, High Performance 32-Bit Microprocessor
Optimized For Lattice Leading-Edge Families– LatticeEC/P– LatticeECP2/M– LatticeSC– LatticeXP
Targeted Towards Wide Variety of Applications– Consumer– Computation– Communications– Medical– Industrial– Automotive
Technical Seminar Tour 2006 - Page 4LatticeMico32
Performance Enhanced Feature Set
RISC architecture
32-bit data path and 32-bit instructions
32 general purpose register
Handles up to 32 external interrupts
Optional instruction and data caches
Dual Wishbone memory interfaces(Instruction and Data)
Technical Seminar Tour 2006 - Page 5LatticeMico32
Architecture
Technical Seminar Tour 2006 - Page 6LatticeMico32
Architecture and Pipeline Stages
Technical Seminar Tour 2006 - Page 7LatticeMico32
Peripheral Components
Enable Design of Complete Embedded Systems
Connect via a WISHBONE Bus Interface– Royalty-free
– Public domain specification controlled by OpenCores.org
Technical Seminar Tour 2006 - Page 8LatticeMico32
Peripheral Components
Broad Selection– Coming from Lattice
» Asynchronous SRAM Controller
» On-Chip Memory Controller
» 32-bit Timer
» DMA Controller
» GPIO
» I2C Master Controller
» SPI
» UART
» DDR ($)
– OpenCores.org» There is a real documentation coming from Lattice
how to create and add wishbone-compatible componentsto the LatticeMico32 development system!!!!
Connectivity With a Click Using Design Tools
Technical Seminar Tour 2006 - Page 9LatticeMico32
Complete Embedded System
Flash/ RAM
FPGAConfig
LatticeMico32Processor
Core
On-ChipMemory
UARTFlash Memory
ControllerGPIO
32-bitTimer
SRAMController
WISHBONE
Interrupt Lines
FPGA
User Logic
EmbeddedRAM
Technical Seminar Tour 2006 - Page 10LatticeMico32
Support Timetable By Device Family
Schedule for Family Support:– LatticeEC/ECP/ECP2/M Now
– LatticeSC November 2006
– LatticeXP January 2007
Technical Seminar Tour 2006 - Page 11LatticeMico32
Resource Utilization & Performance
Configuration Family LUTs Maximum Clock Frequency
BASICNo Multiplier
1 Cycle Shifter
No Cache
LatticeEC/ECP 1830 81 MHz
LatticeECP2/M 1571 98 MHz
StandardMultiplier
3 Cycle Shifter
8K I-Cache, No D-Cache
LatticeEC/ECP 2040 89 MHz
LatticeECP2/M 1816 116 MHz
FullMultiplier
3 Cycle Shifter
8K I-Cache, 8K D-Cache
LatticeEC/ECP 2230 92 MHz
LatticeECP2/M 2158 116 MHz
Technical Seminar Tour 2006 - Page 12LatticeMico32
Open IP Core Licensing
Innovative Open IP Core License– Visibility, Reliability, Scalability
Free of Charge
Generated LatticeMico32 core and Peripherals based on HDL
Technical Seminar Tour 2006 - Page 13LatticeMico32
Development Tool
LatticeMico32 System
to implement HW-IP (uP and Peripherals) and SW
Based on Eclipse C/C++ Dev. Tools (CDT)
Free of charge, via Internet
Combined with ispLEVER
Technical Seminar Tour 2006 - Page 14LatticeMico32
Development Tool
LatticeMico32 System
Mico System Builder (MSB)– Generate uP platform and HDL
– Choose peripherals
– Specify connectivity between peripherlas
C/C++ SW Projekt Environment (SPE) and Debugger
– Eclipse development environment
– GNU-based compiler, linker, assembler, debugger
Technical Seminar Tour 2006 - Page 15LatticeMico32
RTOS Support
Micrium’s uC/OS-II RTOS
Included in LatticeMico32 System
Open source
free of charge for eval and non-commercial use
For commercial-use obtain a license directly from Micrium
Technical Seminar Tour 2006 - Page 16LatticeMico32
Software Deployment
Deploying to
External Parallel Flash
On-Chip (Embedded Block RAM EBR)
Technical Seminar Tour 2006 - Page 17LatticeMico32
Software Deployment: External #1
Load app.design toFPGA config flash
FPGA configurationvia SPI
ELF
FPGAConfig Flash
LatticeMico32 System
FPGA
JTAG UART
OnChip Mem (EBR)
User Logic
Parallel Flash
SRAM / DDR
PC(Debugger,
ispVM)
BIT
BIT
SPI
Technical Seminar Tour 2006 - Page 18LatticeMico32
Software Deployment: External #2
multipleLoad app.code to RAM
Run app.code from RAM
debugging
ELF
FPGAConfig Flash
LatticeMico32 System
FPGA
JTAG UART
OnChip Mem (EBR)
User Logic
Parallel Flash
SRAM / DDR
PC(Debugger,
ispVM)
BIT
BIT
SPI
ELF
Technical Seminar Tour 2006 - Page 19LatticeMico32
Software Deployment: External #3
Load FlashProgrammerto RAM
Run FlashProgrammerfrom RAM
ELF
FPGAConfig Flash
LatticeMico32 System
FPGA
JTAG UART
OnChip Mem (EBR)
User Logic
Parallel Flash
SRAM / DDR
PC(Debugger,
ispVM)
BIT
BIT
SPI
Flash
Programmer
Flash
Programmer
Technical Seminar Tour 2006 - Page 20LatticeMico32
Software Deployment: External #4
FlashProgrammercopies app.code toParallelFlash
ELF
FPGAConfig Flash
LatticeMico32 System
FPGA
JTAG UART
OnChip Mem (EBR)
User Logic
Parallel Flash
SRAM / DDR
PC(Debugger,
ispVM)
BIT
BIT
SPI
ELF
Flash
Programmer
Flash
Programmer
Technical Seminar Tour 2006 - Page 21LatticeMico32
Software Deployment: External #5
Copy app.code toRAM
Run app.code fromRAM
FPGAConfig Flash
LatticeMico32 System
FPGA
JTAG UART
OnChip Mem (EBR)
User Logic
Parallel Flash
SRAM / DDR
BIT
SPI
ELF
ELF
Technical Seminar Tour 2006 - Page 22LatticeMico32
Software Deployment: OnChip #1
Load app.design toFPGA config flash
FPGA configurationvia SPI
ELF
FPGAConfig Flash
LatticeMico32 System
FPGA
JTAG UART
OnChip Mem (EBR)
User Logic
PC(Debugger,
ispVM)
BIT
BIT
SPI
Technical Seminar Tour 2006 - Page 23LatticeMico32
Software Deployment: OnChip #2
multipleLoad app.code to EBR
Run app.code from EBR
debugging
ELF
FPGAConfig Flash
LatticeMico32 System
FPGA
JTAG UART
OnChip Mem (EBR)
User Logic
PC(Debugger,
ispVM)
BIT
BIT
SPI
ELF
Technical Seminar Tour 2006 - Page 24LatticeMico32
Software Deployment: OnChip #3
Resynthesize FPGAbitstream
Load app.design toFPGA config flash
FPGA configurationvia SPI
ELF
FPGAConfig Flash
LatticeMico32 System
FPGA
JTAG UART
OnChip Mem (EBR)
User Logic
PC(Debugger,
ispVM)
BIT
BIT
SPI
Technical Seminar Tour 2006 - Page 25LatticeMico32
Software Deployment:
This are just very simplified descriptions
Please have a look to: LatticeMico32 Tutorial
(based on the Lattice32 Development Board)
SW Developers UserGuide
Technical Seminar Tour 2006 - Page 26LatticeMico32
ECP Development
Development Board– LatticeECP 33 + SPI– DDR SODIMM socket – 2x128 Mbit Flash + 2x4 Mbit SRAM – USB 2.0 Connector for programming – Flywire Connector for programming– 9-pin RS232 serial port– 15-pin VGA connector for 64 colors– Ethernet 10/100 M full/half duplex– Multiple USB connectors– Sigma Delta D/A converter– Audio interface (line-in and line-out) – LCD connector for character displays– 25 MHz oscillator– Two-character 7-segment display
Power Supply, USB Cable
595 $
Technical Seminar Tour 2006 - Page 27LatticeMico32
Software Deployment
Deploying to
External Parallel Flash Memory
Embedded Block RAM (EBR)
Alternatives:
External Parallel Flash Memory = ConfigFlash(needs a small CPLD)
External SPI Flash(coming soon)
Technical Seminar Tour 2006 - Page 28LatticeMico32
System Development Flow
Mico System Builder (MSB)
Platform Development Software Development
FPGA DesignImplementation
Generator
Instruction Set
Simulator
HW Platform
Rest of User Design in HDL
ELFHDL
.h
Debug
Target Board
Debug
ProgramispVM™
C/C++ Software Project Environment (SPE) and
Debugger
Technical Seminar Tour 2006 - Page 29LatticeMico32
System Development Flow
Restriction:(not really ;-)
MSB delivers Verilog– But ispLEVER does not support mixed language designs
– Do you speak Verilog ??
-> use NGO-Flow
How?? Ask your AVM-FAE
Technical Seminar Tour 2006 - Page 30LatticeMico32
LatticeMico32 Tool Flow
Create New project, – Verilog HDL,
– part type ECP33-3F484C if Mico32 dev board is used
Technical Seminar Tour 2006 - Page 31LatticeMico32
Tool Flow
Invoke Mico32 from IspLever
Technical Seminar Tour 2006 - Page 32LatticeMico32
Tool Flow
Create a Platform:– Platform is processor + peripherals
– Pre-defined Platforms or create your own
– Platforms A-E match the LatticeMico32 development board
Technical Seminar Tour 2006 - Page 33LatticeMico32
Tool Flow
Configure Platform – Configurations (e.g. Peripheral name, Wishbone connections,
Memory location, size, interrupts, etc) are specified here
Technical Seminar Tour 2006 - Page 34LatticeMico32
Tool Flow
Configure processor or peripheral:– Double click instance name, and configuration options
appear
Technical Seminar Tour 2006 - Page 35LatticeMico32
Tool Flow
Generate Platform– Addresses, Irq, DRC, Generate HDL
Technical Seminar Tour 2006 - Page 36LatticeMico32
LatticeMico32 Tool Flow
Importing an LM32 Project– <path>/<project>/soc/<project>.v
–
Technical Seminar Tour 2006 - Page 37LatticeMico32
Tool Flow
Importing Development board constraints– “Source” “import constraint/preference file”
– <isptools6.1>/micosystem/platforms/platformxy
– Pinouts for SRAM, LED’s, etc.
Technical Seminar Tour 2006 - Page 38LatticeMico32
Tool Flow
Change Perspective from ‘MSB’ to “C/C++”–
Technical Seminar Tour 2006 - Page 39LatticeMico32
Tool Flow
Using the SPE Environment– ‘New “Mico32 New Managed C project”
–
Technical Seminar Tour 2006 - Page 40LatticeMico32
Tool Flow
Using the SPE Environment– Select a template
Technical Seminar Tour 2006 - Page 41LatticeMico32
Tool Flow
Using the SPE Environment– Compile C Code
– Make utility will compile source
– Check for errors
Technical Seminar Tour 2006 - Page 42LatticeMico32
Tool Flow
Using the SPE Environment– Execute C Code
– Select ‘Run’ ‘debug – mico32 hardware’
– The demo board can now be executed
Technical Seminar Tour 2006 - Page 43LatticeMico32
LatticeMico32 Website
http://www.latticesemi.com/products/intellectualproperty/ipcores/latticemico32.cfm
Technical Seminar Tour 2006 - Page 44LatticeMico32
Detailed LatticeMico32 Documentation
LatticeMico32 Processor Reference Manual
LatticeMico32 Software Developer User's Guide
LatticeMico32 Development Kit User's Guide
LatticeMico32 Tutorial
Online Help– Workbench
– MSB
– C++ Debug
Sparkle Sheet
LatticeMico32 System Installation Guide
Creating Components in the LatticeMico32 System
Peripheral Component Data Sheets and Help Panels
– DMA Controller– GPIO– I2C Master from OpenCores– On-Chip Memory Controller– SPI– Asynchronous SRAM Contro
ller– Parallel Flash Controller– 32-bit Timer– UART
Technical Seminar Tour 2006 - Page 45LatticeMico32
Recommendation: LatticeMico32 Tutorial
~ 3 Hours for completion
Based on LatticeMico32 Dev. Board
Technical Seminar Tour 2006 - Page 46LatticeMico32
Development Board
Development Board– LatticeECP 33 + SPI– DDR SODIMM socket – 2x128 Mbit Flash + 2x4 Mbit SRAM – USB 2.0 Connector for programming – Flywire Connector for programming– 9-pin RS232 serial port– 15-pin VGA connector for 64 colors– Ethernet 10/100 M full/half duplex– Multiple USB connectors– Sigma Delta D/A converter– Audio interface (line-in and line-out) – LCD connector for character displays– 25 MHz oscillator– Two-character 7-segment display
Power Supply
USB Cable
595$