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Latch-up

Dr. Rama Komaragiri

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16: Circuit Pitfalls Slide 2

Latchup

Latchup: positive feedac! leadi"g to #DD$ %&D short 'a(or prolem for 1)*+,s C'S processes

eforeit as ell u"derstood

/void 0 mi"imii"g resista"ce of od0 to%&D #DD

3se ple"t0 of sustrate a"d ell taps

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tapwell tap

n+ p+

n wellRsub

Rwell

Vsub

Vwell

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Latch up 3

Latchup i" C'S Circuits

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Latch-3p

41 is a vertical doule emitter p"p tra"sistor 5ase is formed 0 the "-ell ith a high ase to collector

curre"t gai" P&P7

42 is a lateral doule emitter "p" tra"sistor ase is formed 0 the p-t0pe sustrate ith gai" &P&7

R.ellreprese"ts the parasitic resista"ce i" the "-

ell structure hose value ra"ges from 1!to2+!.

sustrate resista"ce Rsudepe"ds o" the sustratestructure.

Q1

Q1

Q2

Q2

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Latch-3p

%e"erall0 are R.ella"d Rsuare sig"i8ca"tl0 large Li!e ope" circuit co""ectio"s

thus lo curre"t gai"s a"d t0pical curre"ts ould e

reverse lea!age curre"ts for oth the "p" a"d p"ptra"sistors

Due to some e9ter"al distura"ce if the collectorcurre"t of o"e of the parasitic tra"sistors to

i"creases the resulti"g feedac! loop causes thecurre"t perturatio" to e multiplied 0 P&P.&P&

Circuit is i" positive feedac! mode a"d fails

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Latch-up

ccurs 0 estalishi"g a lo-resista"ce paths

co""ecti"g #DD

to #SS

;9ter"al distura"ce: 'a0 e i"duced 0 poersuppl0 glitches or i"cide"t radiatio"

os #5;of

&P& device i"creases collector curre"t i"creases curre"t through R.elli"creases. #5;of P&P device

i"creases further i"creasi"g sustrate curre"t.

Latch up 6VBE

VBE

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Latch up 7

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Latch-up

?he" ac! to ac! 5@As satisf0 BP&P9 B&P& 1 latch-up ma0 occur

peratio" voltage of C'S circuits should e elolatch-up voltage

Remedies of latch-up prolem: Reduce Rsu0 i"creasi"g P dopi"g of sustrate

0 process co"trol

Reduci"g Rella"d resista"ce of ?;LL co"tacts 0

process co"trol. La0out tech"iues: separatio" of P a"d & devices

guard ri"gs ma"0 ?;LL co"tacts at desig"7.

Latch up 8

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16: Circuit Pitfalls Slide )

%uard Ri"gs

Latch-up ris! greatest he" diEusio"-to-sustratediodes could ecome forard-iased

Surrou"d se"sitive regio" ith guard ri"g tocollect i"(ected charge

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Latch-up Some causes for latch-up are:

Slei"g of #DDduri"g start-up causi"g e"oughdisplaceme"t curre"ts due to ell (u"ctio"capacita"ce i" the sustrate a"d ell.

Large curre"ts i" the parasitic silico"-co"trolledrecti8er i" C'S chips ca" occur he" the i"put

or output sig"al si"gs either far e0o"d the #DDlevel or far elo #SSlevel i"(ecti"g a triggeri"g

curre"t.