LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr … · 2017. 11. 10. ·...
Transcript of LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr … · 2017. 11. 10. ·...
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LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr Calorimeter
Mitch Newcomer On Behalf of the ATLAS LAr Calorimeter Group*
*Special Acknowledgment of the significant contributions of Emerson Vernon, Sergio Rescia (BNL) and Nandor Dressnandt (Penn) to this work.
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FEE Design Constraints / Goals for a LArBarrel Calorimeter at SLHC
Low NoisePreamplifier
t i(t)
Physics Requirement•Dynamic energy range: 20MeV - 2 TeV, •Good energy resolution•Minimize Pileup
Drift time 400ns. Signal 25ns rise (1nF 25Ω rin), 400ns fall. Readout Dynamic Range ~16 BitsNoise referred to input. ENI < 75nA RMS
CR – (RC)2
1X10X
ADC40MSps
GainSelector
LAPAS ASIC
FEE Rad Tolerance TID~ 300Krad, Neutron Fluence ~1013 n/cm2
Zin =Z0
~5m, Z0 = 25Ω
Cdet ~1nf
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SiGe Bipolar Technology
*SiGe technology was first introduced to the HEP community by John Cressler :Assessing SiGe HBT Technology For Front-end Electronics Applications5th International Meeting on Front-end Electronics Snowmass, CO, June 2003
Strained Lattice (Si-Ge)• Epitaxial Ge film in base layer.• Increases base emitter band gap for holes.• Improves Radiation Tolerance.• Reduces recombination in the base.• Increases mobility High ft• Excellent Low temp gain stability.• Allows higher doping in base.
Lowers rbb’
*EDN 9/18/2008 credited to IBM
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IBM 8WL SiGe BiCMOSPro’s
– Excellent Bipolar Analog performance. Possible to use Vdd > 5V– Excellent radiation hardness well beyond requirement. – IBM support for the foreseeable future ( > 5 years)– CMOS Digital Libraries in use for other CERN projects should be available for use
with these BiCMOS processes.– 8WL is the least expensive 130nm SiGe bipolar process available from IBM.
Con’s– No PNP’s. Must use PMOS. – Complex process design rules. – Potential increased (npn) SEU susceptibility compared with 8HP– More complex process than CMOS which has a significant cost premium.
(May be reduced as competitive processes come online.)
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FEE LAr Signal Processing
All RC = 15ns Sampled at40MSPS
Z0
Zin = 25Ω
Shaping Primarily dependent on ASIC Passive elements
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Predicted Precision of SiGe Process Passive Shaping Elements
Mim Cap Values from MC
02468
10121416
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7
Capacitance ( Target =5pF)
RMS Variation 3.3%
8WL RP Resitance Distribution 6 X 30um
02468
1012141618
1000
1010
1020
1030
1040
1050
1060
1070
1080
1090
1100
1110
1120
1130
1140
1150
1160
1170
1180
1190
1200
1210
1220
1230
1240
1250
1260
1270
1280
1290
1300
Ohms
RMS Variation 2.9%
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Calculated Shaper Signal Variation
0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns 500ns-200mV
-100mV
0mV
100mV
200mV
300mV
400mV
500mV
600mV
700mV
800mV
900mVV(n005)
Amplitude Variation CR-(RC)2 MC runDue to passive Shaping Components
0
2
4
6
8
10
12
0.7 0.72
0.74
0.76
0.78 0.8 0.82
0.84
0.86
0.88 0.9 0.92
0.94
0.96
0.98 1
Amplitude Arb Units
RMS Variation 3.5%
May not be necessary to tune each channel to stay within a 5% Channel to Channel gain requirement for trigger sums.
Due to Spread in Passive Shaping Elements
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SiGe LAr Preamp (Rin=25Ω)
PFET33L=.5u W=68u m=5
NPN Emitter 20,.12uM=4NPN Emitter 20,.12u
M=4
NPN Emitter 20,.12uM=4
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Operational Characteristics(Simulation Results)
Real Zin Transfer Function
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Calculated Preamp and Shaper Noise Contributions
(Preamp ENI = 66.4nA)
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Input Referred Preamp Noise Contribution (Calculated)
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Prototype Shaper Design Goals
• 2.2nV / √Hz ( Adds 10% to Preamp noise)*• 15 - 16 bit Dynamic range, Less than .1% INL*
(Necessary to use Dual or Triple ranges)• Low Power 100 – 200 mW*• Part to part amplitude variation < 5%• Should be easily matched to a differential ADC
*Competing goals
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Shaper BlocksRC
CR
RC
*
*
*
~2.4nV / √Hz150mW
5V
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Input OTA Block
CascodedPMOS mirrors
ODF_AODF_B
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Voltage output Driver
1.8mA
Turns OTA back into Opamp
Outputs of OTA
OPAmp Output
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Common Mode AmpUsed to set Common Mode voltage at output of Op Amp.
OTA OutCommonMode Point
OTA outputs
ReferenceVoltage
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Open Loop Response Layout Extracted AC OPAmp(Includes external 5pF feedback caps)
Gain ~350
Phase
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Circuit Blocks LAPAS4 Preamps, 2 Shapers (1X &10X)
Gain X10(RC)2 – CR D
river
Preamp
Gain X1(RC)2 - CR D
river
Preamp
Preamp
Preamp
Gain X10(RC)2 – CR D
river
Gain X1(RC)2 - CR D
river
0-5mAinput 0-3V
PA out
0-3V diff Output
0-3V diff Output
vdd
vdd
gnd
gnd
No InputProtection
No InputProtection
LAPAS: Liquid Argon PreAmplifier Shaper 8WL process ASIC 2100 X 1800um
Preamp
PreampPreamp
Preamp
Shaper 1X
Shaper 1X
Shaper 10XShaper 10X
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Measurements with Hand Wired Board
Handiwork of Godwin Mayers, Penn
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Test Signal Input Attached to Shaper
Lecroy 9210Pulser:12ns Rise20ns width400ns fallAmplitude Setting:1V Shaper tests
Shaper inputShown = 5:1Atten
Preamp V I = 5.1k
AC coupled
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Preamp Output Ch 4
Preamp 4
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Shaper 1X outputExpected (RC)2 – CR Shaping
IndividualDifferentialOutputs A, BAC coupled
Out A – Out B37ns Peaking time
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1X and 10X Shaper Output #2
10X1X
14.1mV and 153mV peak 38ns Rise
Pulser Pre-Calibration Percent Deviaton from Linear
-0.2-0.1
00.10.20.30.40.50.60.70.8
0 1 2 3 4
Pulser Setting
Perc
en
Shaper Input Signal
LAPAS Shaper Output
10X Settings
10X Shaper (Deviation from Linear / 300mV FS range)X100
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
Calibrated Pulser Input (V)
% D
evia
tio
10X Shaper Differential Output vs Input Chip 1 Ch4
0
0.5
1
1.5
2
2.5
3
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
Calibrated Pulser Input
Vout
Measured RMS Deviation (0-300mV input) 0.03 %
2% NL @ 450mV input
Design Range 0 - .3V input
LAPAS ASIC Automated Linearity MeasurementUsing AFG3252 & MSO4401
Gain 6.04
Vo
ut
Dif
fere
nti
al
%D
evi
ati
on
INL = .05% over 300mV range
LAPAS ASIC Automated Linearity MeasurementUsing AFG3252 & MSO4401
Shaper Input Signal
LAPAS Shaper Output
1X Differential Output vs Input Chip 1, Ch3
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5 3 3.5 4
Calibrated Pulser Input
Vout
Pulser Pre-Calibration Percent Deviaton from Linear
00.10.20.30.40.50.60.70.8
0 1 2 3 4
Pulser Setting
Perc
ent D
evia
tio
1X Shaper (Deviation from Linear / 3V FS range)X100
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 0.5 1 1.5 2 2.5 3 3.5 4
Calibrated Pulser Input (V)
% D
evia
tio
Measured RMS Deviation (0-3V input) 0.04 %
1X Settings
Design Range 0 - 3V input
Gain 0.625
%D
evi
ati
on
*
Vo
ut
Dif
fere
nti
al
INL = .06% over 3V range
10X
Ran
ge
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Shaper Uniformity across all tested Chips
Distribution of 10X Shaper Amplitudes (out 4) input = 33mV
02468
188.9
191.2
193.5
195.8
198.1
200.4
202.7
205.0
207.3
209.6
211.9
bins (amplitude in V)
freq
uenc
10x Out 4 Shaper Response Uniformity
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0 0.01 0.02 0.03Vin
Vout
Chip 6Chip 4Chip 3Chip 1Chip 7Chip 2Chip 8Chip 9Chip 10Chip 11Chip 12Chip 13Chip 14Chip 15Chp 16Chip 17Chip 18Chip X
1x Out 3 Shaper Response Uniformity
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0 0.2 0.4 0.6 0.8 1
VinVo
ut
Chip 1
Chip 2Chip 3
Chip 4
Chip 6Chip 7
Chip 8
Chip 9Chip 10
Chip 11
Chip 12Chip 13
Chip 14Chip 15
Chip 16
Chip 17
Chip 18Chip X
Distribution of 1x Shaper Ampilitudes (out3) input = 165mV
02468
84.0
85.0
86.0
87.0
88.0
89.0
90.0
91.0
92.0
93.0
94.0
95.0
bins (amplitude in mV)
freq
uenc
RMS Deviation (18 chips) = 5mV RMS Deviation (17 chips*) = 1.8mV
* Chip #16 removed
TWEPP '09 28
Gamma IrradiationBNL source used to irradiate 3 LAPAS ASIC’s to 1MRad in three steps
Chip 8 Shaper Post Irradiation Measurements(0, 200krad, 500krad, 1000krad)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0 0.2 0.4 0.6 0.8 1
input (v)
10x out 4 before
10x out 4 after 200k
10x out 4 after 500k
1x out 3 before
1x out 3 after 200k
1x out 3 after 500k
10x out 1 after 200k
10x out 1 after 500k
1x out 2 after 200k
1x out 2 after 500k
10x out 4 after 1000k
1x out3 after 1000k
10x out1 after 1000k
1x out 2 after 1000k
10X
1X
500K data
Vo
ut
Dif
fere
nti
al
Possible increase in 500Krad gain not inconsistent with change in pulser shape or amplitude.
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Conclusions With Hand Wired Prototype
• DC results very close to Simulations. – Transfer gain ( Vout / Iin) Measure 5.1K Nominal Sim 5.2K– Peaking time 37ns as predicted.
• Preamp Transient response Good Ch 3,4 .Need to understand Ch1, Ch2 oscillation.
• No Shaper Control Tuning reqd.• Shaper Transient response, Good. • Common Mode Auto-Tracking Excellent.• Meas. Shaper Noise (10x) ~130uV of 3V Output range.
ENI ~ 34nA ( 11% of total noise )• Integral Non Linearity Less than .1% over FS 1X and 10X• Dynamic Range As Designed.• Ch to Ch uniformity Better than 5% across 17 tested ASIC’s.• Shaper Power = 26.2mA*5V = 130 mW (combined 1X , 10X channel)• No significant concerns about first Ionizing Radiation results.
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Next Steps for Prototype Evaluation
• PC Board being Stuffed Reduce hookup parasitics to improve testability of preamp.
• Test Preamp with existing LAr FEE.• Preamp / Shaper tests with Prototype ADC. • Finish Radiation Hardness Evaluation ( protons,
neutrons).
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Support Slides…
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Additional Measurements1nF Detector Capacitance Preamp and 10X Shaper
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Preamp and Shaper Response with 0 and 1nF Input Capacitance
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Extracted Netlist Simulation(1nf Detector Capacitance Included)
Preamp CH 1-4
Shaper Ch 1-4
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Translinear Shaper Structures• Low Power ~20mW• Very Linear .2% over 2V output Range• Low component Count• Noise ~15nV/ √Hz, Too High for LAr
no simple targets to reduce noise
**
*
*
*
-1.75V
1.2V
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Process Variation MC
CH4 CH1
CH4CH1
Extracted Netlist (no 1nF Detector Capacitance)
~3% RMS
Amplitude
Variation
65mV
500m
V