P-2/84

Publication Number 0117-0308-10 February 1984

K 105-0 LOG I C ANAL YlER

USERS M\NUAl ADDENDUM

lao DISASSEMBLER

Gould Inc., Design & TesT Sys~ems Division 4600 Old Ironsides Drive Santa Clara, CA 95050-1279 Telephone: (408) 988-6800 TWX/TELEX # 910-338-0509

Copyright c 1984. No parT of this publication may be reproduced without written permission from Gould Inc., Design and Test Systems Division. Printed in U.S.A.

Chapter

INTRODUCTION INTRODUCTION. $ • ~ •••

LOADING THE DISASSEMBLER ••

2 SPECIFICATIONS

. . . . . . . .

CONTENTS

Page

(I (I e 1-1 • • 1-5

PHYSICAL DIMENSIONS AND WEIGHT ••••• $ ••• eo ••••• 2-1

3 D I SPLAYS SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS •••••••• 3-1

Figure 1-1 1-2 3-1 3-2 3-3 3-4

Table

Z80 Microprocessor Pinout Diagram •• Typical RTE to Target (I •• e e e e e _

Disassembler Data Format Set Up Menu •••• Clock Set Up Menu ••• e ••• e ••••

Trace Control Set Up Menu •••••• (I e e

Captured Data in Disassembled Format ••••

• 0 • • • • 1-1

· . . . . . 1-3 • • • 0 • • • 3-1

• • • • • 0 • • • 3-2 3=3

• e . . • 3-4

1-1 Microprocessor-To-Logic Analyzer Connection Data •• $ •••• e 0 1-2

iii

ChapTer 1

iNTRODUCTION

INTRODUCTION

This addendum provides the user with specific information on the Z80 target microprocessor Disassemblers. Included in the addendum is a microprocessor pinout diagram, microprocessor-to-Iogic analyzer connection data, screen displays of the preprogrammed menus, a screen display of captured data in the disassembled format and special notes on the disassembler/logic analyzer.

A, , 40 A,o

A12 2 39 Ag

A13 3 38 A8

A'4 4 37 A7

A,s 5 36 ~

elK 6 35 As

04 7 34 A4

03 8 33 A3

Os 9 32 A2

06 10 31 A, Z80

+5V 11 30 Ao

02 12 29 GND

07 13 28 RFSH

Do 14 27 M1

0, 15 26 RESET

INT 16 25 BUSREO

NMI 17 24 WAIT

HALT 18 23 BUSACK

MREO 19 22 WR

IORO 20 21 RD

Figure 1-1. Z80 Microprocessor PinouT Diagram

1-1

INTRODUCTION

Table 1-1. Microprocessor-To-Logic Analyzer Connection Data

Z80 Z80 K105-D PIN RTE PIN SIGNAL PIN ASSIGNMENT ASSIGNMENT

A 11 1 C3 Jl-45 A12 2 C4 Jl-47 A13 3 C5 Jl-49 A14 4 C6 Jl-51 A15 5 C7 J 1-53 ClK 6 8K J 1-78 04 7 A4 Jl-69 03 8 A3 Jl-67 05 9 A5 Jl-71 06 10 A6 Jl-73 +5V 11 NOT CONNECTED NOT CONNECTED 02 12 A2 Jl-65 07 13 A7 Jl-75 DO 14 AO Jl-61 01 15 A1 Jl-63 INT 16 06 Jl-52 "'UI ,.., .. ..... , .)I-..J'+

HALT 18 04 Jl-48 MREO 19 02 Jl-44 IORO 20 D1,CJ Jl-42,57 RD 21 D3,BJ Jl-46,80 WR 22 OJ Jl-58 8USACK 23 NOT CONNECTED NOT CONNECTED WAIT 24 05 Jl-50 8USREO 25 NOT CONNECTED NOT CONNECTED RESET 26 NOT CONNECTED NOT CONNECTED MT 27 DO Jl-40 RFSH 28 NOT CONNECTED NOT CONNECTED GND 29 GND A-8-C-D SECT. Jl-1,2,37,38,59,60 AO 30 80 Jl-62 A1 31 81 Jl-64 A2 32 82 Jl-66 A3 33 83 Jl-68 A4 34 84 Jl-70 A5 35 85 Jl-72 A6 36 86 Jl-74 A7 37 87 Jl-76 A8 38 CO Jl-39 A9 39 Cl Jl-41 Al0 40 C2 Jl-43

NOTE: The J1 Scrambler board is equivalent to the J7 Motherboard.

1-2

I~DOCTI~

ATTACHMENT TO A TARGET SYSTEM

Figure 1-2 illustrates a typical RTE (Real Time Execution) to target system con­nection.

The RTE probe connectors are labeled to identify the input probe that must be plugged into the specific connector. The user shal I remove the probe tips and instal I the probes, label up, into the RTE connectorse When connecting the microprocessor dip-cable into the RTE, special attention should be given to the keyed position of the connectors. The user should also ensure that pin 1 of the dip-cl ip is al igned with pin 1 of the microprocessor when connecting to the target microprocessor.

Figure 1-2. Typical RTE to Target System Connection

NOTE: Figure 1-2 shows one of several possible connections of the RTE to a target system. As the configuration of the microprocessor pinouts change, the RTE to target system interface may also change.

1-1

INTRODUCTION

ATTACHMENT TO A TARGET SYSTEM

1-4

* * * * * * * * * * * * * * * * * * * * * * * * * * * *

CAUTION * * *

* In the event the microprocessor on your * * target system is soldered to the board and * * the alternate connector is being used, there * * is the possibi lity of inducing reflective * * noise into the test signals. To el iminate * * this problem, we recommend varying the * * threshold voltage levels beyond noise levels. * * * * * * * * * * * * * * * * * * * * * * * * * * * *

I NTROOUCT I ON

LOADING THE DISASSEMBLER

The fol lowing procedure provides step-by-step instructions for loading the Disassembler:

a. Enter the Disk Operating System screen.

b. Gently insert the disk into Drive B, with the disk slot toward the rear of the unit and the label up. Next, lock the disk in place with the drive latch handle.

c. Depress function key F3 to display the B directory.

d. Depress 1 to select the Recal I function.

e. Use the right arrow cursor to enter the fi lename field and then use either the up or down cursor to select the Disassembler.

f: Depress function key F4 to load the Disassembler.

g. Depress the Format key to enter the Format screen.

h. Depress 6 and then DATA to enter Disassembler mode.

* * * * * * * * * * * * * * * * * * * * * * It is

CAUTION

suggested that the user

* * * *

* make a backup copy of the * * master disk prior to attempting* * use of the disassembler. * * * * * * * * * * * * * * * * * * * * *

1-5

PHYSICAL DIMENSIONS AND WEIGHT

Height - 2.25 inches (5.7 cm) Width - 9.5 inches (24.1 cm) Depth - 5.5 inches (14 cm)

Weight - 1 lb. 11 oz. (.77 kg) with flat cable, device clip and probe printed circuit board

ELECTRICAL CHARACTERISTICS

Loading (Signal Inputs)

Input Resistance - 1 megohm +2% to threshold (-1.4 volts)

Input Impedance - 150 ohms (approximate)

TVDical Ri~p./F~I I

ChapTer 2

SPECIFICATIONS

processor and its support devices. The 8086/8088 microprocessor slows approximately 5 nanoseconds on edge rates.

Lo~ding (Ground/Reference InpuT)

Input Resistance - Less than 1 ohm referenced to target system ground.

Ground Difference Immunity - + 0.25 maximum volts between logic analyzer ground and target system ground.

Reflected Noise Into Target System

Probed with Dip CI ip or Circuit Board Socket - heavi Iy dependent on target system ground. Typically, the system noise is reduced due to slower edge rates caused by probe load. This condition occasionally masks the problem being pursued.

2-1

ChapTer 3

DISPLAYS

SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS

Figures 3-1 through 3-4 illustrate the preprogrammed setup menus downloaded from disk to the K105-D. Figure 3-4 illustrates the Disassembled Data. When in the Disassembled Data display, sequential depression of the SHIFT and V keys causes the software version number for the disassembler to be displayed.

L ADDP

_t N r~-::' U T ~=;

II ~I T A I N PUT ~=; DF -·_·I)l::i

.D7-·D0 CF-C::;=~ C: 7 - C iii E:F-B~=: B7-B0 AF-~==t:=: A 7·-A0

C::: r _ .. C) C. l·< I N F' LJ T :~;

CCBB

5151 4040

Cf.I]~·DAT A FC)Pt"1A-r_, !"1 E tOol [) P ITI = t-1 t"1 ~:::I I N

DDDDDDDD

7654:321.0

+ 1. e

+ -I ~ · + 1 · -i .. 1 .I. · .. j- I n

+ 1 · + l · .+. i .I. ·

+ J

4 -4 4 4 -·::1· _.::j.

4 ,::j. ,

~~-I.

51 40

Figure 3-1. Disassembler DaTa FormaT SeT Up.Menu

3-1

DISPLAYS

SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS (cont'd)

C L Ci C: ~<. :::; 0 U PC::: E

t~:.· I.... !. 1 r ~ .. ! !t-_ ~ C:.

3-2

t~: >; T E F N ,~:~ I .. i"oJ (:l (1 E:

!"~: i .. CJ C 1·< ~.:~: () i·-·I E~ I ~.J. ::::1 T T C) i~"/ n F' F T /'""( T T T. [-.=1 r,,·) <~:;

C L () C V: I ~Lj F' i...! T ~=::

Figure 3-2. Clock Set Up Menu

DISPLAYS

SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS (contfd)

L \,' L C C) r-'! j"1 (4 N D :::; E () U E N c: E:: : !2~i: T P ~l C:: E: I..J r"~ TIL :::; A r'1 F' L E = E t;"j A B L E 1.: r F';:~ ~::l C E U NT r L :::; A 1-1 F' L E = T F~ I !3 (3 E F~~ '2: i_I i'~~ ~< C) N. E N T F !T! T C) LEI,) E 1._

TRACE FOR 00512 CLOCVS

.~-----------,-----------------.. -.--.---.---PATTERN DEFINITIONS:

NAME: ADDR STATUS 00 ENABLE =XXXX XXXXXXXX 01 TRIGGER =XXXX XXXXXXXX 02 =XXXX XXX XXX XX

LtJ] -:. T I] P C: r'i IJ .' r F 2 I -*T C) F' P T P r~ "'1 E r-1 CI F.~ iTI = t-i r-1 ~:~ I N

D(4T t:::i XX XX XX

Figure 3-3. Trace Control Set Up Menu

NOTE: In disassembler mode, the trace control patterns are formatted into address, status and data. When the status field is selected as the active field, the possible choices are the status conditions of the processor as fol lows:

(0) READ (1) WR I TE (2) INPUT (3) OUTPUT (4) FETCH

(5) HALT (6) ACK (7) I NT (8) NMI

In Edit mode, status bits can be edited on a bit-by-bit basis. "X" selects al I don't cares.

3-3

DISPLAYS

SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS (cont'd)

C: L .. ~< = 50 r\ :::;: E C

::::; ::::: in: :"i: ::-:: X F'F:AI"iE ADDP (-, ,::'!- :3 t'=:o ft.) E: 0 ~!

,::j, :-'::: .:;:. g P 4?! ::;:~

···!·4l2.'1 44i .::j. ~::j.:2 44·,::!,

446 44';:::'

F F-- :::: F ~ .. ~ FIT E F F i::: E L-.i PIT E 0.f:: 0 :~:: :;? 7 I) C: I N F' U T 0B05 FF::=:E ~:EAD F F ::=: F h~ E ~4 D

.,::!- .,:+ d !{.t .t:: ~ '=, 450 0B0:::: 452 2ADC C)UT PUT 4~;3 I2IB~H ·.:.1· 5 t:::, !2t B L?\ :::;:: ,.:t. 5 7 F F ::::: F ~.j F: I T E ... :j. :3 :::: F F :::: E ~-~ PIT E ·4 5 ':;' 0 B l~ :=:: 46 1 :2Anc: T. NF'UT ·1·62 0E:05 46::::: FF::::E ~:EAD 46..:.1- FF:::;:F' ~:EI::':ID

~: io': C)E;.J CU:DE C:: :3 J;!:, :2l;;:J E: F5 '-'1 --:t ...::. I"

IJB:lJC ;aT:) F 1 20

I .... !:::. ~~ ._:,

D:3DC 2A c:::::::e.20B F5 2A

IJBDC !?IT.:! F 1

CONTROL=0436 REF=1023 CEJ]-:.- F i.3 U F O:::[j~ F' C~ DC) j. ... i r;,,/ IF::: l...:r D ~=; F' LiT' r-" E t-·, C! F: 1/ = ~~ r-1 I:::' I N

,-1 N t=..:: i'1 Ci N I C: ... ,f I::::' t;i-j i:: ¥.~ ::'-2 F'!j :::::; H ~::I F

F'CIF' .'. r'-Hi

1·4.Lt!...! ~·-i.: l;~J ... :'

OUT >: DC: > .' i=-:,

,.J F' l2I B 0 :2 F' 1...1 :::; H t=-::, F

P()F' (~F

Figure 3-4. Captured Data in Disassembled Format

3-4

.... P

.t'.

L 1 l 1 i 1. 1 4 J.

1. 1 .l

i i 'I .L

1 t 1 1.

J. 1 1

DISPLAYS

NOTES:

1. After the disassembler data format, and clock select menus of the logic analyzer are pre-programmed, the trace control selections must be made by the user before making a recording. The trace control selections determine exactly which portions of the data stream are recorded or ignored.

2. Although displayed, the sample labeled "SAMP" is not decoded.

3. If the disassembler is loaded and active, and an additional disassembler is to be loaded, always return to the Data Format screen to ensure the necessary tables are set up.

4. The SEARCH and COMPARE keys are not active in the Data Display Screen. The Edit mode can be used to change the search word. After leaving Edit mode, the NEXT and PREVIOUS keys locate target data in memory. if the search word is not active, the NEXT and PREVIOUS keys update the display to the next or previous trace level transition.

5. Depression of the F3 function key changes the display of recorded infor­mation. Code is not disassembled, but recorded information is displayed from the control cursor (C) position to the end of memory as frame number, address, status and data.

If recorded data is displayed in object format, depressing the F4 function key invokes the disassembly process for data from the control cursor to the end of memory.

6. Illegal instructions are displayed as ???

7. The disassembler is first downloaded from disk to the K105-D and the disassembler format is selected. The trace patterns are then configured as desired.

3-5