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LAB 3 Synchronous Serialort es gn s ng er og

TA : Junyoung Park

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VLSI Lab Overview Cont

RTL level system design using Verilog (Behavioral modeling) to design

Part A: Synchronous Serial Port (SSP) Part B: Integration of SSP with ARM processor using a SoC bus

Verilog Simulators

Simulator VCS (Synopsys), ncverilog (Cadence) Tools

Simulation:

er og s mu at on too

VirSim GUI to control simulation and view waveforms

Design Vision Logic Synthesis

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LabLab33AA SSP Desi nSSP Desi n

SSP Perform

Parallel-to-serial conversion on data received from a

processor

Serial-to-parallel conversion on data received from aperipheral device

Your desi n

Your SSP provides buffering capability on both the TX

and RX logic using FIFOs to allow up to four 8-bitwords to be stored in independently in both TX and RXmodule

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Lab3A SSP Block Dia ram

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Lab3A SSP S ecifications

8-bit wide, 4-location deep FIFO memory buffer

,signal and refuse to accept any additional data

Transmit and Receive Logic

TX Logic: read from TxFIFO and perform parallel-to-serial conversion

en e ser a a a sync ronous y

RX Logic:

erform serial-to- arallel conversion on the incomin datasynchronously

Send data into RxFIFO

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Lab3A Port Descri tions

Name your top module as ssp

You should use the exact names shown below

SSP module port description

nput port: , _ , , ,PWDATA[7:0], SSPCLKIN, SSPFSSIN, SSPRXD

Output port: PRDATA[7:0], SSPOE_B, SSPTXD,

SSPCLKOUT, SSPFSSOUT, SSPTXINTR,

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Lab3A Si nal Descri tion

Please refer to the lab website for details

gna escr p ons

CLEAR_B: Low active clear signal

SSPCLKIN(RxLogic), SSPCLKOUT(TxLogic) Synchronization clock for data transfer

2 times slower than PCLK (clock for SSP) PSEL: Chip select signal for SSP

PWRITE: High Write to SSP, Low Read from SSP SSPFSSIN(RxLogic), SSPFSSOUT(TxLogic)

Indicate starting of data transfer

SSPOE_B: Low active output enable signal, indicating when SSPTXDis valid (Used only for transmission)

Assume erfect s nchronization between SSPCLKIN andSSPCLKOUT - testing is done with external loop back

Dataflow: (Written by the processor) SSP TxFIFO SSPTXDSSPRXD SSP RxFIFO (Read by the processor)

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Lab3A Timin Dia ram sin le

transfer)

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Lab3A Timin Dia ram continuous

transfer)

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Lab3A Lo ic S nthesis

Re ularl s nthesize our code b readin in our

design to make sure your design is synthesizable

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LabLab33BB WISHBONE SoCWISHBONE SoC

interconnection interfaceinterconnection interface

To design WISHBONE bus interface module ton egra e e erogeneous mo u es

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Lab3 What is iven to ou

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Lab3 What ou should do

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Lab3B Module Descri tions ARM processor (Given) Memory module (Given)

Synchronous Serial Port (Designed in Lab3A) ave core o your system

WISHBONE & Clock Management Unit (Need to design

n a WISHBONE master: communicate with the ARM core

s ave: commun ca e w e an memory

module

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Lab3B WISHBONE

When the ARM core gets the data transfer activities,

WISHBONE master has to transfer the data from/to theWISHBONE slave

Slave: Transfer the data to/from the memory of SSP according to

request from the ARM core, and then report the result of the

transfer to the WISHBONE master

Should be done with WISHBONEs timing specifications

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Lab3B WISHBONE Cont

for ARM processor (phi1, phi2)

for Memor hi1 hi2

for WISHBONE and SSP (clk_o)

If interrupts are occurred, Clock Management Unit shouldsto the clock for ARM rocessor.

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Lab3B WISHBONE Cont

Instruction Read

en accesses

Generate memory access signals

Deliver instructions from memory to ARM

Mem SlaveMaster ARM

Path: Read signal (ARM) master slave memory data frommemor slave master ARM instruction transferred to ARM

Data Read from SSP

en access

Generate SSP access signals

Deliver data from SSP RxFIFO to ARM SSP SlaveMaster ARM

Path: Read signal (ARM) master slave SSP data from SSP

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Lab3B WISHBONE Cont

When ARM access h0010000

Generate SSP access si nals

Deliver data from ARM to SSP (TxFIFO) ARMMaster Slave SSP

Path: Read signal and data (from ARM) master slaveSSP (data written to SSP)

Interrupt Handling

Stop ARM by holding phi1 and phi2 (Cloc Management Unit)

E.g., SSP Overflow Interrupt

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Lab3B Simulation

r e your own assem y es program us nginstructions Read ARM manual iven to ou

Compile the assembly code and save it to /image/mem.datactua memory mage

asm_arm my_assembly_code > mem.data

.choose to create your own

un