Lab03 Core Peripherals - access.ee.ntu.edu.tw

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Core PeripheralsCore Peripherals

Speaker: Lung-Hao Chang 張龍豪Advisor: Prof. Andy Wu 吳安宇教授

March 26, 2003

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

SoC Design Laboratory PP. 103/26/2003

Goal of This LabGoal of This Lab

Ø Familiarize with ARM Hardware Development EnvironmentqARM Integrator/APqCore ModuleqLogic Module

Ø How to use Timer/Interrupt



OutlineOutline

Ø ARM Integrator Core Module (CM) [1]Ø ARM Integrator Logic Module (LM) [2]Ø ARM Integrator ASIC Application Platform (AP) [3]Ø System Memory Map [1]Ø Lab3 – Core Peripheral



ARM Integrator Core Module/CMARM Integrator Core Module/CM

Ø CM provides ARM core personality.Ø CM could be used as a standalone development system

without AP.Ø CM could be mounted onto AP as a system core.Ø CM could be integrated into a 3rd-party development or

ASIC prototyping system.



Core moduleCore module



ARM Integrator/CM Feature (CM9TDMI)ARM Integrator/CM Feature (CM9TDMI)

Ø ARM9TDMI microprocessor coreqARM940T/ARM920T

Ø Core module controller FPGA :qSDRAM controllerqSystem bus bridgeqReset controllerq Interrupt controller

Ø Supports 16MB~256MB PC66/PC100 168pin SDRAMØ Supports 256/512 KB SSRAMØ Multi-ICE, logic analyzer, and optional trace connectors.



FPGA functional diagramFPGA functional diagram



ARM Integrator Core Module FPGAARM Integrator Core Module FPGAØ SDRAM controllerqSupports for DIMMs from 16MB to 256MB.

Ø Reset controllerq Initializes the core.qProcess resets from different sources.

Ø Status and configuration spaceqProvides processor information.qCM oscillator setup.q Interrupt control for the processor debug communications

channel.

Ø System bus bridgeqProvides Interface between the memory bus on the CM and

the system bus on the AP.



Connecting MultiConnecting Multi--ICE with CMICE with CM



OutlineOutline




ARM Integrator/LM Logic ModuleARM Integrator/LM Logic Module

Ø LM is designed as a platform for development AHB/ASB/APB peripherals for use with ARM cores.

Ø LM could be used as a standalone system.Ø LM could be mounted with an Integrator/CM, and an

Integrator/AP motherboard.Ø LM could be used as a CM with Integrator/AP if a

synthesized ARM core, such as ARM9TDMI-S, is programmed into the FPGA.



Integrator/LMIntegrator/LM



ARM Integrator/LM Feature (XCVARM Integrator/LM Feature (XCV--2000E)2000E)

Ø Altera or Xilinx FPGAØ Configuration PLD and flash memory for storing FPGA

configurationsØ 1MB SSRAMØ Clock generators and reset resourcesØ SwitchesØ LEDsØ Prototyping gridØ JTAG, Trace, and logic analyzer connectorsØ System bus connectors to a motherboard or other modules



LM ArchitectureLM Architecture



Using MultiUsing Multi--ICE with LMICE with LM



OutlineOutline




About ARM Integrator/APAbout ARM Integrator/AP

Ø An ATX motherboard which can be used to support the development of applications and hardware with ARM processor.

Ø Platform board provides the AMBA backbone and system infrastructure required.

Ø Core Modules (CM) & Logic Modules (LM) could be attached to ASIC Platform.



ARM Integrator/AP FeaturesARM Integrator/AP Features

Ø System controller FPGA.q System bus to CMs and LMsq System bus arbiterq Interrupt controllerq Peripheral I/O controllerq 3 counter/timersq Reset controllerq System status and control

registers

Ø Clock GeneratorØ Two serial ports (RS232 DTE)

Ø PCI bus interface supporting onboard expansion.

Ø External Bus Interface (EBI) supporting external memory expansion.

Ø 256KB boot ROMØ 32MB flash memory.Ø 512K SSRAM.



Integrator/APIntegrator/AP

Not to scale



ARM Integrator/AP Block DiagramARM Integrator/AP Block Diagram



Assembled Integrator Development SystemAssembled Integrator Development System

Core module

Logic module



Assembled Integrator/AP systemAssembled Integrator/AP system



System Controller FPGA (1/2)System Controller FPGA (1/2)Ø System Bus InterfaceqSupports transfers between system bus and the Advanced

Peripheral Bus (APB).qSupports transfers between system bus and the PCI bus.qSupports transfers between system bus and the External

Bus Interface (EBI).Ø System Bus ArbiterqProvides arbitration for a total of 6 bus masters.vUp to 5 masters on CMs or LMs.vPCI bus bridge. (the highest priority)

Ø Interrupt ControllerqHandles IRQs and FIQs for up to 4 ARM processors.q IRQs and FIQs originate from the peripheral controllers, PCI

bus, and other devices on LMs.



System Controller FPGA (2/2)System Controller FPGA (2/2)Ø Peripheral I/O Controllersq2 ARM PrimeCell UARTsqARM PrimeCell Keyboard & Mouse Interface (KMI)qARM PrimeCell Real Time Clock (RTC)q3 16-bit counter/timersqGPIO controllerqAlphanumeric display and LED control, and switch reader

Ø Reset Controllerq Initializes the Integrator/AP when the system is reset

Ø System Status & Control RegisterqClock speedsqSoftware resetqFlash memory write protection



System Controller FPGA DiagramSystem Controller FPGA Diagram



Reset ControllerReset Controller

Ø A reset controller is incorporated into the system controller FPGA.

Ø The hardware reset sources are as follows:qPush-button PBRST and CompactPCI signal CP_PRSTqATX power OK signal nPW_OK and CompactPCI power fail

signal CP_FALqFPGADONE signal (routed through CPCI arbiter to become

nRSTSRC5)qLogic modules using nEXPRSTqCore modules (and Multi-ICE) using nSRST



Integrator/AP Reset ControlIntegrator/AP Reset Control



Interrupt ControllerInterrupt Controller

Ø The system controller FPGA contains four interrupt controllers.

Ø The system controller incorporates a separate IRQ and FIQ controller for each core module.

Ø Interrupts are masked enabled, acknowledged, or cleared via registers in the interrupt controller.

Ø Main sources of interrupts:qSystem controller’s internal peripheralsqLM’s devicesqPCI subsystemqSoftware



Interrupt Controller ArchitectureInterrupt Controller Architecture



System BusSystem Bus

Ø The HDRA/HDRB and EXPA/EXPB connector pairs are used to connect the system bus between the AP and other modulesqCore modules on the connectors HDRA and HDRBqLogic modules on the connectors EXPA and EXPB

Ø There are three main system bus (A[31:0], C[31:0], and D[31:0]) and fourth bus B[31:0]qA[31:0]: This is the address busqB[31:0]: Only connects HDRA to EXPA and reserved for

future useqC[31:0]: Used to implement a system control busqD[31:0]: This is the data bus



System Bus ArchitectureSystem Bus Architecture



PeripheralsPeripherals

Ø The peripheral devices incorporated into the system controller FPGAqCounter/timersqReal-time clockqUARTsqKeyboard and mouse interfaceqGPIO



Counter/TimersCounter/Timers

Ø There are 3 counter/timers on an ARM Integrator AP.Ø Each counter/timer generates an IRQ when it reaches 0.Ø Each counter/timer has:qA 16-bit down counter

with selectable prescaleqA load registerqA control register



Counter/Timers Registers (1/2)Counter/Timers Registers (1/2)

Ø These registers control the 3 counter/timers on the Integrator AP board.

Ø Each timer has the following registers.qTIMERX_LOAD: a 16-bit R/W register which is the initial

value in free running mode, or reloads each time the counter value reaches 0 in periodic mode.

qTIMERX_VALUE: a 16-bit R register which contains the current value of the timer.

qTIMERX_CTRL: an 8-bit R/W register that controls the associated counter/timer operations.

qTIMERX_CLR: a write only location which clears the timer’s interrupt.



Counter/Timers Registers (2/2)Counter/Timers Registers (2/2)ØCounter Timer RegistersAddress Name Type Size Function0x13000000 TIMER0_LOAD R/W 16 Timer0 load register0x13000004 TIMER0_VALUE R 16 Timer0 current value reg0x13000008 TIMER0_CTRL R/W 8 Timer0 control register0x1300000C TIMER0_CLR W 1 Timer0 clear register

ØTimer Control RegisterBits Name Function7 ENABLE Timer enable: 0=disable; 1=enable.6 MODE Timer mode: 0=free running; 1=periodic5:4 unused Unused, always 03:2 PRESCALE Prescale divisor: 00=none; 01 = div by 16

10=div by 256; 11 = undefined1:0 Unused Unused,always 0



The IRQ and FIQ Control RegistersThe IRQ and FIQ Control RegistersØ Implemented in the system controller FPGA.Ø Provides interrupt handling for up to 4 processors.Ø There’s a 22-bit IRQ and FIQ controller for each processor.



IRQ Registers (1/2)IRQ Registers (1/2)

Ø The registers control each processor’s interrupt handler on the Integrator AP board.

Ø Each IRQ has following registers:q IRQX_STATUS: a 22-bit register representing the current

masked IRQ status.q IRQX_RAWSTAT: a 22-bit register representing the raw IRQ

status.q IRQX_ENABLESET: a 22-bit location used to set bits in the

enable register.q IRQX_ENABLECLR: a 22-bit location used to clear bits in

the enable register.



IRQ Registers (2/2)IRQ Registers (2/2)

• IRQ RegistersAddress Name Type Size Function0x14000000 IRQ0_STATUS R 22 IRQ0 status0x14000004 IRQ0_RAWSTAT R 22 IRQ0 IRQ status0x14000008 IRQ0_ENABLESET R/W 22 IRQ0 enable set0x1400000C IRQ0_ENABLECLR W 22 IRQ0 enable clear

• IRQ Registers bit assignmentsBit Name Function0 SOFTINT Software interrupt5 TIMERINT0 Counter/Timer interrupt6 TIMERINT1 Counter/Timer interrupt7 TIMERINT2 Counter/Timer interrupt



OutlineOutline




System Memory MapSystem Memory Map



Core Module Memory MapCore Module Memory Map



OutlineOutline




Lab 3: Core PeripheralsLab 3: Core Peripherals

Ø Goalq Understand available resource

of ARM Integratorv Integrator/APvCore Module (CM)vLogic Module (LM)vMemory-mapped devicevTimer/Interrupt

Ø Principlesq ARM ASIC Platform Resourcesq Semihostingq Interrupt handlerq Architecture of Timer and

Interrupter controller

Ø Guidance q Introduction to Important

functions used in interrupt handler

Ø Stepsq The same to that of code

developmentØ Requirements and ExercisesqModified the C program. We

use Real-Time Clock instead of timer to show our IRQ0 values.

Ø Discussionq How to use multi-

timer/interrupt.



Timer/Interrupt example without Timer/Interrupt example without uHALuHAL

Ø Several important functions are used in this example:q Install_Handler: This function install the IRQ handler at the

branch vector table at 0x18.qmyIRQHandler: This is the user’s IRQ handler. It performs

the timer ISR in this example.qenableIRQ: The IRQ enable bit in the CPSR is set to enable

IRQ.qLoadTimer, WriteTimerCtrl, ReadTimer, ClearTimer:

Timer related functions.



ReferencesReferences[1]http://www.arm.com/support/4XHLQX/$File/DUI0126B_CM7TDMI_UG.

pdf[2]http://www.arm.com/devtools/integrator/LM-XCV2000E.pdf[3]http://www.arm.com/arm/User_Guides/DUI0098B_AP_UG.pdf.

Lab03 Core Peripherals - access.ee.ntu.edu.tw

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