Lab 7: Interfacing an 8051 with the WM8731 Audio Chipset

CpE 214: Digital Engineering Lab II

Last revised: April 1, 2013 (CAC)

In this lab, you will be given the datasheet of the Wolfson audio chipset that is available on Altera DE-2 FPGA board.With it, you will then design an 8051 circuit that will interface with the onboard audio. A VHDL interface for the audio isprovided to simplify the process. The student will learn how basic analog/digital (A/D) conversion takes place in modernembedded systems. A sample set of audio will be captured and then stored in internal RAM on the 8051. The discretizedaudio being captured will also be able to be played back to the user through the FPGA’s sound port.

0.1 Outline and Concepts

1. Introduction to A/D Conversion and WM8731

2. Creating Top Level Design

3. Writing the C program

4. Testing with Cyclone II FPGA

1 Introduction to A/D Conversion and WM8731

All sounds stored in digital systems are clearly sampled in a certain fashion. WAV audio files, which was one of the morepopular formats some years ago, stored sound in 16-bit signed 2’s complement form. Each 16-bit value represented a "sample"of the audio signal, and is typically referred to as some form of Pulse Code Modulation (PCM). Modern DSP devices work onthe same premise. An audio signal (consisting of a series of different single frequencies, or plane waves) is discretely sampled,with the results being sent on to some type of microprocessor to store and/or encode the results. Playing the discretizedsignal back is done in the reverse manner. A basic diagram showing how this works is shown in Figure 1.

FIG. 1: ADC workflow [1]

1

Sampling Theory Background

For the purposes of this lab, you need to know a little bit about sampling theory in general. This is of course coveredextensively in many of our signal processing courses, so we will focus on the main point. Clearly a very important questionfrom the digital side of things is how often should I sample? Obviously sampling more often uses more memory, so we wantto sample ONLY as often as needed to fully capture the original signal in its entirely, thus being able to reconstruct it ifneeded (such as playing back an MP3).

• This leads to the Nyquist theorem, which states that you should sample at twice the rate of the highestfrequency component in order capture both the Min and Max peaks for the wave.

fsampling = 2fmax (1)

Human hearing is generally considered to be between 20Hz and 20KHz (with most males topping out around ≈18KHz).Therefore, something slightly above 40KHz is a safe rate to be sampling at. In fact, in the recording industry most of yourDVD’s are sampled at 44.1KHz, as well as typical MP3’s you will find. This is no coincidence.

However, let us take this type of sampling in reference to our 8051 memory model. If we sample an audio signal for 1second at 44.1KHz, where each sample has a left channel and a right channel at 16-bits each (4B in total), then some quickmath will tell us that this will take up 173KB of memory just for a single second! The 8051 can only reference up to 64KBof memory (externally) at the most, so clearly you can see that signal processing is memory intensive. This also points tothe need for encoding format algorithms (such as MP3, etc) to cut down on the size of each sample. To work around this forthe purposes of the lab, we will only focus on storing a small set of samples that we can manage.

WM8731 Diagram

FIG. 2: DE-2 FPGA’s WM8731 Circuit Schematic

2

The WM8731 chip is integrated into the Altera DE-2 FPGA’s mainboard. This allows for a convenient pinout connectionsto our designs just like we have done with other peripherals on the board. The schematic is shown in Figure 2. Like mostdevices, the audio chipset needs to be configured first before you can begin sampling audio with ADC on the line in jack, andplaying back digital audio (DAC) through the line out jack. This configuration is done with a common interface (nowadays)called SPI. It is a serial protocol, and allows for different devices to be connected on the line simultaneously. Each device onthe line has a unique 7-bit address identifier, followed by a single R/W bit to indicate the operating mode.

The issue with the 8051 is that the original reference design is missing an SPI interface. Newer versions (like the LPC932series used in the Simon boards) now include one. So, for our lab we will need to build an additional audio interface thatimplements SPI to use as a go-between from our microcontroller (and C control code) and the audio chip itself. We will buildthis in the VHDL structural language (which is what the 8051 module we are using is based on as well).

2 Creating Top Level Design

The top level design is very similar to what you have gotten used to by now: you use the 8051 and ROM modules. The onlydifference is you will need use an external module to work with the audio.

1. As usual, create a new lab7 folder and copy the associated provided files on Blackboard.

2. Additionally, you will need to copy in your seven segment decoder from lab2. You need both the .bdf and the .bsf(symbol file).

3. Make a symbol of the 8051.edf. The audio_interface.vhd symbol can’t be created (won’t compile) until we configure itproperly in the next step.

4. Wire up the design as shown in Figure 3.

Audio Interface in VHDL

Normally, we would handle controlling the audio chip completely in the C code, but since we don’t have an SPI interfaceon the 8051 itself, we need to actually configure the audio settings within the audio_interface’s vhdl code directly in Quartus.

1. Open the audio_interface.vhd, and a little ways down located the constant SCI_REG_ROM, and constant SCI_DAT_ROMcode areas. These are the registers we load with configuration data.

2. In Appendix G (WM8731 datasheet), go to page 46 and located the register table. These and the succeeding pagesdescribe the bit options for each register.

3. In this order, you need to configure the chip. Put the first 8-bits in the REG_ROM, and the second 8-bits inthe DAT_ROM. Note this is for convenience, technically the addresses are only 7-bits long and the data is 9-bits.See my initial example for how to format the lines of instructions.

(a) Deactivate the DSP interface with R9

(b) Disable Mute L/R with R0

(c) Set headphone volume for both L/R with R2. Use this value, it works well: 11110101.

(d) Select Line input for the DAC, Disable Bypass with R4.

(e) Choose 44.1KHz de-emphasis and disable ADC HPF with R5.

(f) Power on device (disable PWROFF). Disable powerdown for ADC, DAC, LININPUT with R6.

(g) Set Master clocking mode, 16-bit Input Length, DSP Mode with R7.

(h) Set the sampling Rate to 48KHz with R8. This ends up being the default 00000000.

3

(i) Finally Activate the DSP interface with R9.

Note: The datasheet’s Table 29 is a little confusing as to how the registers are addressed. Take R2 for example, the tableshows it as 04h. Then directly next to it the 7-bits of the address is actually 02h. They are tacking on an extra 8th bit (0bit) on the least significant end to come up with this, which is obviously confusing and not technically correct (should havebeen appended on the most significant end). Don’t let this throw you off. Just use the actual B15, B14,... bits as they arelisted in the table, so for example SCI_REG_ROM in this instance should have "00000101" where the last bit is actuallythe B8 option we choose for setting this register.

Errata: In Appendix D, there is a misprint in the audio chipset’s circuit schematic for the I2C read and write addresses.They are flipped, and are correctly shown in our Figure 2.

FIG. 3: Top level schematic

When you finish, you should compile your design to check for any errors. If the only error you receive is about I8051_ROM,then everything is GOOD and you can proceed to writing your code.

3 Writing the C program

As usual, a template to get started is provided on Blackboard. Since all of the hard work of configuring the audio chipset isdone, the C code will be pretty minimal.

1. You need to first set the INIT function high in order to trigger the audio_interface to configure the chip.

4

2. Wait for the INIT_FINISH flag to be raised before continuing on with your code. At this point ADC/DAC is opera-tional.

3. Store the Left Channel Audio samples in the 128 Bytes of internal RAM. (which is the uppermost 16-bits on theADCDATA line connected to P1 and P0). You will only be able to store 64 samples in total. You can only do thiswhen the adc_full flag is high, or you won’t have captured all of the data. A pointer p corresponding to internal RAMaddress 00h is declared for your convenience.

4. After you have captured the 64 samples and filled the memory completely, loop through and send the results stored inmemory out to Port 2, which is connected to the seven-segment displays. For convenience, just assume you are lookingat each sample 1 byte at a time.

4 Testing with Cyclone II FPGA

Before you test on the FPGA, you should compile your design first after you import your VHDL code back to Quartus. Thisway we can fix any errors first before you get to the board and something doesn’t work.

• Assign input pins N25 as your reset, N2 as your clock, and choose your 7 segment displays appropriately. The audiopins have their own section in Appendix D (4.8). Note the MCLK is also called XCK. Compile once more. Thendownload the design onto the Altera DE-2 FPGA board using the Programmer tool in Quartus II.

• To capture audio, load up sound on the PC and then connect a 3.5mm audio cable from the PC’s line out jack to theblue line in jack on the board. To make sure that that audio chipset is configured correctly and properly capturingaudio samples (independent of your C code and the 8051 itself), you can connect a pair of headphones to the line outon the board to test it.

IMPORTANT: ONLY PLUG IN THE HEADPHONES AFTER YOU HAVE FLASHED. IF YOU DOTHIS BEFORE THERE MAY BE LOUD SCREECHING. EVEN AT THAT DON’T PUT THE HEAD-PHONES IN YOUR EARS TO BE SAFE!

• Test and see that your audio samples are being properly stored in the 8051’s internal RAM and displayed out on theseven segment displays in successive fashion.

• What if it doesn’t seem to be working?

First, double check that you have everything connected and labeled properly on the top level diagram. If you can’t hearanything playing back through the FPGA’s audio jack, then you have made a mistake in configuring the audio_interface’sregisters in the VHDL code. If you can hear sound, but just don’t see anything on the seven segments then your issue is onlyin your C code. In either case show your code to the instructor and they can help.

5 Questions (attach at end of your report)

1. Briefly summarize how the ADC/DAC works in this lab.

2. What improvements or added features to the 8051 would make working with this audio chipset easier?

3. MP3 encoding libraries are very popular for taking 16-bit samples and compressing them down. Describe how youwould go about implementing this.

References:

[1] source: http://www.eecg.toronto.edu/~jayar/ece241_08F/AudioVideoCores/audio/img/audio_adc.png

5