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Lab 5 - INUesc.inu.ac.kr/~seban90/Lab5.pdf · 2017. 11. 20. · Clock domain crossing A clock...
Transcript of Lab 5 - INUesc.inu.ac.kr/~seban90/Lab5.pdf · 2017. 11. 20. · Clock domain crossing A clock...
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Jaeyong Chung
System-on-Chip(SoC) Laboratory
Incheon National University
Digital Integrated Circuits
Lab 5
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Outline
BCD Counter
FPGA Board
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BCD Counter
Introduction
Make a decade counter by using a counter module.
A data from the decade counter is changed into the FND
data by the FND decoder.
Express a decade number by using the FND data and the
fndscan.
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BCD Counter
7-Segment
The numerals 0, 1, 6, 7 and 9 may be represented by 7 leds.
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BCD Counter
7-Segment
Binarycode encodings for displaying the digits.
DATA value
ADigits B C D E F G DP ADigits B C D E F G DP
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BCD Counter
7-Segment
By adjusting some values, each of the segments displays a
different number.
DATA value SCAN value
Digits
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BCD Counter
Implementation
The device is initialized by reset signal.
The counter increment once for every second.
Display form
The device display the digits by using 7-Segments.
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BCD Counter
Block Diagram
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BCD Counter
Code
clockGenerator
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BCD Counter
Code
clockDivider
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Code
clockDivider
BCD Counter
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BCD Counter
Code
counter
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BCD Counter
Code
fndDecoder
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BCD Counter
Code
fndDecoder
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BCD Counter
Code
Testbench
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BCD Counter
Simulation result
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BCD Counter
Code
Main
rstMain -> Reset signal
clkMain -> Main Clock
fndData -> Data
fndScan -> Com data
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BCD Counter
Code
UCF
connecting the module with FPGA PIN
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Outline
BCD Counter
FPGA Board
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FPGA Board
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FPGA Board
Block Diagram
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Create New Project
File -> New Project
Enter a name and a path of your project.
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Create New Project
Setting some values.
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Create New Project
Next
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Create New Project
Add files
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Create New Project
Project was created successfully.
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Synthesize (XST)
Click the run menu.
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Synthesize (XST)
Run succeeded.
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Download
Double click ”Configure Device (iMPACT)” button.
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Download
Double click ‘xc3s2000’
Download the bit file
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Download
Click the right button and the program
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BCD Counter
Implementation
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Clock domain crossing
A clock domain crossing(CDC) is the traversal of a
signal in a synchronous digital circuit from one clock
domain into another
Avoid if possible (Metastability, etc…)
Exercise
Remove CDC in BCD counter
D Q D Q
CLK1 CLK2
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