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Slides adapted from:

N. Weste, D. Harris, CMOS VLSI Design, Addison-Wesley, 3/e, 2004

Introduction toCMOS VLSIDesign

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Outline

z A Brief Historyz MOS transistorsz CMOS Logicz CMOS Fabrication and Layoutz

Design Flowz System Designz Logic Designz Physical Designz Design Verificationz Fabrication, Packaging and Testing

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CMOS Fabrication

z CMOS transistors are fabricated on a thin siliconwafer that serve as both a mechanical supportand electrical common point called substrate

z Lithography process similar to printing press

z On each step, different materials are deposited oretched

z Easiest to understand by viewing both top and

cross-section of wafer in a simplifiedmanufacturing process

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Inverter Cross-section

z Typically use p-type substrate for nMOStransistors

z Requires n-well for body of pMOS transistors

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Well and Substrate Taps

z Substrate must be tied to GND and n-well to VDDz Metal to lightly-doped semiconductor forms poor

connection called Shottky Diode

z Use heavily doped well and substrate contacts /taps

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Inverter Mask Set

z Transistors and wires are defined by masks

z Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor

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Detailed Mask Views

z Six masks

z n-well

z Polysilicon

z n+ diffusion

z p+ diffusion

z Contact

z

Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

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Fabrication Steps

z Start with blank wafer

z Build inverter from the bottom up

z First step will be to form the n-well

z Cover wafer with protective layer of SiO2 (oxide)

z Remove layer where n-well should be built

z Implant or diffuse n dopants into exposed wafer

z Strip off SiO2

p substrate

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Photoresist

z Spin on photoresistz Photoresist is a light-sensitive organic polymer

z Softens where exposed to light

p substrate

SiO2

Photoresist

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Lithography

z Expose photoresist through n-well mask

z Strip off exposed photoresist

p substrate

SiO2

Photoresist

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Etch

z Etch oxide with hydrofluoric acid (HF)

z Seeps through skin and eats bone; nasty stuff!!!

z Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist

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n-well

z n-well is formed with diffusion or ion implantation

z Diffusion

z Place wafer in furnace with arsenic gas

z Heat until As atoms diffuse into exposed Si

z Ion Implanatation

z Blast wafer with beam of As ions

z Ions blocked by SiO2, only enter exposed Si

n well

SiO2

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Strip Oxide

z Strip off the remaining oxide using HF

z Back to bare wafer with n-well

z Subsequent steps involve similar series ofsteps

p substrate

n well

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Polysilicon

z Deposit very thin layer of gate oxide

z < 20 (6-7 atomic layers)

z Chemical Vapor Deposition (CVD) of silicon layer

z Place wafer in furnace with Silane gas (SiH4)

z

Forms many small crystals called polysiliconz Heavily doped to be good conductor

Thin gate oxide

Polysilicon

p substraten well

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Polysilicon Patterning

z Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxide

Polysilicon

n well

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Self-Aligned Process

z Use oxide and masking to expose where n+dopants should be diffused or implanted

z N-diffusion forms nMOS source, drain, and n-

well contact

p substraten well

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N-diffusion

z Pattern oxide and form n+ regionsz Self-aligned process where gate blocks diffusion

z Polysilicon is better than metal for self-aligned gatesbecause it doesnt melt during later processing

p substraten well

n+ Diffusion

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N-diffusion cont.

z Historically dopants were diffused

z Usually ion implantation today

z But regions are still called diffusion

n wellp substrate

n+n+ n+

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N-diffusion cont.

z Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+

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P-Diffusion

z Similar set of steps form p+ diffusion regionsfor pMOS source and drain and substratecontact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+

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Contacts

z Now we need to wire together the devicesz Cover chip with thick field oxide

z Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

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Metalizationz Sputter on aluminum over whole wafer, filling the contacts

as well

z Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal

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Layoutz

Chips are specified with set of masksz Minimum dimensions of masks determine

transistor size (and hence speed, cost, and

power)

z Feature size f = distance between source and

drain

z Set by minimum width of polysilicon

z Feature size improves 30% every 3 years or so

z Normalize for feature size when describing

design rules

z Express rules in terms of = f/2

z E.g. = 0.3 m in 0.6 m process

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Layout Design Rules

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Design Rules Summary

z Metal and diffusion have minimum width and spacing of 4z Contacts are 2 x 2 and must be surrounded by 1 on the layers

above and belowz Polysilicon uses a width of 2z Polysilicon overlaps diffusions by 2 where a transistor is desired

and has spacing or 1 away where no transistor is desiredz Polysilicon and contacts have a spacing of 3 from other

polysilicon or contactsz N-well surrounds pMOS transistors by 6 and avoid nMOS

transistors by 6

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Gate Layout

Layout can be very time consuming

Design gates to fit together nicely

Build a library of standard cells

Standard cell design methodology VDD and GND should abut (standard height)

Adjacent gates should satisfy design rules

nMOS at bottom and pMOS at top

All gates include well and substrate contacts

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Inverter Layout

Transistor dimensions specified as W / L ratio- Minimum size is 4 / 2, sometimes called 1 unit- In f= 0.6 m process, this is 1.2 m wide,

0.6 m long

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Example: Inverter Standard Cell Layout

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Example: 3-input NAND Standard Cell Layout

Horizontal n-diffusion andp-diffusion strips

Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 by 40

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Stick Diagrams

z Stick diagrams help plan layout quickly

z Need not be to scale

z Draw with color pencils or dry-erase markers

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Wiring Tracksz A wiring track is the space required for a wire

z 4 width, 4 spacing from neighbor = 8 pitch

z Transistors also consume one wiring track

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Well spacingz Wells must surround transistors by 6

z Implies 12 between opposite transistor flavors

z Leaves room for one wire track

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Area Estimationz Estimate area by counting wiring tracks

z Multiply by 8 to express in

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Design Challenges

The greatest challenge in modern VLSI is not indesigning the individual transistors but in managingsystem complexity

Modern System-on-Chip designs use:

Many millions (soon billions!) of transistors Tens to hundreds of engineers

How to cope with Complexity ? Abstraction Level Structured Design Design Flow

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Design Abstraction Levels

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Structured Design Tenets

Hierarchy

Divide and Conquer

Regularity

Reuse modules wherever possible

Ex: standard cell library Modularity

Well-formed interface allows modules to be treated asblack boxes

Locality

Physical and Temporal

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Design Flow

Architecture: Users perspective, what does it do? Instruction set, MIPS, x86, Alpha, PIC, ARM,

Microarchitecture Single cycle, multi cycle, pipelined, superscalar?

Logic: how are functional blocks constructed ? Ripple carry, carry look ahead, carry select adders

Circuit: how are transistors used ? Static CMOS, pass transistors, domino logic,

Physical: chip layout Datapaths, memories, random logic

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Design Flow: Gajskis Y-Diagram

The design process can be viewedas making transformations fromone domain to another while

maintaining the equivalency of thedomains

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Architecture: MIPS example

Instruction Set Instruction encoding formats

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Architecture: MIPS example cont.

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Microarchitecture: MIPS example

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Logic Design: MIPS example Start at the top level

Define the top-level interface

Top level block diagram

Hierarchically decompose top level into units

Design the units (e.g. HDL)

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Logic Design: MIPS top level block diagram

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Logic Design: MIPS Hierarchy

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Logic Design using HDLs

Hardware Description Languages Widely used in logic design

Verilog and VHDL

Describe hardware using code Document logic functions

Simulate logic before building

Synthesize code into gates and layout Requires a library of standard cells

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Circuit Design

How should logic be implemented? NANDs and NORs vs. ANDs and ORs?

Fan-in and fan-out?

How wide should transistors be?

These choices affect speed, area, power

Logic synthesis makes these choices for you Good enough for many applications

But when a system has critical requirementHand-crafted circuits are still better

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Example: Full Adder

Transistors? Gate Delays?

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Example: Carry circuit

VERILOG:assign cout = (a&b) | (a&c) | (b&c);

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Gate-level Netlist

module carry(input a, b, c,

output cout)

wire x, y, z;

andg1(x, a, b);

andg2(y, a, c);

andg3(z, b, c);

or g4(cout, x, y, z);

endmodule

ab

ac

bc

cout

x

y

z

g1

g2

g3

g4

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Transistor-Level Netlist

a b

c

c

a b

b

a

a

b

coutcn

n1 n2

n3

n4

n5 n6

p6p5

p4

p3

p2p1

i1

i3

i2

i4

module carry(input a, b, c, output cout)

wire i1, i2, i3, i4, cn;

tranif1 n1(i1, 0, a);

tranif1 n2(i1, 0, b);

tranif1 n3(cn, i1, c);

tranif1 n4(i2, 0, b);tranif1 n5(cn, i2, a);

tranif0 p1(i3, 1, a);

tranif0 p2(i3, 1, b);

tranif0 p3(cn, i3, c);

tranif0 p4(i4, 1, b);

tranif0 p5(cn, i4, a);

tranif1 n6(cout, 0, cn);

tranif0 p6(cout, 1, cn);

endmodule

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SPICE Netlist

.SUBCKT CARRY A B C COUT VDD GNDMN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P

MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P

MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P

MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P

MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P

MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P

MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P

MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P

MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P

MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P

MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P

MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P

CI1 I1 GND 2FF

CI3 I3 GND 3FF

CA A GND 4FF

CB B GND 4FFCC C GND 2FF

CCN CN GND 4FF

CCOUT COUT GND 2FF

.ENDS

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Physical Design

Floorplan

Standard cells Place & route

Datapaths Slice planning

Area estimation

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MIPS floorplan

Does the design fit the chiparea budgeted ?Estimates area of major unitsand defines their relativeplacementEstimate wire lengthsEstimates wiring congestion

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MIPS layout

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Taxonomy of On-Chip structures

z Random logic

z Data paths

z Arrays

z Analog

z Input/output (I/O)

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Synthesized MIPS Controller

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Hand-Crafted MIPS Datapath

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Standard Cells

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Synthesized MIPS

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Area Estimationz Need area estimates to make floorplan

z Compare to another block you already designed

z Or estimate from transistor counts

z Budget room for large wiring tracks

Some cell library vendor specify cell layout densities in Kgates/mm2

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Design Verification

Fabrication is slow & expensive MOSIS 0.6m masks: $1000, 3 months State of art masks (130nm): $1M, 1 month

Debugging chips is very hard Limited visibility into operation

Prove design is right before building! System simulation (C/C++) Logic simulation (HDL testbench) Circuit simulation / formal verification

Layout vs. schematic comparison Design & electrical rule checks

Verification is > 50% of effort on most chips !

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Fabrication

Tapeout final layout

Formats for mask descriptions:CIF (academia) and GDS II (industry)

Fabrication

6, 8, 12 wafers (bare wafer costs $1000-$5000)

Optimized for throughput, not latency (turnaround times up to 10weeks !)

Cut into individual dice

Fabs cost billions of dollars and become obsolete in a few years

Fabless semiconductor companies

Manufacturing Companies: TSMS, UMC, IBM

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Packaging

Bond gold wires from die I/O pads to package

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Testing

Test that chip operates Design errors

Manufacturing errors

A single dust particle or wafer defect kills a die Yields from 90% to < 10%

Depends on die size, maturity of process

Test each part before shipping to customer

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Summary

z Many chip designers spend much of their timespecifying circuits with HDL and seldom look atthe actual transistor

z However:z Chip Design is not software engineering

z It requires a fundamental understanding of

circuit and physical designz The best way to learn VLSI design is by doing it

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Summary cont.

Now you know everything to start designing a

simple chip !