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Register and Counter Design

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Registers in the Basic Computer

Registers are basic building blocks in

digital systems.

store information auxiliary circuits may modify stored

information or steer it to and from register

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Registers and Counters

A register is a set of flip flops, often supplemented byadditional circuits to control input and output.

- can have parallel I/O or serial I/O or combination

Usually, registers are used to store a set of related bits.-bits that collectively represent an integer value

bits of an ASCII character code

-status bits for a device in a computer system (diskcontroller)

Counters are registers that store numeric values along with circuits to increment/decrement the stored value.

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counters

- up-counters, down-counters, up-down

counters

- generalized counters- BCD counters, gray-code counters, ...

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Simple Parallel Load Register

Four bit register.

if LD is high when clockrises,new values are stored

LD should change only whileCLK is high

Registers using gated clocks

-can lead to timing problems.

- increases clock skew

- may lead to violations of flip-flop setup, hold time specs

- extra care needed to ensurecorrect operation

safer to avoid clock gatingwhenever possible

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Preferred Parallel Load

RegisterMultiplexer for eachregister bit.

new value loaded whenLD

is low otherwise, old valuestored, No gated clock,

- minimizing clock skew.

simplifies checking ofsetup and hold timespecs.

can focus on delaysbetween connected flipflops Increases gatecount by about 30%.

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4-bit Shift Register

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2-bit Register

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Serial-in-serial-out Shift Register

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Design of SR FF

library ieee;

use ieee.std_logic_1164.all;

entity ff is

port ( s,r : in std_logic;

q,qbar : out std_logic

);end ff;

architecture behave of ff is

begin

process

begin

if (s = '0' and r = '0') then

q

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SR FF (cont..)elsif (s = '1' and r = '0') then

q

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D-flip flop

library ieee;

use ieee.std_logic_1164.all;

entity dff is

port (d, clk : in std_logic;

q, qbar : out std_logic);

end dff;

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architecture behave of dff is

signal temp : std_logic;begin

process (clk)begin

if (clk'event and clk = '0') then

temp

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SR flip-flop (process)library ieee;

use ieee.std_logic_1164.all;

entity ffclk is

port ( s,r,clk : in std_logic;

q,qbar : out std_logic

);

end ffclk;

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architecture behave of ffclk is

signal temp,tempbar : std_logic;begin

process (clk)begin

if (clk = '1') thenif (s = '0' and r = '0') then

temp

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elsif (s = '1' and r = '0') then

temp

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counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;entity counter4bit is

port (load,clear, clk : in std_logic;

d : in std_logic_vector (3 downto 0);

q : out std_logic_vector (3 downto 0));

end counter4bit;

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architecture behave of counter4bit is

signal temp : std_logic_vector (3 downto 0);

begin

a:process (clk,load,clear,d)begin

if (load = '1') thentemp

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temp

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With second process (b)

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Serial-in-parallel-out Shift

Register

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Synchronous Counter

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Ring Counter

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Up/down counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

-- up/down counterentity counterupdown is

port (load,reset, clk : in std_logic; -- control signal

dir : in std_logic; --

directiond : in std_logic_vector (3 downto 0);

q : out std_logic_vector (3 downto 0));

end counterupdown;

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Waveform (up/down counter)

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Binary counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;entity binarycounter is

port (clk : in std_logic;

q : out std_logic_vector (3 downto 0));

end binarycounter;

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architecture behave of binarycounter is

signal temp : std_logic_vector (3 downto 0);begin

a:process (clk)beginif (clk'event and clk = '0') then

temp

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Waveform (binary counter)

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Mod 2 counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;entity mod2 is

port (clk : in std_logic;

q : out std_logic_vector (3 downto 0));

end mod2;

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architecture behave of mod2 is

signal temp : std_logic_vector (3 downto 0);

begina: process (clk)

begin

if (clk'event and clk = '0') then

if (temp = "0010" ) thentemp

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Waveform (mod 2 counter)