L07 MemoryII Class
-
Upload
samalmasry -
Category
Documents
-
view
233 -
download
0
Transcript of L07 MemoryII Class
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 1/27
CS 152 Computer Architecture andEngineering
Lecture 7 - Memory Hierarchy-II
Krste Asanovic
Electrical Engineering and Computer SciencesUniversity of California at Berkeley
http://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs152
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 2/27
2/17/2009 CS152-Spring’09 2
Last time in Lecture 6
• Dynamic RAM (DRAM) is main form of main memorystorage in use today
– Holds values on small capacitors, need refreshing (hence dynamic) – Slow multi-step access: precharge, read row, read column
• Static RAM (SRAM) is faster but more expensive – Used to build on-chip memory for caches
• Caches exploit two forms of predictability in memoryreference streams
– Temporal locality, same location likely to be accessed again soon – Spatial locality, neighboring location likely to be accessed soon
• Cache holds small set of values in fast memory(SRAM) close to processor
– Need to develop search scheme to find values in cache, andreplacement policy to make space for newly accessed locations
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 3/27
2/17/2009 CS152-Spring’09 3
Placement Policy
0 1 2 3 4 5 6 70 1 2 3Set Number
Cache
Fully (2-way) Set DirectAssociative Associative Mappedanywhere anywhere in only into
set 0 block 4 (12 mod 4) (12 mod 8)
0 1 2 3 4 5 6 7 8 91 1 1 1 1 1 1 1 1 10 1 2 3 4 5 6 7 8 9
2 2 2 2 2 2 2 2 2 20 1 2 3 4 5 6 7 8 9
3 30 1
Memory
Block Number
block 12can be placed
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 4/27
2/17/2009 CS152-Spring’09
Direct-Mapped Cache
Tag Data BlockV
=
BlockOffsetTag Index
t k b
t
HIT Data Word or Byte
2 k
lines
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 5/27
2/17/2009 CS152-Spring’09
2-Way Set-Associative Cache
Tag Data BlockV
=
BlockOffsetTag Index
t k
b
HIT
Tag Data BlockV
DataWordor Byte
=
t
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 6/27
2/17/2009 CS152-Spring’09
Fully Associative Cache
Tag Data BlockV
=
Block
Offset
Tag
t
b
HIT
DataWordor Byte
=
=
t
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 7/272/17/2009 CS152-Spring’09 7
Replacement Policy
In an associative cache, which block from a setshould be evicted when the set becomes full?
• Random
• Least Recently Used (LRU)
• LRU cache state must be updated on every access• true implementation only feasible for small sets (2-way)• pseudo-LRU binary tree often used for 4-8 way
• First In, First Out (FIFO) a.k.a. Round-Robin• used in highly associative caches
• Not Least Recently Used (NLRU)• FIFO with exception for most recently used block or blocks
This is a second-order effect. Why?
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 8/272/17/2009 CS152-Spring’09 8
Word3Word0 Word1 Word2
Block Size and Spatial Locality
Larger block size has distinct hardware advantages• less tag overhead• exploit fast burst transfers from DRAM• exploit fast burst transfers over wide busses
What are the disadvantages of increasing block size?
block address offset b
2 b = block size a.k.a line size (in bytes)
Split CPU
addressb bits32-b bits
Tag
Block is unit of transfer between the cache and memory
4 word block,b=2
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 9/272/17/2009 CS152-Spring’09 9
CPU-Cache Interaction(5-stage pipeline)
PC addr inst
PrimaryInstructionCache
0x4Add
IR
D
nop
hit ?
PCen
Decode,Register
Fetchwdata
R
addr
wdata
rdataPrimaryDataCache
weA
B
YYALU
MD1 MD2
Cache Refill Data from Lower Levels of Memory Hierarchy
hit ?
Stall entireCPU on data
cache miss
To Memory Control
M E
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 10/272/17/2009 CS152-Spring’09 10
Improving Cache Performance
Average memory access time =Hit time + Miss rate x Miss penalty
To improve performance:• reduce the hit time
• reduce the miss rate• reduce the miss penalty
What is the simplest design strategy?
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 11/272/17/2009 CS152-Spring’09
Serial-versus-Parallel Cache andMemory access
α is HIT RATIO: Fraction of references in cache1 - α is MISS RATIO: Remaining references
CACHEProcessorMainMemory
Addr Addr
DataData
Average access time for serial search: t cache + (1 - α ) t mem
CACHEProcessorMainMemory
Addr
DataData
Average access time for parallel search: α t cache + (1 - α )t mem
• Savings are usually small, t mem >> t cache , hit ratio α high
• High bandwidth required for memory path
•Complexity of handling parallel paths can slow t
cache
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 12/272/17/2009 CS152-Spring’09 12
Causes for Cache Misses
• Compulsory: first-reference to a block a.k.a. coldstart misses- misses that would occur even with infinite cache
• Capacity: cache is too small to hold all data needed
by the program- misses that would occur even under perfect
replacement policy
• Conflict: misses that occur because of collisions
due to block-placement strategy- misses that would not occur with full associativity
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 13/272/17/2009 CS152-Spring’09 13
Effect of Cache Parameters on Performance
• Larger cache size
• Higher associativity
• Larger block size
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 14/272/17/2009 CS152-Spring’09 14
Write Policy Choices
• Cache hit: – write through: write both cache & memory
» generally higher traffic but simplifies cache coherence
– write back: write cache only(memory is written only when the entry is evicted)
» a dirty bit per block can further reduce the traffic
• Cache miss: – no write allocate: only write to main memory – write allocate (aka fetch on write): fetch into cache
• Common combinations: – write through and no write allocate – write back with write allocate
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 15/272/17/2009 CS152-Spring’09 15
Write Performance
Tag DataV
=
BlockOffsetTag Index
t kb
t
HIT Data Word or Byte
2 k
lines
WE
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 16/272/17/2009 CS152-Spring’09 16
Reducing Write Hit Time
Problem: Writes take two cycles in memory stage,one cycle for tag check plus one cycle for datawrite if hit
Solutions:• Design data RAM that can perform read and write in onecycle, restore old value after tag miss
• Fully-associative (CAM Tag) caches: Word line onlyenabled if hit
• Pipelined writes: Hold write data for store in single buffer ahead of cache, write cache data during next store’s tagcheck
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 17/272/17/2009 CS152-Spring’09 17
CS152 Administrivia
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 18/272/17/2009 CS152-Spring’09 18
Pipelining Cache Writes
Tags Data
Tag Index Store Data
Address and Store Data From CPU
Delayed Write DataDelayed Write Addr.
=?
=?
Load Data to CPU
Load/Store
LS
1 0
Hit?
Data from a store hit written into data portion of cacheduring tag access of subsequent store
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 19/272/17/2009 CS152-Spring’09 19
Write Buffer to Reduce Read Miss Penalty
Processor is not stalled on writes, and read misses can goahead of write to main memory
Problem: Write buffer may hold updated value of location needed by a read missSimple scheme: on a read miss, wait for the write buffer to go emptyFaster scheme: Check write buffer addresses against read miss addresses, if no
match, allow read miss to go ahead of writes, else, return value in write buffer
DataCache
UnifiedL2 Cache
RF
CPU
Writebuffer
Evicted dirty lines for writeback cacheOR
All writes in writethru cache
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 20/272/17/2009 CS152-Spring’09 20
Block-level Optimizations
• Tags are too large, i.e., too much overhead – Simple solution: Larger blocks, but miss penalty could be large.
• Sub-block placement (aka sector cache) – A valid bit added to units smaller than full block, called sub-blocks
– Only read a sub-block on a miss – If a tag matches, is the word in the cache?
100 300 204
1 1 1 11 1 0 0 0 1 0 1
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 21/27
2/17/2009 CS152-Spring’09 21
Set-Associative RAM-Tag Cache
Not energy-efficient – A tag and data word is read
from every way
Two-phase approach – First read tags, then just
read data from selectedway
– More energy-efficient – Doubles latency in L1 – OK, for L2 and above, why?
=? =?
Tag Status Data Tag Status Data
Tag Index Offset
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 22/27
2/17/2009 CS152-Spring’09 22
Multilevel Caches• A memory cannot be large and fast
• Increasing sizes of cache at each level
CPU L1$ L2$ DRAM
Local miss rate = misses in cache / accesses to cache
Global miss rate = misses in cache / CPU memory accesses
Misses per instruction = misses in cache / number of instructions
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 23/27
2/17/2009 CS152-Spring’09 23
A Typical Memory Hierarchy c.2008
L1 DataCache
L1
InstructionCache Unified L2Cache
RF Memory
Memory
Memory
Memory
Multiportedregister file
(part of CPU)
Split instruction & dataprimary caches(on-chip SRAM)
Multiple interleavedmemory banks
(off-chip DRAM)
Large unified secondary cache(on-chip SRAM)
CPU
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 24/27
2/17/2009 CS152-Spring’09 24
Presence of L2 influences L1 design
• Use smaller L1 if there is also L2 – Trade increased L1 miss rate for reduced L1 hit time and reduced
L1 miss penalty – Reduces average access energy
• Use simpler write-through L1 with on-chip L2 – Write-back L2 cache absorbs write traffic, doesn’t go off-chip – At most one L1 miss request per L1 access (no dirty victim write
back) simplifies pipeline control – Simplifies coherence issues – Simplifies error recovery in L1 (can use just parity bits in L1 and
reload from L2 when parity error detected on L1 read)
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 25/27
2/17/2009 CS152-Spring’09 25
Inclusion Policy
• Inclusive multilevel cache: – Inner cache holds copies of data in outer cache – External access need only check outer cache – Most common case
•Exclusive multilevel caches: – Inner cache may hold data not in outer cache – Swap lines between inner/outer caches on miss – Used in AMD Athlon with 64KB primary and 256KB secondary
cache
Why choose one type or the other?
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 26/27
2/17/2009 CS152-Spring’09 26
Itanium-2 On-Chip Caches(Intel/HP, 2002)
Level 1: 16KB, 4-way s.a.,64B line, quad-port (2load+2 store), single cyclelatency
Level 2: 256KB, 4-way s.a,128B line, quad-port (4load or 4 store), five cyclelatency
Level 3: 3MB, 12-way s.a.,128B line, single 32B port,twelve cycle latency
8/4/2019 L07 MemoryII Class
http://slidepdf.com/reader/full/l07-memoryii-class 27/27
Acknowledgements
• These slides contain material developed andcopyright by:
– Arvind (MIT) – Krste Asanovic (MIT/UCB) – Joel Emer (Intel/MIT) – James Hoe (CMU) – John Kubiatowicz (UCB) – David Patterson (UCB)
• MIT material derived from course 6.823
• UCB material derived from course CS252