kvl flipflops

8/6/2019 kvl flipflops

1/11

Table of ContentsIntroduction

Edge-Triggered Flip-flops Pulse-Triggered (Master-Slave) Flip-flops Data Lock-Out Flip-flops Operating Characteristics Applications

Introduction

Flip-flops are synchronous bistable devices. Theterm synchronous means the output changes stateonly when the clock input is triggered. That is,changes in the output occur in synchronization withthe clock.Flip-flop is a kind of multivibrator. There are three

types ofmultivibrators:

1. Monostable multivibrator (also called one-shot) has

only one stable state. It produces a single pulse in response to

a triggering input.

2. Bistable multivibrator exhibits two stable states. It is

able to retain the two SET and RESET states indefinitely. It is

commonly used as a basic building block for counters, registers

and memories.

3. Astable multivibrator has no stable state at all. It is

used primarily as an oscillator to generate periodic pulse

waveforms for timing purposes.

In this tutorial, the three basic categories ofbistable elements are emphasized: edge-triggeredflip-flop, pulse-triggered (master-slave) flip-flop,and data lock-out flip-flop. Their operatingcharacteristics and basic applications will also bediscussed.
http://www.eelab.usyd.edu.au/digital_tutorial/part2/#Introductionhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop02.htmlhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop03.htmlhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop03.html#DLOhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop04.htmlhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop05.htmlhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/#Introductionhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop02.htmlhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop03.htmlhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop03.html#DLOhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop04.htmlhttp://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop05.html


2/11

Edge-Triggered Flip-flops

An edge-triggered flip-flop changes states either at the positive edge

(rising edge) or at the negative edge (falling edge) of the clock pulse on


3/11

the control input. The three basic types are introduced here: S-R, J-K

and D.

Click on one the following types of flip-flop. Then

its logic symbol will be shown on the left. Notice the

small triangle, called the dynamic input indicator, isused to identify an edge-triggered flip-flop.

Positive edge-triggered (without bubble atClock input):S-R,J-K, and D.Negative edge-triggered (with bubble atClock input):S-R,J-K, and D.

The S-R, J-K and D inputs are called synchronous inputs becausedata on these inputs are transferred to the flip-flop's output only on

the triggering edge of the clock pulse.On the other hand, the direct set

(SET) and clear (CLR) inputs are called asynchronous inputs, as they

are inputs that affect the state of the flip-flop independent of the

clock. For the synchronous operations to work properly, these

asynchronous inputs must both be kept LOW.

Edge-triggered S-R flip-flop

The basic operation is illustrated below, along withthe truth table for this type of flip-flop. Theoperation and truth table for a negative edge-triggered flip-flop are the same as those for apositive except that the falling edge of the clockpulse is the triggering edge.

As S = 1, R = 0. Flip-flop SETS on the

rising clock edge.

Note that the S and R inputs can be changed at any time when the

clock input is LOW or HIGH (except for a very short interval around
http://%20sample1%28%27ffpic%27%29/http://%20sample2%28%27ffpic%27%29/http://%20sample3%28%27ffpic%27%29/http://%20sample4%28%27ffpic%27%29/http://%20sample5%28%27ffpic%27%29/http://%20sample6%28%27ffpic%27%29/http://%20sample1%28%27ffpic%27%29/http://%20sample2%28%27ffpic%27%29/http://%20sample3%28%27ffpic%27%29/http://%20sample4%28%27ffpic%27%29/http://%20sample5%28%27ffpic%27%29/http://%20sample6%28%27ffpic%27%29/


4/11

the triggering transition of the clock) without affecting the output.

This is illustrated in the timing diagram below:

Edge-triggered J-K flip-flop

The J-K flip-flop works very similar to S-R flip-flop. The only

difference is that this flip-flop has NO invalid state. The outputs

toggle (change to the opposite state) when both J and K inputs are

HIGH. The truth table is shown below.

Edge-triggered D flip-flop

The operations of a D flip-flop is much more simpler. It has only one

input addition to the clock. It is very useful when a single data bit (0

or 1) is to be stored. If there is a HIGH on the D input when a clock

pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW

on the D input when a clock pulse is applied, the flip-flop RESETsand stores a 0. The truth table below summarize the operations of the

positive edge-triggered D flip-flop. As before, the negative edge-

triggered flip-flop works the same except that the falling edge of the

clock pulse is the triggering edge.


5/11

Pulse-Triggered (Master-Slave)Flip-flops

The term pulse-triggered means that data are entered into the flip-

flop on the rising edge of the clock pulse, but the output does not

reflect the input state until the falling edge of the clock pulse. As thiskind of flip-flops are sensitive to any change of the input levels during

the clock pulse is still HIGH, the inputs must be set up prior to the

clock pulse's rising edge and must not be changed before the falling

edge. Otherwise, ambiguous results will happen.

The three basic types of pulse-triggered flip-flops are S-R, J-K and D.

Their logic symbols are shown below. Notice that they do not have


6/11

the dynamic input indicator at the clock input but have postponed

output symbols at the outputs.

The truth tables for the above pulse-triggered flip-flops are all the

same as that for the edge-triggered flip-flops, except for the way they

are clocked. These flip-flops are also called Master-Slave flip-flops

simply because their internal construction are divided into two

sections. The slave section is basically the same as the master section

except that it is clocked on the inverted clock pulse and is controlledby the outputs of the master section rather than by the external

inputs. The logic diagram for a basic master-slave S-R flip-flop is

shown below.

Data Lock-Out Flip-flops

The data lock-out flip-flop is similar to the pulse-triggered (master-

slave) flip-flop except it has a dynamic clock input. The dynamic

clock disables (locks out) the data inputs after the rising edge of the

clock pulse. Therefore, the inputs do not need to be held constantwhile the clock pulse is HIGH.

The master section of this flip-flop is like an edge-triggered device.

The slave section becomes a pulse-triggered device to produce a

postponed output on the falling edge of the clock pulse.

The logic symbols of S-R, J-K and D data lock-out flip-flops are


7/11

shown below. Notice they all have the dynamic input indicator as well

as the postponed output symbol.

Again, the above data lock-out flip-flops have same the truth tables as

that for the edge-triggered flip-flops, except for the way they are

clocked.

Operating Characteristics

The operating characteristics mention here apply to all flip-flops

regardless of the particular form of the circuit. They are typically

found in data sheets for integrated circuits. They specify the

performance, operating requirements, and operating limitations of

the circuit.

Propagation Delay Time - is the interval of time requiredafter an input signal has been applied for the resulting output change

to occur.

Set-Up Time - is the minimum intervalrequired for the logic levels to be maintainedconstantly on the inputs (J and K, or S and R, or D)prior to the triggering edge of the clock pulse inorder for the levels to be reliably clocked into theflip-flop.


8/11

Hold Time - is the minimum interval requiredfor the logic levels to remain on the inputs after thetriggering edge of the clock pulse in order for thelevels to be reliably clocked into the flip-flop.Maximum Clock Frequency - is thehighest rate that a flip-flop can be reliablytriggered.Power Dissipation - is the total powerconsumption of the device.Pulse Widths - are the minimum pulse widthsspecified by the manufacturer for the Clock, SET and

CLEAR inputs.

Applications

Frequency Division

When a pulse waveform is applied to the clock input of a J-K flip-flop

that is connected to toggle, the Q output is a square wave with half the

frequency of the clock input. If more flip-flops are connected together

as shown in the figure below, further division of the clock frequency

can be achieved.


9/11

The Q output of the second flip-flop is one-fourth the frequency of the

original clock input. This is because the frequency of the clock isdivided by 2 by the first flip-flop, then divided by 2 again by the

second flip-flop. If more flip-flops are connected this way, the

frequency division would be 2 to the power n, where n is the number

of flip-flops.

Parallel Data Storage

In digital systems, data are normally stored in groups of bits that

represent numbers, codes, or other information. So, it is common to

take several bits of data on parallel lines and store them

simultaneously in a group of flip-flops. This operation is illustrated in

the figure below.


10/11

Each of the three parallel data lines is connected to the

D input of a flip-flop. Since all the clock inputs areconnected to the same clock, the data on the D inputs

are stored simultaneously by the flip-flops on the

positive edge of the clock. Registers, a group of flip-

flops use for data storage, will be explained in more

detail in a later chapter.

Counting

Another very important application of

flip-flops is in digital counters, which

are covered in detail in the next chapter.

A counter that counts from 0to 3 is illustrated in the timingdiagram on the right. Thetwo-bit binary sequencerepeats every four clockpulses. When it counts to 3, itrecycles back to 0 to begin

the sequence again.


11/11

kvl flipflops

Documents

Transcript of kvl flipflops