Khan Shahnawaz Contact 9581119248

Mail khan.shahnawaz141@gmail.com

Address Room no.26, Essa mansion, Hans Road,

Jacob Circle, Mumbai – 400011.

Education M. Tech in Microelectronics and VLSI (CGPA-8.67) 2013 - 2015 Indian Institute of Technology, Hyderabad

I am post graduate student from IIT Hyderabad specialized in Microelectronics and VLSI having an excellent academic record and ability to grow with a team in an organization. I am an enthusiast seeking a challenging career position that would enhance my skills even further.

Major Course Work Digital IC Design and Verification

Analog IC Design

Embedded System

Digital Signal Processing lab

Silvaco TCAD lab

Advanced Digital Circuit Design

VLSI Technology

Semiconductor Device Modelling

More Than Moore Electronics

Skills Programming languages

C / Embedded C / C++

Python / Perl / Tcl

Verilog HDL

Assembly language for 8085 and 8051

Tools known DC Compiler / IC Compiler

Silvaco TCAD

SoC Encounter

ModelSim

Cadence Virtuoso

Xilinx ISE (FPGA – Nexys 3 / Virtex 7)

Experience Intern in Physical Design Engineer May - August 2015 Mediatek, Bangalore

I was involved in working on ASIC design using Synopsys IC Compiler. The internship aimed to gain the practical exposure to the challenges involved in ASIC design from Netlist to GDSII in full chip implementation.

Tcl Scripting

Perl Scripting

Static Timing Analysis

Netlist to GDSII flow

Projects Programmable input clock frequency divider Xilinx ISE and Nexys 3 FPGA Board

Behavioral Verilog HDL code written for a programmable input clock frequency divider was fully FPGA implementable and was tested on Nexys 3 FPGA Board. The user have to give input in the range of 2 to 7 and the input clock of frequency “f” is from “f/2 to f/7”.

Linearized Gm-C based Low Pass filter Design Cadence Virtuoso

Design of a Linearized Gm-C based filter design in Cadence (Virtuoso) using UMC 180nm technology library for folded cascade topology for single ended differential amplifier and CMFB circuit for linearization of trans-conductance for a range of differential input voltages.

256x64 6T SRAM Cell based Memory module Cadence Virtuoso

256x64 6T SRAM Memory Module using UMC 65nm technology library. It was designed and analyzed considering all parasitic effects of transistors and RC extracted parameters of wire was considered.

Induction heating Controller circuit Microcontroller Atmel ATMEGA 128

Design of controller circuit for generating the signal to control the power (current) flowing through the induction heating coil that can be for Industrial and commercial applications.

ECG Feature extraction using HAAR wavelet Visual DSP++

C programming for the detection of P-peak, R-peak, QRS-on, QRS-off for the given ECG signal by developing a very low complex algorithm and running the same on Visual DSP++.

MQCA based low complexity circuit design OOMMF Simulator (Micro Magnetic Simulator)

Designing of Magnetic Quantum based digital circuits. Micromagnets patterned digital circuit was simulated on OOMMF Simulator and various parameters was determined.

Achievements Certification Wired Robotics Workshop under IEEE in August 2009

Participation in National Robotics Contest, Robocon 2010

Certification in ElectroWorks 2010

All India Rank 229 in GATE 2013

Declaration I hereby declare that the above information is true to the best of my knowledge.

Khan Shahnawaz