KE02 Sub-Family Reference Manual - Reference Manual · 2013. 8. 6. · KE02 Sub-Family Reference...

KE02 Sub-Family Reference ManualSupports: MKE02Z16VLC2(R), MKE02Z32VLC2(R),

MKE02Z64VLC2(R), MKE02Z16VLD2(R), MKE02Z32VLD2(R),MKE02Z64VLD2(R), MKE02Z32VLH2(R), MKE02Z64VLH2(R),

MKE02Z32VQH2(R), and MKE02Z64VQH2(R)

Document Number: MKE02Z64M20SF0RMRev 3, July 2013

KE02 Sub-Family Reference Manual, Rev. 3, July 2013

2 Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1About This Document

1.1 Overview.........................................................................................................................................................................33

1.1.1 Purpose.............................................................................................................................................................33

1.1.2 Audience..........................................................................................................................................................33

1.2 Conventions....................................................................................................................................................................33

1.2.1 Numbering systems..........................................................................................................................................33

1.2.2 Typographic notation.......................................................................................................................................34

1.2.3 Special terms....................................................................................................................................................34

Chapter 2Introduction

2.1 Overview.........................................................................................................................................................................35

2.2 Module functional categories..........................................................................................................................................35

2.2.1 ARM Cortex-M0+ core modules.....................................................................................................................36

2.2.2 System modules...............................................................................................................................................37

2.2.3 Memories and memory interfaces....................................................................................................................37

2.2.4 Clocks...............................................................................................................................................................38

2.2.5 Security and integrity modules........................................................................................................................38

2.2.6 Analog modules...............................................................................................................................................38

2.2.7 Timer modules.................................................................................................................................................39

2.2.8 Communication interfaces...............................................................................................................................39

2.2.9 Human-machine interfaces..............................................................................................................................40

2.2.10 Orderable part numbers....................................................................................................................................40

Chapter 3Chip Configuration

3.1 Introduction.....................................................................................................................................................................41

3.2 Module to Module Interconnects....................................................................................................................................41

3.2.1 Interconnection overview.................................................................................................................................41


Freescale Semiconductor, Inc. 3


3.2.2 Analog reference options.................................................................................................................................43

3.2.3 ACMP0 output capture....................................................................................................................................43

3.2.4 UART0_TX modulation..................................................................................................................................43

3.2.5 UART0_RX capture........................................................................................................................................44

3.2.6 UART0_RX filter............................................................................................................................................44

3.2.7 RTC capture.....................................................................................................................................................45

3.2.8 FTM2 software synchronization......................................................................................................................45

3.2.9 ADC hardware trigger......................................................................................................................................45

3.3 Core Modules..................................................................................................................................................................46

3.3.1 ARM Cortex-M0+ core configuration.............................................................................................................46

3.3.1.1 ARM Cortex M0+ core ...............................................................................................................47

3.3.1.2 Buses, interconnects, and interfaces............................................................................................47

3.3.1.3 System Tick Timer.......................................................................................................................48

3.3.1.4 Core privilege levels....................................................................................................................48

3.3.1.5 Caches..........................................................................................................................................48

3.3.2 Nested Vectored Interrupt Controller (NVIC) configuration...........................................................................48

3.3.2.1 Interrupt priority levels................................................................................................................49

3.3.2.2 Non-maskable interrupt................................................................................................................49

3.3.2.3 Interrupt channel assignments......................................................................................................49

3.3.3 Asynchronous wakeup interrupt controller (AWIC) configuration.................................................................52

3.3.3.1 Wakeup sources...........................................................................................................................52

3.4 System Modules..............................................................................................................................................................53

3.4.1 SIM configuration............................................................................................................................................53

3.4.2 PMC configuration...........................................................................................................................................54

3.4.3 MCM configuration.........................................................................................................................................54

3.4.4 Crossbar-light switch configuration.................................................................................................................55

3.4.4.1 Crossbar-Light switch master assignments..................................................................................56

3.4.4.2 Crossbar switch slave assignments..............................................................................................56




3.4.5 Peripheral bridge configuration.......................................................................................................................57

3.4.5.1 Number of peripheral bridges......................................................................................................57

3.4.5.2 Memory maps..............................................................................................................................57

3.5 System Security..............................................................................................................................................................58

3.5.1 CRC configuration...........................................................................................................................................58

3.5.2 Watchdog configuration...................................................................................................................................58

3.5.2.1 WDOG clocks..............................................................................................................................59

3.5.2.2 WDOG operation.........................................................................................................................59

3.6 Clock Modules................................................................................................................................................................60

3.6.1 ICS configuration.............................................................................................................................................60

3.6.1.1 Clock gating.................................................................................................................................61

3.6.2 OSC configuration...........................................................................................................................................61

3.7 Memories and Memory Interfaces..................................................................................................................................62

3.7.1 Flash memory configuration............................................................................................................................62

3.7.1.1 Flash and EEPROM memory sizes..............................................................................................63

3.7.1.2 Flash memory map.......................................................................................................................64

3.7.1.3 Flash security...............................................................................................................................64

3.7.1.4 Erase all flash contents.................................................................................................................64

3.7.2 Flash memory controller configuration............................................................................................................64

3.7.3 SRAM configuration........................................................................................................................................65

3.7.3.1 SRAM sizes..................................................................................................................................66

3.7.3.2 SRAM ranges...............................................................................................................................66

3.8 Analog.............................................................................................................................................................................67

3.8.1 12-bit analog-to-digital converter (ADC) configuration..................................................................................67

3.8.1.1 ADC instantiation information.....................................................................................................68

3.8.1.2 ADC0 connections/channel assignment.......................................................................................68

3.8.1.3 ADC analog supply and reference connections...........................................................................69

3.8.1.4 Temperature sensor......................................................................................................................69

3.8.1.5 Alternate clock.............................................................................................................................70




3.8.2 ACMP configuration........................................................................................................................................70

3.8.2.1 ACMP overview..........................................................................................................................71

3.8.2.2 ACMP interconnections...............................................................................................................71

3.8.2.3 ACMP in Stop mode....................................................................................................................72

3.9 Timers.............................................................................................................................................................................72

3.9.1 FlexTimer configuration..................................................................................................................................72

3.9.1.1 FTM overview..............................................................................................................................73

3.9.1.2 FTM clock options.......................................................................................................................75

3.9.1.3 FTM interconnections..................................................................................................................75

3.9.1.4 FTM interrupts.............................................................................................................................76

3.9.2 PIT configuration.............................................................................................................................................76

3.9.2.1 PIT overview................................................................................................................................77

3.9.2.2 PIT interconnections....................................................................................................................77

3.9.3 RTC configuration...........................................................................................................................................77

3.9.3.1 RTC overview..............................................................................................................................78

3.9.3.2 RTC interconnections..................................................................................................................78

3.10 Communication interfaces..............................................................................................................................................79

3.10.1 SPI configuration.............................................................................................................................................79

3.10.1.1 SPI overview................................................................................................................................79

3.10.2 I2C configuration.............................................................................................................................................80

3.10.2.1 I2C overview................................................................................................................................80

3.10.3 UART configuration........................................................................................................................................80

3.10.3.1 UART overview...........................................................................................................................81

3.10.3.2 UART interconnection.................................................................................................................81

3.11 Human-machine interfaces (HMI)..................................................................................................................................82

3.11.1 GPIO configuration..........................................................................................................................................82

3.11.1.1 GPIO overview............................................................................................................................82

3.11.2 KBI configuration............................................................................................................................................83

3.11.2.1 KBI overview...............................................................................................................................83




3.11.2.2 KBI assignments..........................................................................................................................83

3.11.3 IRQ configuration............................................................................................................................................84

3.11.3.1 IRQ assignment............................................................................................................................84

Chapter 4Memory Map

4.1 Introduction.....................................................................................................................................................................85

4.2 System memory map.......................................................................................................................................................85

4.3 Bit Manipulation Engine.................................................................................................................................................86

4.4 Peripheral bridge (AIPS-Lite) memory map...................................................................................................................86

4.4.1 Read-after-write sequence and required serialization of memory operations..................................................87

4.4.2 Peripheral Bridge (AIPS-Lite) Memory Map..................................................................................................87

4.5 Private Peripheral Bus (PPB) memory map....................................................................................................................91

Chapter 5Clock Distribution

5.1 Introduction.....................................................................................................................................................................93

5.2 Programming model........................................................................................................................................................93

5.3 High-level device clocking diagram...............................................................................................................................93

5.4 Clock definitions.............................................................................................................................................................95

5.4.1 Device clock summary.....................................................................................................................................95

5.4.2 Clock distribution.............................................................................................................................................96

5.5 Internal clocking sources................................................................................................................................................97

5.6 External clock sources....................................................................................................................................................98

5.7 Clock gating....................................................................................................................................................................99

5.8 Module clocks.................................................................................................................................................................99

Chapter 6Reset and Boot

6.1 Introduction.....................................................................................................................................................................101

6.2 Reset................................................................................................................................................................................101

6.2.1 Power-on reset (POR)......................................................................................................................................101




6.2.2 System reset sources........................................................................................................................................102

6.2.2.1 External pin reset (RESET)..........................................................................................................102

6.2.2.2 Low-voltage detect (LVD)...........................................................................................................103

6.2.2.3 Watchdog timer............................................................................................................................103

6.2.2.4 ICS loss-of-clock (LOC)..............................................................................................................103

6.2.2.5 Stop mode acknowledge error (SACKERR) ..............................................................................104

6.2.2.6 Software reset (SW).....................................................................................................................104

6.2.2.7 Lockup reset (LOCKUP).............................................................................................................104

6.2.2.8 MDM-AP system reset request....................................................................................................104

6.2.3 MCU resets......................................................................................................................................................104

6.2.3.1 POR Only ....................................................................................................................................104

6.2.3.2 Chip POR ....................................................................................................................................105

6.2.3.3 Early Chip Reset .........................................................................................................................105

6.2.3.4 Chip Reset ...................................................................................................................................105

6.3 Boot.................................................................................................................................................................................105

6.3.1 Boot sources.....................................................................................................................................................105

6.3.2 Boot sequence..................................................................................................................................................106

Chapter 7Power Management

7.1 Introduction.....................................................................................................................................................................107

7.2 Power modes...................................................................................................................................................................107

7.3 Entering and exiting power modes.................................................................................................................................108

7.4 Module operation in low-power modes..........................................................................................................................108

Chapter 8Security

8.1 Introduction.....................................................................................................................................................................111

8.2 Flash security..................................................................................................................................................................111

8.3 Security interactions with other modules........................................................................................................................112

8.3.1 Security interactions with debug......................................................................................................................112




Chapter 9Debug

9.1 Introduction.....................................................................................................................................................................113

9.2 Debug port pin descriptions............................................................................................................................................113

9.3 SWD status and control registers....................................................................................................................................114

9.3.1 MDM-AP Status Register................................................................................................................................115

9.3.2 MDM-AP control register................................................................................................................................116

9.4 Debug resets....................................................................................................................................................................117

9.5 Debug in low-power modes............................................................................................................................................117

9.6 Debug and security.........................................................................................................................................................118

Chapter 10Signal Multiplexing and Signal Descriptions

10.1 Introduction.....................................................................................................................................................................119

10.2 Pinout..............................................................................................................................................................................119

10.2.1 Signal multiplexing and pin assignments.........................................................................................................119

10.2.2 Device pin assignment.....................................................................................................................................122

10.3 Module signal description tables....................................................................................................................................123

10.3.1 Core modules...................................................................................................................................................123

10.3.2 System modules...............................................................................................................................................124

10.3.3 Clock modules..................................................................................................................................................124

10.3.4 Memories and Memory Interfaces...................................................................................................................124

10.3.5 Analog..............................................................................................................................................................125

10.3.6 Timer modules.................................................................................................................................................125

10.3.7 Communication Interfaces...............................................................................................................................126

10.3.8 Human-machine interfaces (HMI)...................................................................................................................127

Chapter 11Port Control (PORT)

11.1 Introduction.....................................................................................................................................................................129

11.2 Port data and data direction.............................................................................................................................................131

11.3 Internal pullup enable.....................................................................................................................................................132




11.4 Input glitch filter setting..................................................................................................................................................132

11.5 High current drive...........................................................................................................................................................133

11.6 Pin behavior in Stop mode..............................................................................................................................................133

11.7 Port data registers............................................................................................................................................................134

11.7.1 Port Filter Register (PORT_IOFLT)................................................................................................................134

11.7.2 Port Pullup Enable Low Register (PORT_PUEL)...........................................................................................137

11.7.3 Port Pullup Enable High Register (PORT_PUEH)..........................................................................................142

11.7.4 Port High Drive Enable Register (PORT_HDRVE)........................................................................................146

Chapter 12System Integration Module (SIM)

12.1 Introduction.....................................................................................................................................................................149

12.1.1 Features............................................................................................................................................................149

12.2 Memory map and register definition...............................................................................................................................149

12.2.1 System Reset Status and ID Register (SIM_SRSID).......................................................................................150

12.2.2 System Options Register (SIM_SOPT)...........................................................................................................153

12.2.3 Pin Selection Register (SIM_PINSEL)............................................................................................................156

12.2.4 System Clock Gating Control Register (SIM_SCGC).....................................................................................158

12.2.5 Universally Unique Identifier Low Register (SIM_UUIDL)..........................................................................161

12.2.6 Universally Unique Identifier High Register (SIM_UUIDH).........................................................................162

12.2.7 BUS Clock Divider Register (SIM_BUSDIV)................................................................................................162

12.3 Functional description.....................................................................................................................................................163

Chapter 13Power Management Controller (PMC)

13.1 Introduction.....................................................................................................................................................................165

13.2 Low voltage detect (LVD) system..................................................................................................................................165

13.2.1 Power-on reset (POR) operation......................................................................................................................166

13.2.2 LVD reset operation.........................................................................................................................................166

13.2.3 LVD enabled in Stop mode..............................................................................................................................166

13.2.4 Low-voltage warning (LVW)..........................................................................................................................167




13.3 Bandgap reference..........................................................................................................................................................167

13.4 Memory map and register descriptions...........................................................................................................................167

13.4.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................168

13.4.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................169

Chapter 14Miscellaneous Control Module (MCM)

14.1 Introduction.....................................................................................................................................................................171

14.1.1 Features............................................................................................................................................................171

14.2 Memory map/register descriptions.................................................................................................................................171

14.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)....................................................................172

14.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)................................................................172

14.2.3 Platform Control Register (MCM_PLACR)....................................................................................................173

Chapter 15Peripheral Bridge (AIPS-Lite)

15.1 Introduction.....................................................................................................................................................................177

15.1.1 Features............................................................................................................................................................177

15.1.2 General operation.............................................................................................................................................177


15.2.1 Access support.................................................................................................................................................178

Chapter 16Watchdog Timer (WDOG)

16.1 Introduction.....................................................................................................................................................................179

16.1.1 Features............................................................................................................................................................179

16.1.2 Block diagram..................................................................................................................................................180


16.2.1 Watchdog Control and Status Register 1 (WDOG_CS1)................................................................................181

16.2.2 Watchdog Control and Status Register 2 (WDOG_CS2)................................................................................183

16.2.3 Watchdog Counter Register: High (WDOG_CNTH)......................................................................................184

16.2.4 Watchdog Counter Register: Low (WDOG_CNTL).......................................................................................184

16.2.5 Watchdog Timeout Value Register: High (WDOG_TOVALH).....................................................................185




16.2.6 Watchdog Timeout Value Register: Low (WDOG_TOVALL)......................................................................185

16.2.7 Watchdog Window Register: High (WDOG_WINH).....................................................................................186

16.2.8 Watchdog Window Register: Low (WDOG_WINL)......................................................................................186


16.3.1 Watchdog refresh mechanism..........................................................................................................................187

16.3.1.1 Window mode..............................................................................................................................188

16.3.1.2 Refreshing the Watchdog.............................................................................................................188

16.3.1.3 Example code: Refreshing the Watchdog....................................................................................189

16.3.2 Configuring the Watchdog...............................................................................................................................189

16.3.2.1 Reconfiguring the Watchdog.......................................................................................................190

16.3.2.2 Unlocking the Watchdog.............................................................................................................190

16.3.2.3 Example code: Reconfiguring the Watchdog..............................................................................190

16.3.3 Clock source.....................................................................................................................................................191

16.3.4 Using interrupts to delay resets........................................................................................................................192

16.3.5 Backup reset.....................................................................................................................................................192

16.3.6 Functionality in debug and low-power modes.................................................................................................192

16.3.7 Fast testing of the watchdog.............................................................................................................................193

16.3.7.1 Testing each byte of the counter..................................................................................................193

16.3.7.2 Entering user mode......................................................................................................................194

Chapter 17Bit Manipulation Engine (BME)

17.1 Introduction.....................................................................................................................................................................195

17.1.1 Overview..........................................................................................................................................................196

17.1.2 Features............................................................................................................................................................196

17.1.3 Modes of operation..........................................................................................................................................197



17.3.1 BME decorated stores......................................................................................................................................198

17.3.1.1 Decorated store logical AND (AND)...........................................................................................200




17.3.1.2 Decorated store logical OR (OR).................................................................................................201

17.3.1.3 Decorated store logical XOR (XOR)...........................................................................................202

17.3.1.4 Decorated store bit field insert (BFI)...........................................................................................203

17.3.2 BME decorated loads.......................................................................................................................................205

17.3.2.1 Decorated load: load-and-clear 1 bit (LAC1)..............................................................................208

17.3.2.2 Decorated Load: Load-and-Set 1 Bit (LAS1)..............................................................................209

17.3.2.3 Decorated load unsigned bit field extract (UBFX)......................................................................210

17.3.3 Additional details on decorated addresses and GPIO accesses........................................................................211

17.4 Application information..................................................................................................................................................212

Chapter 18Flash Memory Module (FTMRH)

18.1 Introduction.....................................................................................................................................................................215

18.2 Feature.............................................................................................................................................................................215

18.2.1 Flash memory features.....................................................................................................................................216

18.2.2 EEPROM features............................................................................................................................................216

18.2.3 Other flash module features.............................................................................................................................216



18.3.1.1 Wait mode....................................................................................................................................217

18.3.1.2 Stop mode....................................................................................................................................217

18.3.2 Flash and EEPROM memory map...................................................................................................................217

18.3.3 Flash and EEPROM initialization after system reset.......................................................................................218

18.3.4 Flash and EEPROM command operations.......................................................................................................218

18.3.4.1 Writing the FCLKDIV register....................................................................................................219

18.3.4.2 Command write sequence............................................................................................................221

18.3.5 Flash and EEPROM interrupts.........................................................................................................................223

18.3.5.1 Description of flash and EEPROM interrupt operation...............................................................223

18.3.6 Protection.........................................................................................................................................................224




18.3.7 Security............................................................................................................................................................229

18.3.7.1 Unsecuring the MCU using backdoor key access........................................................................229

18.3.7.2 Unsecuring the MCU using SWD................................................................................................230

18.3.7.3 Mode and security effects on flash and EEPROM command availability...................................231

18.3.8 Flash and EEPROM commands.......................................................................................................................231

18.3.8.1 Flash and EEPROM commands...................................................................................................231

18.3.8.2 EEPROM commands...................................................................................................................232

18.3.8.3 Allowed simultaneous flash and EEPROM operations...............................................................232

18.3.9 Flash and EEPROM command summary........................................................................................................233

18.3.9.1 Erase Verify All Blocks command..............................................................................................234

18.3.9.2 Erase Verify Block command......................................................................................................234

18.3.9.3 Erase Verify Flash Section command..........................................................................................235

18.3.9.4 Read once command....................................................................................................................236

18.3.9.5 Program Flash command.............................................................................................................237

18.3.9.6 Program Once command..............................................................................................................238

18.3.9.7 Erase All Blocks command..........................................................................................................239

18.3.9.8 Erase flash block command.........................................................................................................240

18.3.9.9 Erase flash sector command.........................................................................................................240

18.3.9.10 Unsecure flash command.............................................................................................................241

18.3.9.11 Verify backdoor access key command.........................................................................................242

18.3.9.12 Set user margin level command...................................................................................................242

18.3.9.13 Set factory margin level command..............................................................................................244

18.3.9.14 Erase verify EEPROM section command....................................................................................245

18.3.9.15 Program EEPROM command......................................................................................................246

18.3.9.16 Erase EEPROM sector command................................................................................................247


18.4.1 Flash Clock Divider Register (FTMRH_FCLKDIV)......................................................................................248

18.4.2 Flash Security Register (FTMRH_FSEC).......................................................................................................249

18.4.3 Flash CCOB Index Register (FTMRH_FCCOBIX)........................................................................................250




18.4.4 Flash Configuration Register (FTMRH_FCNFG)...........................................................................................251

18.4.5 Flash Error Configuration Register (FTMRH_FERCNFG)............................................................................252

18.4.6 Flash Status Register (FTMRH_FSTAT)........................................................................................................252

18.4.7 Flash Error Status Register (FTMRH_FERSTAT)..........................................................................................253

18.4.8 Flash Protection Register (FTMRH_FPROT).................................................................................................254

18.4.9 EEPROM Protection Register (FTMRH_EEPROT).......................................................................................256

18.4.10 Flash Common Command Object Register:High (FTMRH_FCCOBHI)........................................................257

18.4.11 Flash Common Command Object Register: Low (FTMRH_FCCOBLO)......................................................257

18.4.12 Flash Option Register (FTMRH_FOPT).........................................................................................................257

Chapter 19Flash Memory Controller (FMC)

19.1 Introduction.....................................................................................................................................................................259

19.1.1 Overview..........................................................................................................................................................259

19.1.2 Features............................................................................................................................................................259

19.2 Modes of operation.........................................................................................................................................................260

19.3 External signal description..............................................................................................................................................260



Chapter 20Internal Clock Source (ICS)

20.1 Introduction.....................................................................................................................................................................263

20.1.1 Features............................................................................................................................................................263

20.1.2 Block diagram..................................................................................................................................................264


20.1.3.1 FLL engaged internal (FEI).........................................................................................................264

20.1.3.2 FLL engaged external (FEE)........................................................................................................264

20.1.3.3 FLL bypassed internal (FBI)........................................................................................................265

20.1.3.4 FLL bypassed internal low power (FBILP).................................................................................265

20.1.3.5 FLL bypassed external (FBE)......................................................................................................265




20.1.3.6 FLL bypassed external low power (FBELP)...............................................................................265

20.1.3.7 Stop (STOP).................................................................................................................................265


20.3 Register definition...........................................................................................................................................................266

20.3.1 ICS Control Register 1 (ICS_C1)....................................................................................................................266




20.3.5 ICS Status Register (ICS_S)............................................................................................................................269


20.4.1 Operational modes...........................................................................................................................................270

20.4.1.1 FLL engaged internal (FEI).........................................................................................................271

20.4.1.2 FLL engaged external (FEE)........................................................................................................271

20.4.1.3 FLL bypassed internal (FBI)........................................................................................................272

20.4.1.4 FLL bypassed internal low power (FBILP).................................................................................272

20.4.1.5 FLL bypassed external (FBE)......................................................................................................272

20.4.1.6 FLL bypassed external low power (FBELP)...............................................................................273

20.4.1.7 Stop..............................................................................................................................................273

20.4.2 Mode switching................................................................................................................................................273

20.4.3 Bus frequency divider......................................................................................................................................274

20.4.4 Low-power field usage.....................................................................................................................................274

20.4.5 Internal reference clock....................................................................................................................................274

20.4.6 Fixed frequency clock......................................................................................................................................274

20.4.7 FLL lock and clock monitor.............................................................................................................................275

20.4.7.1 FLL clock lock.............................................................................................................................275

20.4.7.2 External reference clock monitor.................................................................................................275




20.5 Initialization/application information.............................................................................................................................276

20.5.1 Initializing FEI mode.......................................................................................................................................276

20.5.2 Initializing FBI mode.......................................................................................................................................276

20.5.3 Initializing FEE mode......................................................................................................................................276

20.5.4 Initializing FBE mode......................................................................................................................................277

Chapter 21Oscillator (OSC)

21.1 Introduction.....................................................................................................................................................................279

21.1.1 Overview..........................................................................................................................................................279

21.1.2 Features and modes..........................................................................................................................................279

21.1.3 Block diagram..................................................................................................................................................279

21.2 Signal description............................................................................................................................................................280

21.3 External crystal / resonator connections.........................................................................................................................281

21.4 External clock connections.............................................................................................................................................282


21.5.1 OSC Control Register (OSC_CR)....................................................................................................................283


21.6.1 OSC module states...........................................................................................................................................284

21.6.1.1 Off................................................................................................................................................285

21.6.1.2 Oscillator startup..........................................................................................................................286

21.6.1.3 Oscillator stable............................................................................................................................286

21.6.1.4 External clock mode.....................................................................................................................286

21.6.2 OSC module modes.........................................................................................................................................286

21.6.2.1 Low-frequency, high-gain mode..................................................................................................287

21.6.2.2 Low-frequency, low-power mode................................................................................................287

21.6.2.3 High-frequency, high-gain mode.................................................................................................287

21.6.2.4 High-frequency, low-power mode...............................................................................................288

21.6.3 Counter.............................................................................................................................................................288

21.6.4 Reference clock pin requirements....................................................................................................................288




Chapter 22Cyclic Redundancy Check (CRC)

22.1 Introduction.....................................................................................................................................................................289

22.1.1 Features............................................................................................................................................................289

22.1.2 Block diagram..................................................................................................................................................289


22.1.3.1 Run mode.....................................................................................................................................290

22.1.3.2 Low-power modes (Wait or Stop)...............................................................................................290


22.2.1 CRC Data register (CRC_DATA)...................................................................................................................291

22.2.2 CRC Polynomial register (CRC_GPOLY)......................................................................................................292

22.2.3 CRC Control register (CRC_CTRL)................................................................................................................292


22.3.1 CRC initialization/reinitialization....................................................................................................................293

22.3.2 CRC calculations..............................................................................................................................................294

22.3.2.1 16-bit CRC...................................................................................................................................294

22.3.2.2 32-bit CRC...................................................................................................................................294

22.3.3 Transpose feature.............................................................................................................................................295

22.3.3.1 Types of transpose.......................................................................................................................295

22.3.4 CRC result complement...................................................................................................................................297

Chapter 23Interrupt (IRQ)

23.1 Introduction.....................................................................................................................................................................299

23.2 Features...........................................................................................................................................................................299

23.2.1 Pin configuration options.................................................................................................................................300

23.2.2 Edge and level sensitivity................................................................................................................................301

23.3 Interrupt pin request register...........................................................................................................................................301

23.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................301




Chapter 24Analog-to-digital converter (ADC)

24.1 Introduction.....................................................................................................................................................................303

24.1.1 Features............................................................................................................................................................303

24.1.2 Block Diagram.................................................................................................................................................304

24.2 External Signal Description............................................................................................................................................304

24.2.1 Analog Power (VDDA)...................................................................................................................................305

24.2.2 Analog Ground (VSSA)...................................................................................................................................305

24.2.3 Voltage Reference High (VREFH)..................................................................................................................305

24.2.4 Voltage Reference Low (VREFL)...................................................................................................................305

24.2.5 Analog Channel Inputs (ADx).........................................................................................................................305


24.3.1 Clock select and divide control........................................................................................................................306

24.3.2 Input select and pin control..............................................................................................................................307

24.3.3 Hardware trigger..............................................................................................................................................307

24.3.4 Conversion control...........................................................................................................................................308

24.3.4.1 Initiating conversions...................................................................................................................308

24.3.4.2 Completing conversions...............................................................................................................308

24.3.4.3 Aborting conversions...................................................................................................................308

24.3.4.4 Power control...............................................................................................................................309

24.3.4.5 Sample time and total conversion time........................................................................................309

24.3.5 Automatic compare function............................................................................................................................311

24.3.6 FIFO operation.................................................................................................................................................311

24.3.7 MCU wait mode operation...............................................................................................................................314

24.3.8 MCU Stop mode operation..............................................................................................................................315

24.3.8.1 Stop mode with ADACK disabled...............................................................................................315

24.3.8.2 Stop mode with ADACK enabled................................................................................................315




24.4 Initialization information................................................................................................................................................316

24.4.1 ADC module initialization example................................................................................................................316

24.4.1.1 Initialization sequence..................................................................................................................316

24.4.1.2 Pseudo-code example...................................................................................................................317

24.4.2 ADC FIFO module initialization example.......................................................................................................317

24.4.2.1 Pseudo-code example...................................................................................................................318

24.5 Application information..................................................................................................................................................319

24.5.1 External pins and routing.................................................................................................................................319

24.5.1.1 Analog supply pins.......................................................................................................................319

24.5.1.2 Analog reference pins..................................................................................................................319

24.5.1.3 Analog input pins.........................................................................................................................320

24.5.2 Sources of error................................................................................................................................................321

24.5.2.1 Sampling error..............................................................................................................................321

24.5.2.2 Pin leakage error..........................................................................................................................321

24.5.2.3 Noise-induced errors....................................................................................................................321

24.5.2.4 Code width and quantization error...............................................................................................322

24.5.2.5 Linearity errors.............................................................................................................................323

24.5.2.6 Code jitter, non-monotonicity, and missing codes.......................................................................323

24.6 ADC Control Registers...................................................................................................................................................324

24.6.1 Status and Control Register 1 (ADC_SC1)......................................................................................................324




24.6.5 Conversion Result Register (ADC_R).............................................................................................................331

24.6.6 Compare Value Register (ADC_CV)..............................................................................................................332

24.6.7 Pin Control 1 Register (ADC_APCTL1).........................................................................................................333




Chapter 25Analog comparator (ACMP)

25.1 Introduction.....................................................................................................................................................................335

25.1.1 Features............................................................................................................................................................335


25.1.2.1 Operation in Wait mode...............................................................................................................336

25.1.2.2 Operation in Stop mode...............................................................................................................336

25.1.2.3 Operation in Debug mode............................................................................................................336

25.1.3 Block diagram..................................................................................................................................................336



25.3.1 ACMP Control and Status Register (ACMPx_CS)..........................................................................................338

25.3.2 ACMP Control Register 0 (ACMPx_C0)........................................................................................................339




25.5 Setup and operation of ACMP........................................................................................................................................341

25.6 Resets..............................................................................................................................................................................342

25.7 Interrupts.........................................................................................................................................................................342

Chapter 26FlexTimer Module (FTM)

26.1 Introduction.....................................................................................................................................................................343

26.1.1 FlexTimer philosophy......................................................................................................................................343

26.1.2 Features............................................................................................................................................................344


26.1.4 Block diagram..................................................................................................................................................346

26.2 FTM signal descriptions.................................................................................................................................................348


26.3.1 Memory map....................................................................................................................................................348




26.3.2 Register descriptions........................................................................................................................................348

26.3.3 Status And Control (FTMx_SC)......................................................................................................................352

26.3.4 Counter (FTMx_CNT).....................................................................................................................................354

26.3.5 Modulo (FTMx_MOD)....................................................................................................................................354

26.3.6 Channel (n) Status And Control (FTMx_CnSC)..............................................................................................355

26.3.7 Channel (n) Value (FTMx_CnV).....................................................................................................................357

26.3.8 Counter Initial Value (FTMx_CNTIN)............................................................................................................358

26.3.9 Capture And Compare Status (FTMx_STATUS)............................................................................................359

26.3.10 Features Mode Selection (FTMx_MODE)......................................................................................................361

26.3.11 Synchronization (FTMx_SYNC).....................................................................................................................362

26.3.12 Initial State For Channels Output (FTMx_OUTINIT).....................................................................................365

26.3.13 Output Mask (FTMx_OUTMASK).................................................................................................................366

26.3.14 Function For Linked Channels (FTMx_COMBINE).......................................................................................368

26.3.15 Deadtime Insertion Control (FTMx_DEADTIME).........................................................................................373

26.3.16 FTM External Trigger (FTMx_EXTTRIG).....................................................................................................374

26.3.17 Channels Polarity (FTMx_POL)......................................................................................................................376

26.3.18 Fault Mode Status (FTMx_FMS).....................................................................................................................378

26.3.19 Input Capture Filter Control (FTMx_FILTER)...............................................................................................380

26.3.20 Fault Control (FTMx_FLTCTRL)...................................................................................................................381

26.3.21 Configuration (FTMx_CONF).........................................................................................................................383

26.3.22 FTM Fault Input Polarity (FTMx_FLTPOL)...................................................................................................384

26.3.23 Synchronization Configuration (FTMx_SYNCONF)......................................................................................386

26.3.24 FTM Inverting Control (FTMx_INVCTRL)....................................................................................................388

26.3.25 FTM Software Output Control (FTMx_SWOCTRL)......................................................................................389

26.3.26 FTM PWM Load (FTMx_PWMLOAD).........................................................................................................391


26.4.1 Clock source.....................................................................................................................................................393

26.4.1.1 Counter clock source....................................................................................................................393

26.4.2 Prescaler...........................................................................................................................................................394




26.4.3 Counter.............................................................................................................................................................394

26.4.3.1 Up counting..........................................................................

KE02 Sub-Family Reference Manual - Reference Manual · 2013. 8. 6. · KE02 Sub-Family Reference...

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Transcript of KE02 Sub-Family Reference Manual - Reference Manual · 2013. 8. 6. · KE02 Sub-Family Reference...