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“DESIGN AND IMPLEMENTATION OF ALU USING FPGA”

A Synopsis Report

Submitted in partial fulfillment of the requirement for the award of degree of

Master of Technology [VLSI !SI"#$ Submitted To

RA%IV "A#&I 'R()*("I+I VIS&,AVI*ALA*A- .&('AL /M0'01

Submitted by

+A'IL "()R

[2324!533MT36$

)nder the super7ision of

")I! #AM!

epartment of !lectronics 8 5ommunication !ngineering

R+9 Institute of Science 8 Technology- .hopal





5!RTI9I5AT!

This is to certify that the work embodies in this Synopsis entitled :!SI"# A#

IM'L!M!#TATI(# (9 AL) )SI#" 9'"A; being Submitted by +A'IL

"()R [2324!533MT36$ in partial fulfillment of the requirement for the award of

Master of Technology in :VLSI !SI"#; to RAJIV GA!"I #R$%!&$GI'I

VIS"(AVI!&A)A&A*+"$#A),-.#./ during the academic year <23< is a record

of bonafide piece of work* carried out by him under my super0ision and guidance in

the epartment of !lectronics 8 5ommunication !ngineering R'!1 Institute of

Science 2Technology* +hopal0

Appro7ed by

Guide or #ro3ect Ad0isor "ead of the department

MR0 SA&A.AT

&ASA#

9orwarded by

, MR0 +0+0 'A)RA#I+ /



!irector



5!RTI9I5AT! (9 A''R(VAL

The Synopsis entitled :!SI"# A# IM'L!M!#TATI(# (9 AL) )SI#"

9'"A; being submitted by 'A#I) G$%R [2324!533MT36$has been e4amined

by us and is hereby appro0ed for the award of degree :Master of Technology in

:VLSI !SI"#;- for which it has been submitted. It is understood that by this

appro0al the undersign do not necessarily endorse or appro0e any statement made*

opinion e4pressed or conclusion drawn therein* but appro0e the dissertation only

for the purpose for which it has been submitted.

/Internal !=aminer1 /!=ternal !=aminer1



R+9 Institute of Science 8 Technology- .hopalepartment of !lectronics 8 5ommunication !ngineering

!5LARATI(#

I +A'IL "()R- a student of :M0Tech in :VLSI !SI"#; *session <23<

R+9 Institute of Science 8Technology- .hopal/M0'01 here by informed that the

work presented in this dissertation entitled :!SI"# A# IM'L!M!#TATI(#

(9 AL) )SI#" 9'"A; is the outcome of my own work* is bonafide and correct to

the best of my knowledge and this work has been carried out taking care of

5ngineering 5thics. The work presented does not infringe any patented work and has

not been submitted to any other %ni0ersity or anywhere else for the award of any

degree or any professional diploma.

+A'IL "()R

!nrollment #o> 2324!533MT36



A5+#(,L!"!M!#T

I take an opportunity to acknowledge and e4tend my heartfelt gratitude to my guide

and the pi0ot of this enterprise* #rof. G%I!5 who is most responsible for helping me

complete this work. "e showed me different ways to approach the problems and the

need to be persistent to accomplish my goal. "is discernment in the choice of topic*

his confidence in me when I doubted myself and his admirable guidance are some

cogent reasons that make me a0er that without his support this thesis would be a

chimera.

I am also thankful to* !irector* MR0 +0+0 'A)RA#I+ "ead of !epartment of

5lectronics and 6ommunication 5ngineering MR0 SA&A.AT &ASA# for

cooperation and support to complete this work. I would also like to e4press my thanks

to* Group !irector* and R'!1 +hopal pro0iding necessary facilities. I would also

con0ey my Thanks to and of !epartment of 5lectronics and 6ommunication

5ngineering for their continues support. Thanks are due to all the staff members and

lab technicians of !epartment of 5lectronics and 6ommunication 5ngineering R'!1

for pro0iding all help and support.

+A'IL "()R



!nrollment #o> 2324!533MT36

5(#T!#TS

A.STRA5T 'A"! #(0

5&A'T!R > 3 7

I#TR()5TI(# 8

7 A)% 8

5&A'T!R> < 9

LIT!RAT)R! S)RV!* 8 'R(.L!M 9(RM)LATI(# 6

8 A)% design and operation :8.7 multiple4er design ;

8.8 adder design 7<

8.8.7 half adder 7<8.8.8 full adder 78

8.8.= >?bit ripple carry adder 7>

8.= tri state buffer 7@

5&A'T!R> ? 7:

'R('(S! M!T&( /T!5&I#@!-T((LS1 7;

= 6$6)%SI$ 2 1%T%R5 S6$#5 7

R!9!R!#5!S 8<



LIST (9 9I")R!S

#ame of 9igure 'age #o07 symbol for an A)% >

8 block diagram of A)% @= show the circuit le0el diagram of the 8 B7 multiple4er

=.7 >B7 multiple4er

=.8 block diagram of multiple4er logic at the input stage 7<=. = block diagram of multiple4er logic at the output stage 77

> logic le0el diagram of half adder 78@ logic le0el diagram of full adder 7=

9 block diagram of >?bit ripple carry adder 7>: block diagram of tri state buffer 7@

; schematic of tri state buffer 7@



LIST (9 TA.L!S

Sr0 #o #ame of Table 'age #o0

7. Table 7.7 8B7 multiple4er ;

8. Table 7.8 >B7 multiple4er

=. Table 7.= estimated area of multiple4er 7<

>. Table 8 half adder 77

@. Table = full adder 7=

9. Table >.7 acti0e low tri state buffer 7@

:. Table >.8 acti0e high tri state buffer 7@



5&A'T!R > 3



I#TR()5TI(#

3 AL)

TodayCs world requires faster processor for the computation purposes to meet the application

demand of the digital systems. (ith the constant growth of computer applications in e0ery fieldof engineering such as signal processing* communications and neural networks* fast arithmetic

logic units ,A)%/ are increasingly required. The A)% of any processor perform many functionssuch as Addition* Subtraction* -ultiplication* !i0ision and )ogical 6omparison etc. Thesearithmetic operations produce carry propagation chains. The speed of operations depends on the

implementation of arithmetic algorithms.

A)% can be designed using ripple carry or carry look ahead adder. +ut in case of ripple carry

adder the delay will be more as the carry should be propagated entire bit width. So speed will be

reduced. 6arry look ahead adders are faster than ripple carry adders but the comple4ity of the

circuitry increases as the number of bits increases.

A)% is a building block of se0eral circuits. %nderstanding how an A)% is designed and how it

works is essential to building any ad0anced logic circuits. %sing this knowledge and e4perience*

we can mo0e on to designing more comple4 integrated circuits. (hen designing the A)% we

will follow the principle D!i0ide and 6onquerD in order to use a modular design that consists of

smaller* more manageable blocks* some of which can be re?used. Instead of designing the >?bit



A)% as one circuit we will first design a one?bit A)%* also called a bit?slice. These bit?slices can

then be put together to make a >?bit A)%.

The A)% is the part of a microprocessor or a microcontroller that handles all +oolean and

mathematical operations. It is a fundamental building block of the central processing unit of a

computer. -icroprocessor has traditionally been design around these essential unit like decoding

unit* A)% ,arithmetic and logic unit/* timing and control unit. Arithmetic and logically related

operation in microprocessor perform by A)% unit. 6ontents of many different circuits put on a

single chip* makes an integrated circuit. (ith introduction of the integrated circuit* all the

peripheral de0ices and microprocessor was put on a single de0ice. This led to de0elopment of a

microcontroller. A microcontroller differs from microprocessor in many ways. -ost important

aspect is with the functionality. In order for a microprocessor to be functional* other componentsas memory or components for recei0ing and sending data must be added to it. In short

microprocessor is the 0ery heart of the computer. $n the other hand* microcontroller is designed

to be all of that in one. o other e4ternal components are needed for its application as all

necessary components are built to it. Thus we sa0e the time and space needed to construct

de0ices. -icrocontroller also performs arithmetic and logical operation with the help of A)%.

-icrocontroller identified as basic registers* A)%* memory* control and timing unit. !ual?A)%s

are used to e4ecute instructions concurrently for fine?grained parallelism. %p to three

instructions can be e4ecuted simultaneously by 6RIS6. "ere* 6RIS6 architecture design

considerations and instruction cache scheme are in0estigated . The combination of logic styles

and low power E$R gates is used F7. !ouble edge?triggered flip?flops are used to reduce the

switching acti0ity for the register.

http://en.wikipedia.org/wiki/Central_processing_unit





AL) ,Arithmetic and Logic )nit1

A typical schematic symbol for an A)%H A 2 + are operands R is the output 1 is the input from

the 6ontrol %nit ! is an output status. The function of timing and control unit is pro0iding

synchroniation and control the flow of direction of data.

9igure 30 Symbol for an AL)

Sie of the operand is depending on the register length and the length of the data bus of the

processor. )ength of the A)%* used in processor may be > bit* ; bit and may be 79 bit. ItCs

depending upon the type of the processor. 1loating point calculation can be done with the help of

co?processor ,;<;:/.

+lock diagram of A)% 1or the design of > bit A)% we use AF=?AF< and +F=?+F<."ere A

and + are the input of A)% and &F=?&F< are output of the A)%. 1our control line are used

SF8?SF<.If carry is generated during addition operation* itCs reflected by the carry flag of the

http://en.wikipedia.org/wiki/Control_Unit


http://en.wikipedia.org/wiki/Image:ALU_symbol.svg




flag register. 1lag register reflect the result of the A)% unit. The length of the flag register in

;<;@ processor is ; bit and in ;<;9 is 79 bit. 1lag show the status of the accumulator. 1lags are

parity flag* sign flag* au4iliary carry flag* ero flag* carry flag. These flags used in ;<;@.some

e4tra flags used in ;<;9 are o0er flow flag* trap flag* directional flag* interrupt flag and rest of

the bit of flag register are donCt care.

9igure <0 .loc iagram of AL)



5&A'T!R> <



LIT!RAT)R! S)RV!* 8 'R(.L!M 9(RM)LATI(#

< AL) esign and (peration

A programmable arithmetic logic unit for performing high speed bit sliced* pipelined

computations at 0ery low power is fabricated as an )SI component. It is micro programmable

and operates in con3unction with a fast micro program store program memory and controller.!ual input ports which supply data from eight sources are latched and operated on while new

data is simultaneously fetched. The A)% is a digital function that implements basic micro?

operations on the information stored in registers. The full adder design has been implemented

using 6-$S in0erters. The A)% has four stages* each stage consisting of three partsH a/ input

multiple4ers b/ full adder and c/ output multiple4ers. The A)% performs the following four

arithmetic operations* A!!* and S%+TRA6T* I6R5-5T and !56R5-5T. The four

logical operations performed are 5E?$R* 5E?$R* A! and $R. The input and output sections

consist of > to 7 and 8 to 7 multiple4ers. A set of three select signals has been incorporated in the

design to determine the operation being performed and the inputs and outputs being selected.

The full adder design has been implemented using 6-$S in0erters.

A)% with the 6ARR& bit cascading all the way from first stage to fourth stage. The A)% design

consisting of eight > to 7 multiple4ers* eight 8 to 7 multiple4ers and four full adders. The >?bit

A)% was designed using .78 micron technology. This chapter e4plains in detail the >?bit A)%

design. All of the multiple4ers ha0e been implemented using pass transistors* and the full adder

alone has been designed. 5ach stage is discussed in detail in the further sections of this chapter.



<03 Multiple=er esign

The multiple4ers ha0e been used in the A)% design for input and output signals selection. There

are two kinds of multiple4ers implementedH 8 to 7 multiple4er and > to 7multiple4er. The width

of #-$S transistors in multiple4ers has been increased to reduce rise and fall times F:.

Table 303 Truth table of a < to 3

multiple=er

Select signal S8 Selected input

< I<

7 I7

9ig0 ?0 Shows the circuit le7el diagram of the < to 3 M)B0

The output of the multiple4er stage is passed as input to the full adder. A combination of the 8

to 7 -%E at the input and output stage selects the signals depending on the operation being

performed. Transmission gates select one of the inputs based on the 0alue of the control signal.

The input and output stage ha0e a combination of 8 to 7 -%E to select one signal from a set of

two signals. The input and select signals ha0e been named as In and Sn respecti0ely* with the

subscript n indicating the correct signal number F@.

Status of control signal decides which input signal is select. The input and the output stages ha0e

a combination of > to 7 multiple4er to select one signal from a set of four signals.



9igure ?0<C .loc diagram of multiple=er logic at the input stage0

At the input stage* the output of the multiple4er is send to full adder.

9igure ?0?C .loc diagram of multiple=er logic at the output stage0

Table 30? !stimated Area of Multiple=er

T&#5!5)A&

,ns/

AR5A ,(

in u- B " in u-/

7 +it 847 -u4 <.<7 [email protected] B 77.7



>47 -u4 <.<7 8>.9 B =;.>

; +it 847 -u4 <.<7 7;.7@ B ;<.@@

<0< esign of adder

The function of Addison in A)% unit is performed by the adder. Two types of adder is a0ailable*

half adder and full adder.

<0<03 &alf Adder

"alf adder is a logical circuit that performs an addition operation on two binary digits. The half

adder produces a sum and a carry 0alue which are both binary digits. 1igure 9 logic le0el

diagram of a full adder

!quation for S)M and

5arry

S K A 4or + ,=.7/

6 K A and + ,=.8/

9igure 4 logic le7el diagram of a &alf adder0

Table < Truth table of a for half adder



<0<0< 9ull Adder esign

In A)%* full adder forms the core of the entire design. The full adder performs the computing

function of the A)%. A full adder could be defined as a combinational circuit that forms the

arithmetic sum of three input bits. It consists of three inputs and two outputs. In our design* we

ha0e designated the three inputs as A* + and 6in. The third input 6in represents carry input to

the first stage. The outputs are S%- and 6ARR&. 1igure : shows the logic le0el diagram of a

full adder. The +oolean e4pressions for the S%- and 6ARR& bits are as shown below.

SUM = Α⊕ Β ⊕C ΙΝ ,=.=/

CARRY = Α • Β + Α• C ΙΝ + Β •C ΙΝ ,=.>/

S%- bit is the 5?E$R function of all three inputs and 6ARR& bit is the A! function of the

three inputs. The truth table of a full adder is shown in Table =.@. The truth table also indicates

the status of the 6ARR& bit that is to say* if that carry bit has been generated or deleted or

propagated. !epending on the status of input bits A and +* the 6ARR& bit is either generated or

deleted or propagated F78. If either one of A or + inputs is L7C* then the pre0ious carry is 3ust

Input

A

Input

.

(utput

5

(utput

S

2 2 2 2

2 3 3 2

3 2 3 2

3 3 2 3



propagated* as the sum of A and + is L7C. If both A and + areL7Cs then carry is generated because

summing A and + would make output S%- L<C and 6ARR& L7C. If both A and + are L<Cs then

summing A and + would gi0e us L<C and any pre0ious carry is added to this S%- making

6ARR& bit L<C. This is in effect deleting the 6ARR&. To construct an n?bit adder we ha0e to

cascade n such 7?bit adders.

9igure DC Logic le7el diagram of a full adder0

Table ? Truth table of a full adder

A . 5in S)M 5ARR*5arry

Status

< < < < < !elete

< < 7 7 < !elete

< 7 7 7 < #ropagate

< 7 < < 7 #ropagate

7 < < 7 < #ropagate

7 < 7 < 7 #ropagate

7 7 7 < 7 Generate7 7 7 7 7 Generate



<0<0? 4>.it Ripple 5arry Adder

The full adder is configured as ripple carry adder. (e ha0e used this ripple carry adder ,R6A/

configuration in our A)% design. In R6A* the 6ARR& bit ripples all the way from first stage to

nth stage. 1igure ; shows the block diagram of a four?bit ripple carry adder. The delay in a R6A

depends on the number of stages cascaded and also the input bitsC patterns.

1or certain input patterns* a 6ARR& is neither generated nor propagated. This way the 6ARR&

bit need not ripple through the stages. This effecti0ely reduces the delay in the circuit. $n the

other hand* certain input patterns generate carry bit in the first stage itself* which might ha0e toripple through all the stages. This definitely increases the delay in the circuit. The propagation

delay of such a case* also called critical path* is defined as worst?case delay o0er all possible

input patterns. 1igure ;H +lock diagram of a >?bit ripple carry adder. In a ripple carry adder* the

worst?case delay occurs when a carry bit propagates all the way from least significant bit

position to most significant bit position. The total delay of the adder would be an addition of

delay of a S%- bit and delay of a 6ARR& bit multiplied by number of bits minus one in the

input word* gi0en by 5q. ,=.@/ F7=.

Tadder E /#>31 Tcarry F Tsum /?0D1

(here is number of bits in input word* Tcarry and Tsum are propagation delays from one stage to

another. 1or an efficient ripple carry adder* it is important to reduce T carry than Tsum as the former

influences the total adder delay more.

9igure GC .loc diagram of a 4>bit ripple carry adder0



<0? Tri State buffer

!e0ice used in digital circuit operate by recei0ing and producing two logic state signals* a logic

7 and logic <.

$ne type of de0ice that is used in digital circuits recei0es the two logic state but produces three

different type of output signals .+ecause it generate three different signals* it is called a three?

state buffer or tri state buffer.

9igure 60 Tri state buffer

The function of control line is to enable the buffer

to operate when an input signal is applied* or to be

disabling when the signal is recei0ed. There are two type of control lines* an acti0e?high and an

acti0e?low.

5 H

2 B

3 H

6ontrol line M c

Input line ? 4 Table 403 acti7e>low tri state buffer

$utput line ?

6 N

< N

7 E

Table 40< acti7e>high tri state buffer

This buffer is used on input output ,I$/ pins where single pin is used as input with enable high

and as an output with enable low. 1igure 7< shows schematic of a tri state buffer.

9ig Schematic of Tri



State buffer

The output is al a floating state when both pmos and nmos transistors are turned off. It will be

like open circuit and thus passing an ideal ero current through the output i.e. keeping

impedance*

NKVOI P. ,=.9/

(hen enable signal is high* the output is followed by the input. If logic high is to be passed* then

output will follow through the pmos transistor. If a logic ero is to be transferred* output is

followed through nmos transistor. A floating state is said to occur only when enable is reset* i.e.

both the transistors dri0ing the output to a pin are turned off. The total delay of the circuit was

<.<7nS with a total layout area of 7>.><,(/ B 7.>,"/. The peak current through nmos is

<.7ma at 7.8 V Vdd supply. And that for pmos is <.:@>ma at 7.80 Vdd supply. Addition latches

with only n?-$S clocked transistors are used to interface logic operating at different power

supplies and achie0e static power free operation.



5&A'T!R> ?

'roposed Method /Techinque-Tools1

A)% can be designed using ripple carry or carry look ahead adder. +ut in case of ripple carry

adder the delay will be more as the carry should be propagated entire bit width. So speed will bereduced. 6arry look ahead adders are faster than ripple carry adders but the comple4ity of the

circuitry increases as the number of bits increases. %se of non?con0entional number systems in

designing A)% is gaining attention in recent years because of their facility to pro0ide carry freeaddition thus enhancing the achie0able processing speed. 1or making the processing faster a

carry free addition technique is adopted by using Redundant +inary umber System F7F8F;.

The property of carry propagation chain elimination tends to make the processing faster.



In this paper* the R+S! based arithmetic and logical unit is designed using V"!) and its RT)

0iew is generated by its 1#GA implementation. The 1#GA Implementation is done in

54ampleH 6arry M1ree addition using redundant signed radi4 8

In con0entional binary number system radi4 8 number digit set contains <* 7. The number of

digits equal to radi4.54ampleH umber 9 can be represented in binary as below

< 7 7 <

umber > can be represented as below< 7 < <

In case of redundant Signed radi4 8 number digit set contains Q?7*<*7. The number of digits

present in the digit set will be more than the radi4. So each number can be represented in many

ways.54ampleH umber 9 in decimal can be represented in redundant binery as follows.

< 7 7 < ??????? 9

7 < ?7 < ??????? 9 umber > can be represented in redundant binary as follows

< 7 < < ?????????? >

7 ?7 < < ?????????? >

In case of con0entional binary addition there will be carry propagation. 6arry will be propagated

till the end.

Addition in case of R+S! is carry free.

In case of R+S! addition the two operands will be added to get the position sum,pi/. Then the position sum will be di0ided into interim sum ,wi/ and transfer digit,ti/. Then interim sum and

transfer digit is added to get the final sum.

In case of con0entional binary there is no such step.)et the two operanads be Ei K < 7 7 < and &i K < 7 < 7

Ei K < 7 7 < ??????? , 9/7<

&i K < 7 < 7 ??????? ,@/7<The final sum should be , 77/7<

Adding these two numbers using binary.

< 7 7 < ???? Ei

< 7 < 7 ???? &i

? 5(#5L)SI(# 8 9)T)R! S5('!

This section includes conclusion drawn on basis of functional simulation results as well asimplementation of A)%. +y using V"!) we design A)% and we can perform arithmetic and

logical operation. It is a fundamental building block of the central processing unit of a

computer.A)% is a building block of se0eral circuits. %nderstanding how an A)% is designed and

how it works is essential to building any ad0anced logic circuits. !esign consists of different kind of

logicRipple carry adder* full adder* A!* $R* $R* !11* -%E. Simply* to operate on k?bit






0alues* we can connect k 7?bit A)%s. >?bit A)% is constructed using four 7?bit A)%s as in our

case. (e can design > bit A)%* ; bit and 79 bit alu and result is reflected by the flag register.

Sie of the flag register depends on the type of the data bus of the processor.

1uture work could be e4tended to optimiing unit capacitance 0alue. 'nowing the fabrication

run being used and error percentage in process would gi0e us feedback for designing with

smaller capacitors. Realiing logic designs with smaller capacitors will reduce the power

dissipation and make the layout more area efficient. 1urther work could also include e4tending

the current design to include more number of input bits for the A)%. In future !ual?A)%s are

used to e4ecute instructions concurrently for fine?grained parallelism.

R!9!R!#5!S

F7 FA0i 797 A. A0iiens* ,797/ Signed !igit umber Representation for 1ast parallel

Arithmetic*U I555 Trans on 5lectro. 6omp. Vol. 56?7<* ##. =;? ><<.

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5lectronic !esign* January 8<<9.



F= John 1aricelli* )ayout?!ependent #ro4imity 5ffectsin !eep anoscale

6-$SU*April*79*8<<.

httpHOOewh.ieee.orgOr@Oden0erOsscsO#resentationsO8<<W<>W1aricelli.pdf

F> James R. Sheets* +ruce (. Smith -icrolithography Science and Technology*U ew

&orkH -arcel !ekker* pp. =7:?=9@* 8<<<.

F@ (illiam Gerard "urley , Senior Member, IEEE, and 6hi 'wan )ee !e0elopment*

Implementation* and Assessment of a (eb?+ased #ower 5lectronics )aboratory in I555

TRASA6TI$S $ 5!%6ATI$* V$). >;* $. >* $V5-+5R 8<<@.

F9 +ehroo Vahidi , Senior Member, IEEE, and Jamal +eia %sing Spice in Teaching

Impulse Voltage Testing of #ower Transformers to Senior %ndergraduate StudentsU in

TRASA6TI$S $ 5!%6ATI$* V$). >;* $. 8* -A& 8<<@

F: A. Rantala* S. 1ranssila* '. 'aski* J. )ampinen* -. Aberg and #. 'ui0alainen Impro0ed

neuron -$S?transistor structures for integrated neural network circuitsU , IEE

Proceedings- Circuits, Devices and Systems, 0ol. 7>;* pp 8@?=>*1eb. 8<<7.

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F77 ). Shang* ). #eh* and . Jha. !ynamic 0oltage scaling with links for power optimiation

of interconnection networks. In #roceedings of International Symposium on "igh?

#erformance 6omputer Architecture* pages 7M7<8* 8<<=* I555

F78 A.-. Shams and -.A. +ayoumi* A no0el high?performance 6-$S 7?bit full?adder

cellU* IEEE "rans. on Circuits and Systems II& Ana!og and Digita! Signa! Processing *

0ol. >:* pp. >:; M>;7* -ay 8<<<.

http://ewh.ieee.org/r5/denver/sscs/Presentations/2009_04_Faricelli.pdf

http://ewh.ieee.org/r5/denver/sscs/Presentations/2009_04_Faricelli.pdf



F7= A. Sri0asta0a and !. Go0indara3an* A fast A)% design in 6-$S for low 0oltage

operationU , '. o( $%SI Design* 0ol. 7>* no. >* pp. =7@?=8:* 8<<8.

F7> 6. Srini0asan and A. Sri0asta0a A)% !esign using Reconfigurable 6-$S )ogicU* Proc.

o( t)e *+t) IEEE Midest Sym/osium on Circuits and Systems* 0ol.8* pp. 99=?999*

Aug. 8<<8.

F7@ &. Tsi0idis* /eration and Mode!ing o( ")e MS "ransistor * -c Graw?"ill* 7.

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Introduction* -c?Graw "ill* 79.

F7: -r. &u Nhou and "ui Guo ha0e been design in 8<<;* I555 Application specific )ow#ower A)% !esignU




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