JOSEPH S

JOSEPH S. SHOR, Ph.D

RESEARCH INTERESTS

· Sensor Interfaces for physical parameters, such as temperature, voltage, current, process, etc.

· Voltage Droop Detectors

· Ultra Low-Power and Low Voltage Analog Circuits

· Methodologies and building blocks for analog circuits in pure digital processes

· Area-scaling of analog circuits

· Power management Circuits, such as LDO's, Voltage Regulators, and DC-to-DC converters

· Security Circuits, such as Physical Uncloneable Functions (PUF)

· Energy-Efficient Circuits

· Novel Memory Circuits

· High Frequency Circuits

· Microsensors

SUMMARY

Joseph Shor received his Ph.D from Columbia University and was a researcher in the area of Device Physics for several years afterwards. After immigrating to Israel, he moved to the field of analog design and was a lead analog designer and manager in several High Tech companies. His last position was at Intel, where he was the Principal Analog Engineer for the Microprocessor Products Group. In 2015, he transitioned to academia where he established an analog design group at Bar Ilan University.

EDUCATION

Columbia University, School of Arts and Sciences, NY, NY:

Ph.D, M.Phil, and M.S in Electrical Engineering, 5/93 and 1/88

Queens College of CUNY, Queens, NY: B.A. in Physics

Ph.D Thesis Advisor: Prof. Richard M. Osgood.

Thesis Topic: Device Physics, Materials Characterization and Processing of Novel Semiconductor Materials for High Temperature Micro sensors.

· Characterized different types of SiC for application as micromechanical sensors which are capable of operating at high temperatures and in harsh environments.

· Characterized the piezoresistive properties of 3C-SiC and developed a sensor which operated up to 350oC.

· SiC is a largely inert material, so it is very difficult to process it, especially etching. Researched and Developed novel photoelectrochemical etching techniques for 3C-SiC.

· Researched etch-stop processes, which are critical to form micromechanical structures. The etching and etch-stop process which were developed were the first of this type for SiC.

· Developed and characterized metallization processes for SiC which could withstand temperatures as high as 650oC.

· The research work was published in top journals at the time, including: J. Applied Physics, J. Electrochem. Soc., Applied Physics Letters, IEEE Transactions on Electron Devices.

PROFESSIONAL HISTORY

2015-presentAssociate Professor, Bar Ilan University, Faculty of Engineering

2013-2015 Adjunct Associate Professor, Bar Ilan University

2003-2015 Intel Corporation, Yakum, Israel

2010-2015 Principal Engineer - Analog

2004-2010 Senior Analog Engineer

· Manager and Lead analog designer– Led a team of 4 analog engineers

· Developed many novel analog circuits used across Intel worldwide

· Developed among the first ever analog circuits in 22nm and 14nm FINFET technologies. These were published in ISSCC, JSSC and TCAS.

· Developed new miniaturized thermal sensors for measuring on-die hot spots. These sensors were used to characterize the hot spots in Intel’s Sandy Bridge Processor. This result was published in ISSCC and JSSC.

· Developed filtered power supplies for analog and digital PLL's.

· Developed analog circuits for power management and voltage regulation. This included an on-die LDO which drove an Intel Core and was published in ISSCC and JSSC.

· Developed techniques and methodologies for implementing analog circuits in pure digital processes. This included process-independent analog.

· Developed architecture and circuit techniques to scale analog circuits. This resulted in thermal sensors which were 10-15x smaller than the previous generation and a BGREF which was 3X smaller. This type of scaling is very unusual in analog.

Saifun Semiconductor, Netanya, Israel (now Cypress Semiconductor)

2003-2004 Staff Engineer(Senior Principal Engineer)

1999-2003 Principal Engineer

· Lead analog designer and manager.

· Developed analog circuits for the NROM memory- 2 physically separated bits/cell.

· Ramped up the analog field in Saifun nearly from scratch

· Developed power supply circuits, voltage regulators, on-die charge pump, sense amplifiers, filters, bandgap circuits, Class AB drivers, etc.

· Some of these circuits were published in ISSCC and ISCAS.

· Mentored many young engineers and trained them in analog design. This included teaching circuit/analog courses.

· Member of the Saifun Corporate Staff.

1994-1999 Motorola Semiconductor Israel, Herzlia, Israel

Principal and Senior Circuit Design Engineer

· Designed analog and digital circuits for DSP applications

· Circuits included amplifiers, gm/C filters, off-chip drivers, process independent analog circuits, etc.

· Designed high-speed digital IO buffers and memory circuits, which were published in CICC.

1988-1994 Kulite Semiconductor Products, Inc., Leonia, NJ

· Senior Research Scientist

· In this 2.5 year period following my Ph.D., research was conducted on several government- funded research programs which I initiated (see below). This included conceiving and writing research proposals, leading their implementation, and publishing the results in top journals such as Journal of Applied Physics, J. Electrochem. Soc., Applied Physics Letters, and IEEE Transactions on Elec. Dev.

· Led a team of 3 engineers and several technicians.

· Conducted several collaborations with Universities (see below) and government agencies.

· Research programs initiated:

· Semiconductor Pressure sensors for high temperature environments

· Novel Materials characterization including SiC, Semiconducting Diamond, Porous Si and SiC.

· Semiconductor processing

· Optoelectronic materials processing and characterization

· Silicon-on-insulator structures for microsensors.

· The research done in this program is still being cited today and several of the papers have over 100 citations.

· During this period I recruited research funding from Government programs and Industry for over $2M.

1/2-1993 Technion, Israel Institute of Technology, Haifa, Israel

Department of Materials Engineering

Visiting Scientist

1987-1992 Columbia University, New York, NY Microelectronics Sciences Laboratories

Graduate Research Assistant

1987-1988 IBM, T.J. Watson Research Center, Eastview, NY

Research Assistant

TEACHING

Ramped up 5 new courses in Analog Design from scratch.

· Undergrad Courses

· 8330301 – Linear Circuits – semester A

· Single stage amplifiers, input and output impedance, small signal models,

2-port models, differential amplifiers, current sources, 2-stage amplifiers

Compensation of single and two-stage OP-AMP.

· 8332501 – Analog Circuit Lab – semester B

· Simulation and Measurement of analog building blocks including, current mirrors, common source, source follower, differential stage, differential amp, differential-to-single-ended amp, 2 stage Miller amp in feedback configuration.

· Graduate Courses – (also outstanding Undergrad students)

· 8361101 – Intro to Analog Circuits – semester B

· This is a follow up course to the linear circuit lectures and lab. This introduces the students to more complex analog circuits and gives some experience in design and simulations as well. Topics include CMOS inverter based analog circuits, amplifier compensation, random and systematic offsets, offset compensation, comparators, Bandgap references, Noise. Feedback theory. It includes several design exercises as well as a design project.

· 8362101– Advanced Analog Circuit in Digital Processes – semester A

· This course includes the analog circuits which are found in almost every digital product including biasing circuits, Voltage controlled oscillators, Phase-Locked Loops – both analog and digital, Linear Voltage Regulators, and Thermal Sensors. The course includes design assignments as well as a personal project.

· 83608-01– Advanced Energy Efficient Analog– semester A

· This advanced course focuses on analog circuits which are optimized for energy efficiency. The circuits covered include switched-capacitor circuits – including Z-transforms, digital to analog converters (D/A), analog to digital converters (A/D), inductive switching regulators, switch-capacitor DC-to-DC converters, and crystal oscillators. There are 5 short design assignments and a personal project

RESEARCH STUDENTS

 

Grad Students

Degree

1

Ori Bass

Ph.D

2

Anatoli Mordakhay

Ph.D

3

Yizhak Shifman

Ph.D

4

Asaf Feldman

Ph.D

5

Natan Vinshtok Melnik

Ph.D

6

Avi Miller

MS

7

Liron Lisha

MS

8

Amir Mizrachi

MS

9

Yosef Lempel

MS

10

Ateret Wertzberg

MS

11

Or Adiv

MS

12

Aharon Rimer

MS

13

Edi Emanovic (co-advisor for Prof Drazen Jurisic from University of Zagreb)

Ph.D

14

Elisheva Berkowitz

MS

15

Daniel Dahan

MS

16

David Zaguri

MS

17

Orel Dahaman

MS

18

Gil Golan

MS

19

Omer Nechushtan

MS

20

Ido Shpernat

MS

GRADUATES

Ori Bass – Ph.D (Thesis Submitted) - 2020

Asaf Feldman – MS – 2019

Natan Vinshtok Melnich – MS – 2019

Yizhak Shifman – MS - 2018

SPECIAL RECOGNITIONS

.

· EE Times Article "Dispelling the myth about analog scaling", based on an ISSCC 2012 paper, Feb 2012.

· EE Times Article "Intel details Sandy Bridge at ISSCC", based on an ISSCC 2011 Paper, Feb, 2011.

· SBIR Program" 6H-SiC Pressure Sensors for High Temperature Applications" which I initiated was listed as an "SBIR Success Story"- 1996.

· NASA Certificate of Recognition for "Making SiC Semiconductor Devices Containing Porous Regions"- included in NASA Tech Briefs, 1996, based on SBIR Program I led.

· Trade Journal Note - "Porous SiC Expected to Yield Innovative Devices" in Technology Newsletter - "Electronic Design", Oct 24, 1996 based on SBIR Program Shor initiated.

· Trade Journal Note – "6H SiC Pressure Sensors aim for High Temperature Operation at up to 600C" in Technology Breakthrough Section, "Electronic Design", Jan 6, 1997, based on SBIR Program Shor initiated.

· EE Times Article "Single chip answers base-station needs" – highlight from ICSPAT '96, Oct 17, 1996, which Shor was a co-author.

· Recipient of Kulite Scholarship – 1990 –Columbia University and Kulite Semiconductor

· Paul Klapper Physics Prize – Queens College of CUNY, 1986

PAPERS

Google Citations - Updated as of September 10, 2020

All

Since 2014

Citations

2419

610

h-index

29

12

h10-index

44

18

 

Journal Papers

1.

Invited paper : J. Shor, "Compact Thermal Sensors for Dense CPU Thermal Monitoring and Regulation: A Review," accepted for publication in IEEE Sensors Journal, Special Issue on 20 Years IEEE Sensors Journal (Early Access 2020, IEEE).

2.

L. Lisha, O. Bass and J. Shor, "A 5800 μm2 Process Monitor Circuit for Measurement of in-die Variation of Vth in 65nm”, in IEEE Transactions on Circuits and Systems II: Express Briefs (Early Access, 2020).

3.

A. Feldman and J. Shor, "An Accurate 0.55V 2.6uW Voltage Level Detector", accepted for publication in IEEE Solid State Circuits Letters – ESSCIRC 2020 Special Issue (2020).

4.

O. Bass and J. Shor, "A Charge Balancing 1450 um2 PNP Based Thermal Sensor for Dense Thermal Monitoring," in IEEE Transactions on Circuits and Systems II: Express Briefs, Early Access (2020).

5.

Y. Shifman, A. Miller, O. Keren, Y. Weizman and J. Shor, "An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9 Key Error Probability," in IEEE Transactions on Circuits and Systems I: Regular Papers, Early Access (2020).

6.

N. Vinshtok-Melnik and J. Shor, "Ultra Miniature 1850 μm2 Ring Oscillator Based Temperature Sensor," in IEEE Access, vol. 8, pp. 91415-91423, 2020.

7.

O. Bass and J. Shor, "A Miniaturized 0.003 mm² PNP-Based Thermal Sensor for Dense CPU Thermal Monitoring," in IEEE Transactions on Circuits and Systems I: Regular Papers, Early Access (2020).

8.

Y. Shifman, A. Miller, Y. Weizman, O. Keren and J. Shor, "A Method to Improve Reliability in a 65nm SRAM PUF Array" - in IEEE Solid-State Circuits Letters, vol. 1, no. 6, pp. 138-141, June 2018.

9.

A. Mordakhay, and J. Shor  - "Miniaturized, 0.01 mm², Resistor-Based Thermal Sensor With an Energy Consumption of 0.9 nJ and a Conversion Time of 80 μs for Processor Applications", in IEEE Journal of Solid-State Circuits, vol. 53, no. 10, pp. 2958-2969, Oct. 2018.

10.

U Zangi, N Feldman, T. Hadas, N. Dayag, J. Shor , A. Fish, "0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)", Journal of Low Power Electronics and Applications 8 (2), 14, S3S Special Issue (2018)

11.

A. Mordakhay, Y. Telepinsky, L. Klein, J. Shor , A. Fish, "A Low Noise Low Offset Readout

Circuit for Magnetic-Random-Access-Memory," IEEE Transactions on Circuits and Systems I: Regular Papers, 65 (4), 1224-1233 (2018)

12.

KA Bowman, MM Khellah, T Kono, J. Shor , PI Mak, "Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference", IEEE Journal of Solid-State Circuits 53 (1), 3-7

13.

J. Shor and D. Zilberman, "An Accurate Bandgap-Based Power-On-Detector for Microprocessors in 14nm CMOS" , IEEE Transactions on Circuits and Systems II: Express Briefs vol. 63, no. 5, pp. 428-433 (2016)

14.

K. Luria, J. Shor, M. Zelikson, and A. Lyakhov, "Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On–Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm", IEEE Journal of Solid-State Circuits vol 51, no. 3, pp 752 - 762 (2016)

15.

T. Oshita, J. Shor, D. E. Duarte, A. Kornfeld, G. L. Geannopoulos, J. Douglas, and N. Kurd,  "A Compact First-Order ΣΔ modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process", IEEE Journal of Solid-State Circuits vol. 51, no. 2 pp. 378 - 390 (2016)

16.

Takao Oshita, J. Shor, David E Duarte, Avner Kornfeld, Dror Zilberman, "Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process", in IEEE Journal of Solid-State Circuits, vol 50,3, pp. 799-807 (2015)

17.

J. Shor and Kosta Luria, " Miniaturized BJT-Based Thermal Sensor for Microprocessors in 32-and 22-nm Technologies", in IEEE Journal of Solid State Circuits, Nov 2013, pp 2860-2867 (2013)

18.

Marcelo Yuffe, Moty Mehalel, Ernest Knoll, J. Shor, Tsvika Kurts, Eran Altshuler, Eyal Fayneh, Kosta Luria, and Michael Zelikson "A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor" - IEEE Journal of Solid State Circuits, JSSC Jan 2012 pp. 194-206 - ISSCC Special Issue invited (2012)

19.

J. Shor, A.D. Kurtz, I. Grimberg, B.Z. Weiss, and R.M. Osgood, "Dopant Selective Etch Stops in 6H and 3C SiC", Journal of Applied Physics 81,3 (1997).

20.

J. Shor, L. Bemis, A.D. Kurtz, I. Grimberg, B.Z. Weiss, M.F. Macmillan and W.J. Choyke, “Characterization of Nanocrystallites in Porous P-type 6H-SiC”, Journal of Applied Physics 76, 4045 (1994).

21.

J. L. Davidson, J. Shor, D. Wur and A.D. Kurtz,“Diamond Resistors Fabricated Monolithically on Diamond Film Substrate”, J. Electrochem. Soc. 141, 3522 (1994)

22.

J. Shor, L. Bemis and A.D. Kurtz, "Characterization of Monolithic n-type 6H-SiC Piezoresistive Sensing Elements", IEEE Trans. Electron Devices, 41 , 661 (1994).

23.

J. Shor, R. A. Weber, L. G. Provost, D. Goldstein and A. D. Kurtz, "High Temperature Ohmic Contact Metallizations for n-type 3C-SiC", Journal of the Electrochemical Society 141, 579 (1994)

24.

J. Shor and A. D. Kurtz, "Photoelectrochemical Etching of 6H-SiC”, Journal of the Electrochemical Society 141, 778 (1994).

25.

J. Shor, D. Goldstein and A.D. Kurtz, "Characterization of n-type beta-SiC as a Piezoresistor", IEEE Transactions on Electron Devices 40, 1093 (1993).

26.

J. Shor, I. Grimberg, B.Z. Weiss, and A.D. Kurtz, "Direct Observation of Porous SiC Formed by Anodization in HF", Applied Physics Letters 62, 2836 (1993).

 27.

J. Shor and R.M. Osgood Jr., "Broad Area Photoelectrochemical Etching of SiC", Journal of Electrochemical Society 140, L123 (1993).

28.

J. Shor, X.G. Zhang and R.M. Osgood, "Laser Assisted Photoelectrochemical Etching of n-type beta-SiC", Journal of the Electrochemical Society, 139, 1213 (May 22, 1992).

29.

 J. Shor, R.M. Osgood and A.D. Kurtz, "Photoelectrochemical Conductivity Selective Etch Stops in SiC", Applied Physics Letters 60, 1001 (1992).

 

1

Papers in Competitive Conferences (accept rate < 40%)

2

Y. Shifman*, A. Miller*, Y. Weizman, and J. Shor "An SRAM PUF with 2 Independent Bits/Cell in 65nm ," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5.

3

A. Miller*, Y. Shifman*, Y. Weizman, O. Keren and J. Shor, "A Highly Reliable SRAM PUF with a Capacitive Preselection Mechanism and pre-ECC BER of 7.4E-10" 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-4, doi: 10.1109/CICC.2019.8780246

4

O. Bass and J. Shor "Ultra-Miniature 0.003 mm2 PNP-Based Thermal Sensor for CPU Thermal Monitoring", Proceedings of the European Solid State Circuits Conference, ESSCIRC, 2018

5

N. Vinshtok-Melnik, R. Giterman, J. Shor, "Ultra miniature offset cancelled bandgap reference with ±0.534% inaccuracy from −10°C to 110°C," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4.

6

K. Luria, J. Shor, M. Zelikson, A. Lyakhov, "Dual-use low-drop-out regulator/power gate with linear and on-off conduction modes for microprocessor on-die supply voltages in 14nm", IEEE International Solid- State Circuits Conference, Digest of Technical Papers, ISSCC 2015

7

J. Shor, "Low Noise Linear Voltage Regulator for Use as an on-chip PLL Supply in Microprocessors", in IEEE International Symposium on Circuits and Systems, Paris France, May, 2010

8

K. Luria and J. Shor, "Miniaturized CMOS Thermal Sensor Array for Temperature Gradient Measurement in Microprocessors", IEEE International Symposium on Circuits and Systems, Paris France, May, 2010.

9

J. Shor, K. Luria and D. Zilberman, "Ratiometric BJT-based Thermal Sensor in 32nm and 22nm Technologies", International Solid State Circuits Conference- ISSCC , 2012 - Digest of Technical Papers, pp.210.

10

M. Yuffe, M. Mehalel, E. Knoll, J. Shor, Tsvika Kurts, "A Fully Integrated Multi-CPU, GPU and Memory Controller 32nm Processor", International Solid State Circuits Conference- ISSCC 2011 - Digest of Technical Papers

11

J. Shor, Y. Polansky, Y. Sofer, E. Maayan, "Self-regulated four-phased charge pump with boosted wells", ISCAS '03: Proceedings of the 2003 International Symposium on Circuits and System.

12

J. Shor, Y. Sofer, Y. Polansky, and E. Maayan, “ Low Power Voltage Regulator For EPROM Applications” ISCAS 2002: International Symposium on Circuits and Systems, May 26-29, 2002, Phoenix Arizona.

13

E. Maayan, R. Dvir, J. Shor, Y. Polansky, Y. Sofer, I. Bloom, D. Avni, B. Eitan, Z. Cohen, M. Meyassed, Y. Alpern, H. Palm, E. Stein, P. Halibach, D. Caspary, S. Reidel, and R. Knofler, “A 512Mb NROM Flash Data Storage Memory with 8MB/s Data rate”, in International Solid State Circuits Conference - ISSCC 2002 Digest of Technical Papers, Publisher: Univ. of Toronto, Toronto, Canada, Feb. 2002.

14

V. Koifman, Y. Afek and J. Shor; “Circuit Methods for the Integration of Low Voltage (1.1-1.8V) Analog Functions on System-on-a-Chip IC’s in a Single Poly CMOS Process” Proceedings of ISLPED 99: International Symposium on Low Power Electronics and Design, Aug 16-19, 1999.

15

J. Shor, V. Koifman and Y. Afek, "Novel Method to Compensate for Resistor Non-Linearities and its Application to the Integration of Analog Functions on System-on-a-Chip IC's" ISCAS 1999: IEEE Circuits and Systems Conference, May 30 – June 2, 1999.

 16

J. Shor, Y. Afek and E. Engel, "IO Buffer for High Performance, Low Power Applications", Proceeding of the 1997 Custom Integrated Circuits Conference- CICC (IEEE Press, 1997).

 

 

1

Papers Presented and Published in Refereed International Conferences

2

U. Zangi, N. Feldman, J. Shor and A. Fish, “0.45v and 18μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)”, Proceedings of the S3S Conference, Sept. 2017

3

O. Bass and J. Shor, "Ultra Miniature, 10 bit, First Order Sigma Delta Modulator with improved PSRR", presented at the 2016 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, Nov, 2016.

4

J. Shor and K. Luria, “Evolution of Thermal Sensors in Intel Processors from 90nm to 22nm”, 2012 IEEE 27-th Convention of Electrical andElectronics Engineers in Israel, Nov. 2012.

5

J. Shor, "Voltage Regulator Circuits for Low-Jitter PLL’s with High PSSR (>40dB) in a Purely Digital 65nm Process", in IEEE COMCAS, Tel Aviv, Israel, 2008

6

Y. Salant, O. Norman, U. Dayan, N. Sivan, B. Perlman, N. Benayahu,, Y. Tsayeg, E. Zmora, J. Shor, E. Salamon, “A Dual Core Engine for Embedded Applications” in The Proceedings of the Ninth International Conference on Signal Processing Applications and Technology, Sept 13-16, 1998.

7

E. Engel, M. Tarrab, Y. Amon, L. Belotserkovsky, E. Borowitz, D. Kuzmin, D. Moshe, E. Pisek and J. Shor, “ DSP56305 – Motorola New Optimized Single-Chip DSP for GSM Basestation Applications”;, in The Proceedings of the International Conference on Signal Processing Applications and Technology, 1996.

8

J. Shor, I. Grimberg, B.Z. Weiss, and A.D. Kurtz, "Photoelectrochemical Etching of 6H-SiC", Second International Symposium on Electrochemical Applications in Electronics, 183rd Electrochemical Society Conference, Honolulu, Hawaii, May 16-21, 1993.

9

J.L. Davidson, J. Shor, D. Wur and A.D. Kurtz, "Diamond Resistors Fabricated Monolithically on Diamond Film Substrates",Third International Symposium on Diamond Materials, 183rd Electrochemical Society Conference, Honolulu, Hawaii, May 16-21, 1993.

10

J. Shor, L. Bemis, A. D. Kurtz, M. F. Macmillan, W. J. Choyke, I. Grimberg and B. Z. Weiss, "Characterization of the Microstructural and Optical Properties of Porous SiC", Proceedings of the Fifth International Conference on SiC and Related Materials, Washington, DC, Nov. 1-3 1993.

11

L. Bemis, J. Shor and A. D. Kurtz, "Monolithic Piezoresistive Stress Sensing Elements in 6H-SiC", Proceedings of the Fifth International Conference on SiC and Related Materials, Washington, DC, Nov. 1-3 1993.

12

J. Shor, R. S. Okojie, and A. D. Kurtz, "Photoelectrochemical Etching and Etch-Stops in 6H-SiC", Proceedings of the Fifth International Conference on SiC and Related Materials, Washington, DC, Nov. 1-3 1993.

13

J. Shor, D. Goldstein, A.D. Kurtz and R.M. Osgood, Jr. , "SiC Device Development for High Temperature Sensor Applications", 1992 NASA High Temperature Measurement Conference Proceedings, NASA Langley, Hampton, Va, April 12-13 1992, published in conference proceedings.

14

J. Shor, R.A. Weber, L.G. Provost, D. Goldstein, A.D. Kurtz, "High Temperature Ohmic Contact Metallizations for n-type 3C-SiC Sensors" in Wide Band-Gap Semiconductors proceedings of the Fall, 1991 Materials Research Society Conference, Dec. 2-6, 1991, Boston, Mass. (Mat. Res. Soc. Press, Boston, Mass., 1992).

15

J. Shor, X.G. Zhang, R.M. Osgood, and A.D. Kurtz; "Photoelectrochemical Etching and Dopant Selective Etch Stops in SiC", in Amorphous and Crystalline SiC IV ed. by C. Y. Yang, M. M. Rahman and G. L. Harris (Springer-Verlag, Berlin Heidelberg, 1992) p. 356.

16

J. Shor, D. Goldstein and A.D. Kurtz, "Sensor Properties of n-type 3C-SiC", in Amorphous and Crystalline SiC III, Ed. by G. L. Harris, M. G. Spencer and C. Y. Yang (Springer Verlag, Berlin Heidelberg, 1992) p. 111.

17

J. Shor, X.G. Zhang, M.N. Ruberto and R.M. Osgood, "Surface Micromachining of beta-SiC Using Laser-Assisted Photoelectrochemical Etching", in Amorphous and Crystalline SiC III, Ed. by G. L. Harris, M. G. Spencer and C. Y. Yang (Springer Verlag, Berlin Heidelberg, 1992) p. 191.

18

J. Shor, D. Goldstein and A.D. Kurtz, "Evaluation of beta-SiC for Sensors", in Proceedings of the 1991 International Conference on Solid State Sensors and Actuators June 22-26, 1991, p. 912-915.

19

J. Shor, X.G. Zhang and R.M. Osgood, "Photoelectrochemical Etching of beta-SiC", Electrochemical Soc. Extended Abstracts 91-1, May 1991.

20

X.G. Zhang, J. Shor, M.N. Ruberto, M.T. Schmidt, and R.M. Osgood, "Laser Electrochemical Etching of SiC", in The 1990 Proceedings of the State of the Art Program on Compound Semiconductors, (Electrochemical Society Press, 1990).

21

J. Shor, D. Goldstein and A.D. Kurtz,"Characterization of the Gauge Factor of n-type beta-SiC", Electrochem. Soc. Extended Abstracts 90-1, May 1990.

 

D. Goldstein, J. Shor and A.D. Kurtz,"TCR of n-type and n+ beta-SiC", Electrochemical Soc. Extended Abstracts 90-1, May 1990.

 

 

1

DTTC (Design and Test Technology Conference) and ICTC (Intel Circuit Technology Conference) - (Refereed International Intel Conferences - acceptance rate < 25%)

2

K. Luria and J. Shor, "Frequency-based Digital Thermal Sensor", presented at DTTC 2010 (Design and Test Technology Conference)

3

J. Shor, "Analog DFT and DFM Circuits in Sandy Bridge", presented at DTTC 2010

4

J. Shor, "SFR Voltage Regulator for Low Noise PLL’s with High Power Supply Rejection Ratio", presented at DTTC 2007

5

K. Luria and J. Shor, "Miniaturized CMOS Thermal Sensor Array for Measuring Hot Spots in Microprocessors", presented at DTTC 2007

6

J. Shor, "Low Noise Voltage Regulator Circuits for Low-Jitter PLL’s", presented at ICTC 2008 (International Circuit Technology Conference)

7

J. Shor, "Learnings and advances of the SFR circuits for 1264 and 1266 processes", presented at ICTC 2006

8

J. Shor, "Flicker Noise Effects on Analog Circuits in Intel Microprocessors", published at DTTC 2007

 

J. Shor, "Voltage Regulator Architecture for Yonah PLL Power Supply", published at DTTC 2004

 

 

1

Invited Publications and Presentations:

2

J. Shor,  “Digital LDO or Analog LDO? You Decide!!” – Presented at the Worshop of Energy Efficient Electronics, Ystad, Sweden (WEEE, 2017)

3

J.S. Shor, "Application of Wide Bandgap Semiconductors in High Temperature Microsensors" presented at the National Academy of Sciences, Washington, DC, for the National Research Council, Committee on Materials for High Temperature Semiconductor Devices, Sept. 29, 1993 - results published in a report to determine funding policy.

4

Book Chapter: J.S. Shor- "Electrochemical Etching of SiC", in "Properties of SiC" ed. by G.L. Harris (IEE Press, EMIS Materials Science Series, 1995).

5

"Making SiC Semiconductor Devices Containing Porous Regions" , published in NASA Tech Briefs, Aug 1996, p. 88.

6

M.N. Ruberto, R. Scarmazzino, J.S. Shor and R.M. Osgood; "Microphotoelectrochemical Etching", Presented at the Electrochemical Microfabrication Symposium, Electrochemical Soc. Conference, Phoenix AZ, Oct. 13-18, 1991 and published in the conference proceedings.

7

J. Shor "Compact Thermal Sensors in Intel Processors from 90nm to 22nm", Columbia University Integrated Systems Labs, Special Seminar, Feb 2014.

8

J. Shor, "Micromachining Methods for and Characterization of 6H-SiC Piezoresistive Sensing Elements", given at Technion, IIT, Dept. of Mats. Eng., Jan 31, 1993.

ISSUED US Patents

 

US Patent #

Patent Title

Inventors

Award Date

1

10,630,493

Physical unclonable functions related to inverter trip points

J. Shor, R. Levi and Y. Weizman

21-Apr-20

2

10,156,859

Low dropout voltage regulator integrated with digital power gate driver

K. Luria, A. Lyakhov, J. Shor and M. Zelikson

18-Dec-18

3

10,061,336

Switch capacitor in bandgap voltage reference (BGREF)

Joseph Shor

28-Aug-18

4

9,996,143

Apparatus and method for selectively disabling one or more analog circuits of a processor during a low power state of the processor

Joseph Shor

12-Jun-18

5

9,921,592

Bandgap reference circuit with low output impedance stage and power-on detector

J. Shor, G. Geannopoulos, F. Paillet, L. Vu, and O. Dadashev

20-Mar-18

6

9,866,225

Digital phase-locked loop supply voltage control

N. Familia, A. Saksonov, E. Fayneh, J. Shor

9-Jan-18

7

9,639,133

Accurate power-on detector

Joseph Shor

2-May-17

8

9,350,365

Digital phase-locked loop supply voltage control

N. Familia, A. Saksonov, E. Fayneh, J. Shor

24-May-16

9

9,329,668

Apparatus and method for selectively disabling one or more analog circuits of a processor during a low power state of the processor

J. Shor

3-May-16

10

9,213,382

Linear voltage regulator based on-die grid

F. Paillet, J. Shor, G. L. Geannopoulos and H. Y. Tan

15-Dec-15

11

8,136,987

Ratio meter for temperature sensor

K. Luria and J. Shor

20-Mar-12

12

7,973,518

Low noise voltage regulator

J. Shor, A. Zaidel, N. Familia

5-Jul-11

13

7,728,688

Power supply circuit for a phase-locked loop

J. Shor

1-Jun-10

14

7,564,299

Voltage regulator

J. Shor and E. Fayneh

21-Jul-09

15

7,549,795

Analog thermal sensor array

K. Luria and J. Shor

23-Jun-09

16

7,400,186

Bidirectional body bias regulation

J. Tschanz,V. Zia, V. De , J. Shor

15-Jul-08

17

7,336,133

Buffered cascode current mirror

J. Shor

26-Feb-08

18

7,256,438

MOS capacitor with reduced parasitic capacitance

J. Shor, E. Maayan and Y. Betser

14-Aug-07

19

7,190,212

Power-up and BGREF circuitry

J. Shor, Y Betser and Y. Sofer

13-Mar-07

20

7,148,739

Charge pump element with body effect cancellation for early charge pump stages

J. Shor and E. Maayan

12-Dec-06

21

6,922,099

Class AB voltage regulator

J. Shor and Y. Betser

26-Jul-05

22

6,906,966

Fast discharge for program and verification

J. Shor and Y. Polansky

14-Jun-05

23

6,885,244

Operational amplifier with fast rise time

J. Shor

26-Apr-05

24

6,864,739

Charge pump stage with body effect minimization

J. Shor, E. Maayan and Y.Polansky

8-Mar-05

25

6,842,383

Method and circuit for operating a memory cell using a single charge pump

J. Shor, A. Harush and S. Eisen

11-Jan-05

26

6,791,396

Stack element circuit

J. Shor and E. Maayan

14-Sep-04

27

6,677,805

Charge pump stage with body effect minimization

J. Shor and E. Maayan

13-Jan-04

28

6,577,514

Charge pump with constant boosted output voltage

J. Shor, Y. Sofer and E. Maayan

10-Jun-03

29

6,448,750

Voltage regulator for non-volatile memory with large power supply rejection ration and minimal current drain

J. Shor, Y. Sofer and E. Maayan

10-Sep-02

30

6,166,578

Circuit arrangement to compensate non-linearities in a resistor, and method

J. Shor, V. Koifman and Y. Afek

26-Dec-00

31

6,034,001

Method for etching of silicon carbide semiconductor using selective etching of different conductivity types

J. Shor, A.D. Kurtz and D. Goldstein

7-Mar-00

32

5,963,076

Circuit with hot-electron protection and method

J. Shor, M. Yosefin and D. Bruck

5-Oct-99

33

5,952,875

Circuit with hot electron protection and method

M. Yosefin, Y. Afek and J. Shor

14-Sep-99

34

5,751,178

Apparatus and method for shifting signal levels

J. Shor, E. Engel and N. Baron

12-May-98

35

5,597,738

Method for forming isolated CMOS structures on SOI structures

A.D. Kurtz, J. Shor and A. Ned

28-Jan-97

36

5,569,932

Porous silicon carbide (SIC) semiconductor device

J. Shor and A.D. Kurtz

29-Oct-96

37

5,461,001

Method for making semiconductor structures having environmentally isolated elements

A.D. Kurtz, J. Shor and A. Ned

24-Oct-95

38

5,454,915

Method of fabricating porous silicon carbide (SiC)

J. Shor and A.D. Kurtz

3-Oct-95

39

5,386,142

Semiconductor structures having environmentally isolated elements and method for making the same

A.D. Kurtz, J. Shor and A. Ned

31-Jan-95

40

5,376,241

Fabricating porous silicon carbide

J. Shor and A.D. Kurtz

27-Dec-94

41

5,303,594

Pressure transducer utilizing diamond piezoresistive sensors and silicon carbide force collector

A.D.Kurtz and J. Shor

19-Apr-94

42

5,298,767

Porous silicon carbide (SiC) semiconductor device

J. Shor and A.D. Kurtz

29-Mar-94

43

5,165,283

High temperature transducers and methods of fabricating the same employing silicon carbide

A.D. Kurtz, D. Goldstein and J. Shor

24-Nov-92

PENDING PATENTS

1

J. Shor and N. Vinshtok-Melnik, “RING OSCILLATOR TEMPERATURE SENSOR”, US20190199329A1

2

J. Shor, Y. Weizman and Y. Shifman, "DETECTING UNRELIABLE BITS IN TRANSISTOR CIRCUITRY", US20190074984A1

3

Y. Shifman, A. Miller, J. Shor, "TWO BIT/CELL SRAM PUF WITH ENHANCED RELIABILITY", US Patent Application 16021371. (2018)

4

A. Mordakhay and J. Shor, "MINIATURIZED THERMISTOR BASED THERMAL SENSOR", US Patent Application 15981014. (2018)

5

O. Bass and J. Shor, "MINIATURIZED DIGITAL TEMPERATURE SENSOR", US Patent Application 15959239. (2018)

6

L. Lisha and J. Shor, “PROCESS MONITOR CIRCUITRY WITH MEASUREMENT CAPABILITY” US Patent Application 16/550,236. (2019)

Grants Awarded as a Bar Ilan Faculty Member

Grant Title

Agency

Award Date

# of years

Budget (NIS)

Multi-Mode Circuit for Image Sensor Readout (PI: Joseph Shor. Co-PI: Alex Fish)

Huawei/Toga

Sep-19

2

$390k

Cryogenic EDRAM and Support Circuitry for Smart IR Imaging Applications (PI: Joseph Shor; Co –PI’s: Adam Teman and Alex Fish)

Smart IR Consortium

Aug 2019

1.5 extendable to 3

1.285 Million NIS

High Frequency next Gen VCO

Huawei/Toga

Jan-19

2

$400k

Process Monitors for Near Vth Power Management

GenPro Consortium

Sep-18

3

770k

Intel Donation

Intel

June and Sept-18

$58k

Ultra-Low Power, Configurable, nano-Watt level Bandgap Voltage and Current References for IOT

Israel Science Foundation (ISF)

Jul-18

4

260k x 4 (NIS)

Individual Faculty Equipment Grant

ISF

Jul-18

3

760k (NIS)

Advanced Droop Detection and Correction Method for Improved Energy Efficiency and Performance in Integrated Circuits (Alex Fish – Co-PI)

Ministry of Science

Oct-17

3

200k x 3 (NIS)

Highly Reliable SRAM PUFs for Secure Key Generation and Authentication

Kamin

Jul-17

2

840k (NIS)

Thermal Sensors and Process Monitors

Hiper Consortium

Jul-15

4

320k x 4 (NIS)

Grants Awarded Prior to Joining Bar Ilan: These research grants were conceived and written by Dr. Shor in a 2.5 year period immediately following his Ph.D.

Small Business Innovation Research - SBIR Program (USA)

Agency

Year

Award

Silicon Carbide Micro sensor with Piezoresistive Diamond Sensing Elements - Phase 1

DOD

1993

$ 49,660

Silicon Carbide Micro sensor with Piezoresistive Diamond Sensing Elements - Phase 2

DOD

1994

$ 500,000

Silicon-Carbide Ultraviolet and Near Ultraviolet Optoelectronics - Phase 1

NASA

1993

$ 50,000

Silicon-Carbide Ultraviolet and Near Ultraviolet Optoelectronics - Phase 2

NASA

1994

$ 499,973

6H-SiC Pressure Sensors for High Temp Applications - Phase 1

NASA

1992

$ 49,929

6H-SiC Pressure Sensors for High Temp Applications - Phase 2

NASA

1993

$ 499,183

INTERNATIONAL AND NATIONAL COLLABORATIONS

[1] Collaborated with many Intel groups in Portland and Folsom on the development of analog circuits for microprocessors. 2004-present.

[2] NASA Lewis Research Center (now NASA Glenn) – Collaborated on the use of SiC for sensor and optoelectronic applications. This led to funding from them as well (see above). 1989-1994.

[3] Technion IIT, Dept. of Mats. Eng. – Collaborated with Prof. B.Z. Weiss (now deceased) – TEM characterization of the microstructure of Monocrystalline and Porous SiC. 1989-1994.

[4] University of Pittsburg, Physics Dept. – Collaborated with Prof W.J. Choyke on the Luminescence properties of Porous SiC. 1992-1994.

[5] Vanderbilt University, Dept. of Elec. Eng. – Collaborated with Prof. J. L. Davidson on the use of semiconducting diamond for sensors. 1992-94.

AFFILIATIONS AND INTERNATIONAL ACTIVITIES

· Member ESSCIRC Technical Program Committee (TPC) - Power Management Subcom -since 2018

· Guest Associate Editor – Solid State Circuits Letters – ESSCIRC 2019 Special Issue.

· Session Chair - "LDO Techniques", ESSCIRC 2018

· Member ISSCC International Technical Program Committee (ITPC) – International Solid State Circuits Conference, 2014-2018

· Guest Associate Editor - Journal of Solid State Circuits - JSSC - ISSCC 2017 Special Issue

· Session Co-Chair - ISSCC 2016 - Sensors and Displays

· Member of ISSCC 2014-2018 IMMD Subcommittee

· Member of ISSCC 2014-2018 European Regional Committee

· Member of ISSCC 2015 Demo Committee

· (ISSCC is the world's foremost Circuit/Analog International Conference)

· Senior Member IEEE

· Associate Editor - IEEE Sensors 

· IEEE Solid State Circuits Letters – Editorial Review Board

· Member IEEE Solid State Circuits Society

· Member of American Institute of Physics

· Member – American Physical Society

· Reviewer for IEEE Journal of Solid State Circuits

· Reviewer for IEEE Transactions on Circuits and Systems 1 and 2

· Reviewer for IEEE Transactions of VLSI Systems

· Reviewer for IEEE VLSI Circuits Symposium

· Reviewer for Applied Physics Letters

· Reviewer for Materials Research Society

· Reviewer for ISCAS (International Conference of Circuits and Systems)

· Reviewer for Sensors Journal

· Reviewer for IEEE Access

· Reviewer for Microelectronics Journal

· Guest Editor in the 2014 Sensors Special Issue of the Journal of Low Power Electronics and Applications.

· IEEE FTFC 2014– Member of the Technical Program Committee.

· Member of Intel's International Circuit IP Patent Committee 2004-2015.

· Reviewer for the Intel International Design and Test Technology Conference 2013-2015

· Member of US Karate Team to Maccabia Games, 1985, 1981

· Member of Israel Traditional Karate Team, 2011, 2009.

· Certified Sports Coach and Instructor according to the Israel Sports Law

Academic Profile:

Prof. Shor is has been an academic and industrial researcher active in the field of analog design and sensors. He is a sensor expert both on the technological side, as well as the analog interface circuitry. He has designed and published some of the first analog circuits in the FINFET process, 22nm, 16nm. and 14nm. There are major technological challenges here, including designing circuits in processes which are optimized for digital, not analog. The transistor Rout is very low in these processes, so novel techniques needed to be developed in order to enable high performance circuits. The circuits also need to be very robust, since they have been mass-produced in the hundreds of millions. This research, which started in Intel, continued in Bar Ilan, and circuits developed by Prof. Shor’s group have been published in some of the top conferences and Journals and held benchmarks for small size and performance.

Prof. Shor has served in technical program committees of ISSCC (International Solid State Circuit Conference) from 2014-2018 and ESSCIRC (European Solid State Circuits Conference) from 2018-present. ISSCC is the #1 forum for analog and circuit design, while ESSCIRC is also among the top conferences. He was a guest associate editor for JSSC (Journal of Solid-State Circuits) and SSCL (Solid State Circuits Letters), which are the two top journals in the field.

He has been on many international Intel committees, including the International Circuit IP Patent committee, Design and Test Technology Conference committee, Intel Technology Readiness Committee for the 10nm process, and the Thermal Sensors Expert Review Committee.

Prof. Shor ramped up the field of analog design, basically from scratch, in two industrial sites – Intel Yakum and Saifun Semiconductor (now Cypress Israel). This included training junior engineers in the field by giving courses, mentoring and role modeling.

The research field of Analog Design in Bar Ilan was established by Prof. Shor in mid-2015 when he joined the faculty. Since then, many of the students have joined Shor’s group to pursue advanced degrees in the field. The graduates of this program have been highly sought after by industry and have been accepted to the top industrial analog groups in the country. There are currently 14 graduate students and 11 undergrad students pursuing the field of analog design in Shor’s group.

In the Technology area, Dr Shor was the principal or lead investigator of seven SBIR (Small Business Innovation Research) in the areas of sensor technology. He initiated these research programs, wrote the research proposals, and conducted the research in these areas. Two of these programs received awards and were published in NASA Tech Briefs. One of them was listed by NASA as an "SBIR Success Story".

Some of the specific design and technological advances which Dr. Shor achieved are listed below:

Analog Circuits:

Thermal Sensors: The thermal sensors developed, patented and published by Dr. Shor at Intel and Bar Ilan have been benchmarked as the state-of-the-art smallest sensors reported in the literature. They have been published in top forums, such as ISSCC, JSSC, ISCAS, and ESSCIRC. The sensor papers are cited quite often in the literature. Some of these small sensors were used to characterize the hot-spots and thermal gradients in the Intel Sandy-Bridge microprocessor. This work was published in ISSCC and JSSC.

Hardware Security Circuits (PUF): Shor has developed several novel physical unclonable function (PUF) circuits. A PUF is an entropy generator for identification and authentication used in secure communication. The circuits have benchmarks as the lowest bit-error-rate and lowest energy of PUF circuits in this category and have been published in top forums.

Power Management Circuits: Dr. Shor has worked extensively on analog circuits for power management, such as voltage regulators and LDO's. These VR’s have been used as filter supplies for PLL’s in Intel products, while the LDO’s were used to drive an Intel core. These circuits have been published in top forums, such as ISSCC, JSSC and ISCAS.

Voltage Supplies for NROM Memory: While at Saifun Semiconductor, Dr. Shor developed hig efficiency power supplies, voltage regulators and sense amplifiers for the NROM charge-trapping memory. The analog technology he researched and developed was critical in enabling the NROM technology to be accepted in the marketplace. The analog circuits he developed resulted in 12 patents for Saifun as well as several papers in top forums, such as ISSCC.

New Opportunities: There are many new projects in Prof. Shor’s group covering different areas of analog and digital circuit design. This includes high frequency VCO’s, Voltage Droop Detectors, Image Sensors, Cryogenic CMOS for Infrared Images, Dual Mode Logic, Ultra Low-Power nW Level analog circuits, Voltage Level Detectors, Power Management for near-Vth operation, and Process Monitors.

Microsensors:

While in the US, Dr. Shor researched novel microsensors including the following areas:

Novel Sensor Materials: Dr. Shor characterize the piezoresistive properties of semiconducting SiC and diamond and developed high temperature pressure sensors using these materials. The piezoresistance of two polytypes of SiC, 3C-SiC and 6H-SiC, were reported. He was one of the first to publish in this field and this work has been very well referenced until today.

Porous SiC

Dr. Shor the first papers and patents about the process to develop Porous SiC, a material with very interesting mechanical optical properties. It had the potential to be used as a UV light source or as a chemical sensor because of it nanometer sized pores. A novel electrochemical etching process was developed which resulted in micropore formation in SiC. SiC is a relatively inert material, so this process was very unusual. Collaborations were established with the University of Pittsburg and Technion to perform photoluminescence and TEM studies of the material to understand its interesting properties. This resulted a series of publications and a research project was established with funding from NASA. The project was given a NASA award and reported in NASA Tech Briefs and other trade publications as well. There are several hundreds of citations of this work and it is a topic of study till today.

Processing of Novel Semiconductors : In order to develop high temperature microsensors, Dr. Shor researched new processes for the relevant materials. This work has resulted in many papers and citations to this day. As SiC is a very inert material, it was difficult to process. Dr. Shor developed novel electrochemical etching and etch-stop processes for SiC. These works were published in Applied Physics Letters, Journal of Applied Physics and Journal of the Electrochemical Society. In addition, metallization processes were developed for SiC and diamond. These processes were used to develop SiC and diamond pressure sensors, which are robust in high temperature environments. The development of Porous SiC and the SiC Microsensor were featured in several trade publications, including NASA Tech Briefs, resulting in a award for Dr. Shor. In addition, the SiC Sensor was listed as an SBIR Success Story.

Tapeouts at Bar Ilan:

Since arriving at Bar Ilan, Prof. Shor has trained students and developed infrastructure to enable Silicon Tapeouts which include analog and digital circuits. Typically, the training a student requires from the time he/she enters analog till a successful tapeout takes 3 years. Below is a list of the tapeouts which have been and are being implemented.

a) Pathfinder (May, 2017 – 65nm TSMC) – This was the first BIU analog tapeout. It included thermal sensors, as well as PUF circuits. The circuits exhibited excellent functionality and have generated publications in JSSC, TCAS1, TCAS2, SSCL, and ESSCIRC.

b) Pathfinder2 (May 2018 – 65nm TSMC) – This follow-up tapeout included several new PUF circuits, all of which functioned well in Silicon. Papers were published in TCAS1, CICC 2019, ISCAS 2019 and counting

c) Genesis (May 2019 – 65nm TSMC) – This tapeout included PUFs, a Process Monitor and an ultra-low power bandgap reference. The circuits are fully functional, and papers are being written.

d) SOC2 (June 2019 – 16nm TSMC) – Shor’s group participated in this tapeout of the Hiper Consortium and the contribution include an ultra-small, ultra-fast thermal sensor for thermal monitoring of the SOC. Initial debug indicates that the sensor is functional. Full characterization is in progress.

e) Genesis2 (Aug 2019 – 65nm TSMC) – Circuits included a Ring-Oscillator based sensor, a mobility monitor and a Low Voltage Power-On-Reset Circuit. All circuits are functioning well and papers are being prepared. So far, papers were accepted or published in SSCL and IEEE Access.

f) Snir (Feb 2020, 65nm TSMC) – This chip contains an LDO, a Process Monitor, a Noise modeling circuit, two different Droop detector circuits, a Dual Mode Logic block, and a Switch-capacitor DC-DC converter.