Joint optimization of layout and litho for SRAM and logic towards … · 2013-03-15 ·...

Joint-Optimization of Layout and Litho for SRAM and Logic towards the 20 nm node, using 193i

Peter De Bisschopa, Bart Laenensa, Kazuya Iwaseb, Teruyoshi Yaoc, Mircea Dusad, Michael C. Smaylinge

aimec, Kapeldreef 75, Leuven, Belgium B-3001 bSony, Kapeldreef 75, Leuven, Belgium B-3001

cFujitsu Semiconductor Europe, Kapeldreef 75, Leuven, Belgium B-3001 dASML, De Run 1110, 5503 LA Veldhoven, The Netherlands

eTela Innovations, Inc., 485 Alberto Way, Suite 115, Los Gatos, CA, USA 95032

ABSTRACT This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes, it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the layout-style – litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial wafer results).

Keywords: DFM, gridded design, restricted design rules, Local Interconnect, Layout-Source-Mask Optimization, SMO

1. INTRODUCTION Technology- or area-scaling in semiconductor manufacturing has traditionally been driven by a steady increase of the NA and/or a decrease of the exposure wavelength λ of the lithographic exposure tools. In optical lithography this evolution has now come to a halt, which implies that other means need to be used to manufacture more aggressive nodes at a constant NA-λ. Pattern splitting is one of the answers that has emerged to meet this challenge, but also the concept that the layouts itself need to be included into the flow of finding a manufacturable solution for a given node (referred to as ‘design for manufacturability’[1], ‘restricted design’, etc) has been put forward already many years ago. Although most lithographers would agree that layout restrictions must become inevitable at some point, and many papers have been devoted to this subject[2-13], it is perhaps less clear at which node such restrictions actually would have to be applied, what these restrictions should look like, how much lithographic-performance improvement can be gained from them, and also at what ‘price’ they would come. This paper tries to provide at least a partial answer to these questions. As one could expect that the performance benefit must depend on the exact application that is being considered, including its particular implementation (e.g. design rules) and target performance, all of which would be different for every manufacturer, we conceived this paper as a case study, in which we apply these questions on a practical case (‘test chip’), consisting of an SRAM cell and a small block of four Standard Logic cells (a flip-flop, full-adder, inverter and nand). We generated different layout versions of this test chip (always using the same ‘net-list’, i.e. the electrical diagram of the cells as well as the individual transistor characteristics, as given by their so-called length and width, remain identical), such that we can assess the merits and drawbacks of each layout style from a comparison of the predicted lithographic performance we obtain from them. Comparisons like this have been made before, but our study differs perhaps from earlier work in the following way: • By repeating this comparison for gradually decreasing chip area in the 28-20 nm node range, we obtain a more

systematic understanding of the differences between the layout styles • We have used the most advances computational lithography technology that is available today, in particular SMO[14-

17] (including model-based assist placement), to optimize each individual case, so that the lithography-performance differences are not affected by e.g. the choice of a common illumination mode, which might unwillingly favor one

Optical Microlithography XXIV, edited by Mircea V. Dusa, Proc. of SPIE Vol. 7973, 79730B · © 2011 SPIE · CCC code: 0277-786X/11/$18 · doi: 10.1117/12.881688

Proc. of SPIE Vol. 7973 79730B-1

style or the other. The SMO optimization provides also a prediction of the litho performance of the test chip, which includes variability with scanner focus- and dose-errors as well as mask errors. A limitation of our approach is that we have done these simulations using image-in-resist calculations (i.e. constant-threshold model), such that we do not take full account of real resist effects. Although this obviously impacts the absolute-value accuracies we report here, we trust that the trends that we obtain, e.g. in comparing different layout styles or other options, retain enough validity.

• We include also technology options that are perhaps not yet commonly used today, but have shown potential to facilitate manufacturability of advanced nodes. Among these are o The presence or absence of a so-called Local-Interconnect (LI) layer[17-22] to connect front- and back-end in the

test chip. Such a layer would typically reduce the density of e.g. contact and metal1, and reduces some of the ‘strain’ on these typically difficult layers. It also has a significant effect on the Active layer (see section 3.6)

o The use of negative-tone developer[15,22-24], (as opposed to the more traditional positive-tone developer), known for its potential to improve process latitudes of e.g. contact-type layers in particular, but in fact for all layers that are traditionally done with dark-field masks.

o We of course allow pattern splitting, as opposed to single patterning. Our study then gives an indication where along the node axis single patterning has to give way to double-patterning and triple patterning.

Our study will in fact demonstrate that all these ‘new technologies’ will serve as important enablers for aggressive technology nodes.

We will now describe the conditions, assumptions and cases included in our simulation study in more detail.

2. CASES INCLUDED AND METHODOLOGY USED 2.1. Three Layout Styles

The key of this paper is to see whether and how increased layout restrictions can improve patterning margins for increasingly advanced nodes, looking at a typical SRAM+Logic application. We defined three ‘layout styles’ for this study, of course acknowledging that these are not the only possibilities, and that within a given style the particular choice of a multitude of layout parameters and design-rule values will further impact the patterning performance. Figure 1 illustrates the difference between these styles. All three are to some extent restricted already. In all cases, all transistor gates have the same orientation (‘vertical’) and are at a single, fixed pitch (which implies that at some positions in the logic cells dummy poly lines will be inserted to ‘maintain’ this pitch). In the logic cells, a ground (gnd) and power (Vdd) rail is running at the top- and bottom-edge of the cell. The height of the logic cell is equal to 10 times the minimum metal1 pitch (‘10 track’ cells); the height of the SRAM cell is 6x the minimum metal1 pitch. The main differences between the three layout styles are: • Style A, ‘noLI_2D’: does not use a local-interconnect layer, and 2D patterns are allowed in Poly and Metal1 (by

which we mean that poly and metal1 have wires running both in the vertical and the horizontal direction), but both are tied to a grid with a pitch PX and PY for vertical and horizontal oriented wires respectively.

• Style B, ‘noLI_1D’: does not use a local-interconnect layer, but the Poly and Metal1 wires are only allowed in a vertical and horizontal orientation respectively (which we call ‘1D’ type styles, even though there are still gaps interrupting the poly- and metal-lines. So we use ‘1D’ really as a synonym for ‘uni-directional’.)

• Style C: ‘LI_1D’: uses a local interconnect layer (connects active to active or – through contact – to gnd or Vdd); both Poly and Metal1 are 1D.

In the two ‘1D’ styles we impose one fixed gap-size in Poly and Metal1, such that these two layers can be realized with the cut-mask technique (which, in the case of Metal1, would be more correctly referred to as a ‘fill mask’, but we shall continue to call it a ‘cut-mask’). Note that we accept that some of the internal logic-cell wiring also occurs in Metal2, but only when there is no other way. (Our test chip does in fact not contain any cell-to-cell connections.)

2.2. SRAM layouts

We have used two SRAM cell layouts, one without and the other with a LI layer (see Figure 2), to be combined in the optimization/evaluation with style A or B and C respectively. These SRAM cells follow the typical planar 6T layout for Active and Poly; the other layers have been optimized during the course of this study.


Active (green);

LI (grey) Poly Contact Metal1 Via & Metal2 (used

to complete internal cell connections)

Style A: noLI_2D

Style B: noLI_1D

Style C: LI_1D

Figure 1: Illustration of the main differences between the layout styles used in this study (only a small part of the logic

clip is shown)

SRAM layout

without use of LI

SRAM with use of LI

Active (green), Poly(red) & LI (blue) & Contact Metal1 & Via & Metal2 & Via2 Via2 & Metal3

Figure 2: SRAM layers (shown is half of the unit cell, which is equal to 4 bit-cells. The complete unit cell is obtained by mirroring the half cell down, along the bottom edge in the drawings)

2.3. Pitch combinations (‘nodes’) and general design parameters

As there does not seem to be a universally accepted definition of technology nodes any more, we need to define what the 28 to 20 nm node range we referred to earlier means in this paper. For lithography, pitches are the key parameters, and Table 1 identifies eight Poly-Metal1 pitch combinations that we identify (for the sake of the current study) with the 28-20 nm node range. Also included in the table are the resulting SRAM bit-cell area, and the values used for some basic design parameters. The more important parameters for this study are of course the litho targets (as we are doing a litho-performance optimization), but for poly we also indicate the assumed after-etch values. To be noted is that two design parameters are not changing with the node: the area of the after-litho contact and the metal1 gap size (for style B and C). The reasons for this are as follows. • With the fixed values of NA and λ, there is a certain minimum contact size (or area) that can be printed with

reasonable process latitudes. When moving to a more aggressive node, this after-litho size can therefore not be reduced very much, and the necessary decrease in the after-etch size (which is imposed by the contact size design rule) must be realized by a process- or etch-bias[25]. We also imposed the requirement that no ‘contact triangles’ should exist in the logic-cell layouts, i.e. a group of contacts consisting of one contact-pair at 1× the poly-pitch in the horizontal direction, separated (at equal distance) from the 3rd contact by 1× the metal1 pitch in the vertical


direction. Goal was to avoid the need for double- and (especially) triple-patterning as long as possible. Note however that densely spaced contacts cannot be avoided in the SRAM cells, and – as we shall see further on – this imposes multiple patterning in the Contact layer anyway.

• The fixed Metal1 gap-size (of 60 nm) – only applied to style B and C - is a choice that we made from the general observation that small gaps usually lead to high MEF values. We therefore decided not to shrink the gap-size when scaling the pitches, but to make sure that the cell layout (of both SRAM and logic) is such that such a large gap can be maintained without leading to e.g. unreasonably small metal1-contact extensions. This particular ‘layout restriction’ came with an area penalty of ~2% on our logic block but no SRAM-area penalty. Also here the purpose of avoiding small Metal1 gaps was to avoid the necessity of double patterning because of the gaps being too small.

These two design constraints imposed some internal-cell wiring connections at Metal2, in the logic cells.

Node Label SRAM bit-cell area

Pitches [nm] Poly line width [nm]

Poly gap [nm]

Litho Contact size after litho [nm]

Min Metal1 gap [nm]

[μm2] PX (Poly)

PY (Metal1)

Design target

Litho target in SRAM Size_Y Size_Y Style

A Style B&C

28 P110P90 0.12 110 90 28 44 51 48 52 45 60 25 P100P80 0.096 100 80 25 37 45 47 49 40 60 25 P90P90 0.097 90 90 25 37 51 43 54 45 60 24 P90P80 0.086 90 80 24 35 45 45 52 40 60 22 P80P80 0.077 80 80 22 32 45 42 54 40 60 22 P90P70 0.076 90 70 22 32 40 47 50 35 60 21 P80P70 0.067 80 70 21 29 40 44 52 35 60 20 P82P64 0.063 82 64 20 27 36 46 50 32 60

Table 1: Definition of the basic design parameters for the eight pitch combinations (or ‘nodes’) used in this study

Figure 3: Representation of the goal of this study: explore SRAM/Logic litho solutions in the three-dimensional space: Layout style – Node – Litho Options. An example of the ‘test chip’ used in this study is also shown (style-A version):

SRAM-unit cell (left side) and 4-cell logic block (right side).

2.4. The test chip

The test chip used in this study consisted of two ‘isolated’ clips (see Figure 3), one being the SRAM unit cell, the other being a single row of our four logic cells (flip-flop, full-adder, inverter and nand), each cell being separated from its neighbors by a ‘tap’ cell, i.e. a small cell (a single poly-pitch wide) that makes the bulk contacts. Of course, in a real chip the variety of logic cells and placement configurations would be much larger, but we believe that this small test chip contains enough variety and includes most of the to-be-expected litho difficulties to ensure that the observations of our study are meaningful. We generated these test clips for the 3 layout styles and 8 Poly-Metal1 pitch combinations. It is already interesting to compare the relative sizes of the logic-block clips and count the number of contacts and metal1-wires for each of the 3


styles, as well as looking at the minimum Via and Metal2 pitches. This information is given in Table 2. Contrary to what is sometimes thought, the 1D styles do not lead to a larger cell area. Also, it is clear that style B has the highest contact- and metal1-density, and also has the tightest Via and Metal2 pitches. So one can expect these layers to be more difficult than in the other styles.

Style Width logic

test clip

Minimum Pitch Number of Contacts

Number of Metal1 wires (not

incl. dummies) Contact Via Metal2

A: noLI_2D 55 PX ),)2/(min( 22XYX PPP + 22

YX PP + PY 149 25

B: noLI_1D 52 PX PY PY PX 142 75 C: LI_1D 52 PX 22)2/( YX PP + 2 PY 3 PX 119 49

Table 2: General properties of the implementation of the three layout styles in our particular Logic test clip. The actual values would in fact be different if other cells had been chosen, but this info still gives an interesting view on general density and area differences.

2.5. Litho optimization and performance evaluation We adopted the following approach: Litho optimization 1. Choose a clip for doing the optimization.

Our test chip is sufficiently small to allow us to do the SMO optimization on the entire chip in all cases, but we decided not to do that for two reasons. With a large test chip, this would not be practical (due to the large calculation time reuired), and one would have to adopt some approach for selecting a subset of cells for optimization anyway. Usually the SRAM is the more critical part of the chip. Therefore in general we tried the following approach. We did the SMO optimization on the SRAM only and then apply this ‘solution’ (i.e. the optimum source and image threshold) to the logic clip. Only if this did not give satisfactory results, we changed our approach.

2. Run the SMO step The software we used is the Tachyon SMOTM software from Brion. Since we did not have a calibrated resist model when our study started, we did all calculations using the simple ‘threshold on resist-image’ approach (under the Kirchhoff mask assumption). This evidently is a limitation of our approach, which tells us that we cannot take the absolute values of the performance metrics literally. But we believe we can still compare results, e.g. between layout styles or when scaling to tighter pitch combinations. Note that the output of the SMO step is an optimized source and resist-image threshold, and that the SMO process does automatic assist-placement and OPC. The optimization itself tries to minimize the edge-placement error of the clip that is used in the optimization, considering not only the nominal focus-, dose- and mask-conditions, but including a number of off-nominal conditions. The off-nominal con-ditions we typically used in our study are given in Table 3. We always fixed the NA at 1.35 and use xy-polarization

Litho performance calculation 3. Evaluate the litho performance on the complete SRAM+Logic clip.

This step is only required when the SMO optimization was not done on the full chip. We then run what is called an MO calculation (MO = ‘mask only’): the optimized source and threshold are used to do assist-placement and OPC on the full chip, from which litho-performance metrics can again be deduced.

4. Litho metrics used The Brion software allows user-defined ‘cut-lines’ on the design, i.e. positions where CD, DOF, EL and MEF can be calculated, one set of values for every cut-line. Our basic performance metrics are: • The worst individual MEF value, i.e. the max. value of the MEFs, calculated for each of the cut-lines defined • The worst individual DOF@6%EL value, i.e. the minimum value of all the individual DOFs we obtain. So note

that we do not consider overlapping DOF (essentially to avoid low-DOF performance only because of an occasionally imperfect OPC)

To these two basic metrics, we sometimes added others. In the case of active and poly, for example, an additional metric we used is the CD-variation over the transistor area, as this variability will impact the electrical performance of the cells[26,27]. In calculating this CD variability one can combine focus- dose and mask-errors (instead of considering individual offsets only), and also include overlay errors. Also interesting is to look for bridging- or pinching-hot spots, information which is easy to extract with Brion’s LMC software.


5. Target performance values. In deciding whether the performance obtained is good or not, we adopted the following target performance values:

• Max MEF ≤ ~4 • Min DOF@6%EL ≥ ~100 nm

On which we allowed some exceptions, which we will detail further on. In doing the DOF calculation, also a CD tolerance needs to be defined. In most cases we deviated from the traditional ±10% CD tolerance. Table 4 gives additional details on this.

Conditions for SMO Conditions for CD-variability

calculation: CD-tolerance definition

ΔF [nm] ΔE [%] ΔCDMaskEdge [nm] Layer CD tolerance

Focus offset, ΔF [nm] ±50 0 0 0, ±1 Active ±10% Dose offset, ΔE [%] ±3 ±50 0 0, ±1 Poly linewidth ±10% of design

target Mask error per edge, ±1 0 ±3 0, ±1 Contact ±4.6 nm ΔCDMaskEdge [nm] ±35 ±2.1 0, ±1 Metal1 line width ±10%

Table 4: FE- and Mask settings during optimization and evaluation. CD tolerances per layer

Metal1 gap ±10% (style A) ± 10 nm (B&C)

Metal1 cut-mask width ±10 nm

3. LITHO PERFORMANCE RESULTS This section summarizes our main results, being the litho-performance values we obtained for the different layout-style and pitch combination (‘node’) cases. Although we will of course consider the absolute values of the various litho metrics used (e.g. the DOF and MEF target values set forward in section 2.5), the main emphasis will more often be on the comparison between styles or trends through the pitch ranges. We will use the values themselves primarily to estimate where single patterning has to be replaced by double- and eventually even triple patterning, and to estimate which style-pitch combinations really do not have enough performance to be maintained. As we are dealing with simulated data only, and have used a simple image-in-resist model, these absolute values should however be treated with care. The final decisions on whether a particular case works or not, or where exactly the single-double-triple patterning transition points are, will – as always – have to come from wafer data. Some preliminary resist-images are included.

3.1. The 2D style: an endangered (if not already extinct) species

Figure 1 shows that Style A (noLI_2D) has quite ‘aggressive’ 2D shapes, both in Poly and Metal1, i.e. areas with densely packed lines or trenches running both in the horizontal and vertical direction. It has been shown before[8,9] that such patterns start suffering from serious deformations (ringing, bridging, pinching), if the pitches and gap sizes scale down. In order to assess how important these effects would be in the case of our test-chip and the pitch-combinations of our study, we did SMO optimizations on the Logic poly layer only, i.e. leaving aside the SRAM part of the test chip. This explores whether we have really come to the limit of such aggressive 2D patterns. Figure 4a shows the PV band (predicted contour variation, obtained from the SMO step, due to the focus-, dose- and mask-error-variations given in the ‘Conditions for SMO’ part of Table 4) of a small section of the Poly layer. (The SMO step itself of course being run on the entire poly logic clip). Although the PV band still seems reasonable at the most relaxed pitch combination of our study, severe ringing and bridging (and also line breaking, not shown) starts to occur when one of the pitches approaches the practical resolution limit of ~80 nm. Even more relevant is to consider the actual poly-CD control that is obtained on the transistor areas of the chip. We calculated an overall 3σ CD-variation (now taking the ‘Conditions for CD-variability calculations’ settings in Table 4), where this 3σ value considers the CD variation from transistor to transistor as well as the CD variation along every individual transistor. The result is shown in figure 4b, where we also plot the corresponding data we obtain with layout styles B and C, i.e. when the poly pattern is initially printed as an uninterrupted L/S pattern and the gaps are formed afterwards by using a poly-cut mask. Assuming that we request a CD-control value below ±10% of the Design poly CD value (as listed in Table 1), we see that only in case of the most relaxed pitch combination of Figure 4b, the 2D poly style seems capable of meeting this target. We therefore must conclude that such 2D poly layouts are no viable candidates any


more for even the 28 nm node. It is therefore no surprise that the poly-cut mask approach seems to be used by several companies already[12]: it seems to have appeared in SRAM at the 45 nm node and is now also being applied in Logic. It is interesting to note that the requested CD control becomes difficult even for the poly cut-mask approach at the small-pitch-combination side. Given that the calculated CD variations in our study are usually dominated by MEF, this shows that mask-CD control is becoming an important factor at the 20 nm node. A possible solution would be to print the poly L/S pattern not in a single-patterning step, but with e.g. a spacer defined double patterning process, which makes the CD control independent of lithography.

PX/PY = 110/90 nm

Gap = 45 nm 90/90

45 90/80

40 80/80 40

90/70 35

Figure 4a: Deformation of a small clip of the Poly pattern (Style A: noLI_2D) at decreasing pitch-gap combinations. Shown is the PV band obtained from an individual SMO optimization of the entire logic poly clip (not just of the small part shown

here), but leaving aside the SRAM part of the test chip. (A separate SMO run was done for every pitch combination)

2D poly (A)

(Poly = red, Active = green)

1D poly (B&C)

(Poly-cut PV band = purple)

3

4

5

6

7

8

P80P70

Target

P82P64

P90P70

P90P80

P80P80

P90P90

P100 P80

P120P100

P110 P90

1D poly

2D poly

3σ P

oly

CD

[nm

]

Pitch Combination (Node)

Figure 4b: Estimate of the total CD variation on the transistor areas of the logic chip (shaded in red) for the case of layout style A (2D poly) and layout styles B and C (1D poly, assumed to be done with the poly-cut mask approach). The ‘Target’ curve corresponds with 0.2 times the ‘Design Target’ for the poly line width of Table 1. (We added one pitch combination

here that did not appear in Table 1: PX=120 nm, PY=100 nm, and poly Design Target = 30 nm.)

It is obvious that also the Metal1 patterns of Style A will face similar problems as the ones we just described for Poly. As Metal1 is essentially only expected to make electrical connections, such that accurate CD control is less important than for Poly, we will limit the discussion here to the printability problem (i.e. avoiding lines to break or bridge). Figure 5 shows a few examples that illustrate the problem. (The cases deviate a little from our list in Table 1, but that should not affect the argument we try to make.) Figure 5a and 5b show the PV band of a small part of our logic chip as obtained after the SMO optimization (on the entire Logic clip!), for two different PX-PY combinations. (Note again that a separate SMO run is done for different PX-PY chips.) Again, we did the SMO on the logic chip only, to really search the print-ability limit of the aggressive 2D patterns. As in the poly case, we see that even with such a case-dedicated optimization, bridging and pinching starts to occur at some point: in the case of figure 5b, we get bridging at one of the small gaps. The logical step to take, then, is to see whether this problem can be overcome by splitting the pattern, i.e. search for a double pattering (e.g. LELE) solution. As shown in figure 5c this works well for the part of the chip that is shown: it is what we call ‘DP-compatible’, which means that it can be split into two separate patterns without any coloring conflicts. However, it is also well know that not all patterns are DP-compatible. Figure 5d shows one example, taken from our small logic chip, that has a high ‘coloring-conflict density’, and for which consequently we do not have a DP solution. We tried to redesign this part of our logic chip to make it DP-compatible, but found no way to do that, unless perhaps by significantly increasing the cell size, something that would not be acceptable, really, as it would significantly slow down or even effectively stop the area scaling we are trying to achieve!


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No-LI layout; Single

Pattering

Inital wafer prints

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Figure 7a: predicted PV bands after doing SMO on the Metal1 layer of the two SRAM layouts of Figure 2, both for a single- and a double-patterning approach. (The SMO was done assuming a negative-tone development process). Wafer prints were obtained using

the FAiRS-9521NT03 of FujiFilm NTD process. The test mask (that was used to make the wafer prints) was OPCed using a non-calibrated resist model (a constant-threshold model, in fact), so wafer CD and pattern shape can be further improved.


Figure 7b: Stitched SEM images of our complete M1 logic clip for the P80P80 case (i.e. vertical pitch between trenches = 80 nm); single patterning (negative-tone development, FujiFilm FAiRS-9521NT03). Solution of SMO

on SRAM applied to Logic cell; OPC done using a non-calibrated resist model (constant-threshold model), so further shape and CD improvement is possible. Design-contact layer is overlayed on the SEM image.

Figure 7 shows the predicted PV bands that are generated by the SMO optimization of the Metal1 layers, for a few relevant PX-PY pitch combinations, as a first indication of the scalability of the SP and DP option of the two SRAM layouts. (Note that we have done these SMO simulations assuming a negative-tone development (NTD) process. The advantages of NTD have primarily been demonstrated for contact-printing[15,23], but also for trenches do our simulations almost always show an advantage of NTD over the traditional positive tone development. See also our earlier SRAM work[22].) Although these PV-band images provide qualitative information only, they do show some interesting things: • The ‘no-LI’ SP case shows visibly wider PV bands for the horizontally oriented Metal1 wire, and completely breaks

down at the 90/90 nm pitch combination, whereas the ‘with-LI’ layout single patterning option shows reasonable PV bands down to the minimum Metal1 pitch of 80 nm. We included a few top-down SEM images (after litho) made with the source-mask obtained from the SMO optimization. These nicely confirm the observations from the simulated PV bands, at least in a qualitative way. (Note that no calibrated resist model was available when we did the OPC on this test mask, which means that the shape- and CD-fidelity of these wafer results can be further improved.) Figure 7b shows a similar SEM image from the Metal1 print of the Logic clip. The vertical pitch between the M1 trenches is 80 nm; single patterning using negative-tone developer. This result (where again an uncalibrated OPC model was used) shows the potential of printing an aggressive M1 case in single patterning of the uni-directional layout style.

• Both DP options in Figure 7a seem to last until the tightest pitch combination of our study (82/64 nm), even though the width of the PV bands becomes visibly larger. So, of course, we need to quantify the actual process latitudes.

We compare this in Figure 8, where we plot the minimum (i.e. worst) individual DOF@6%EL and the maximum (i.e. worst) individual MEF for the four cases of Figure 6. The interpretation of these results requires some discussion: • If we strictly apply our minDOF≥100nm and maxMEF≤4 basic criteria, only the Cut-mask results from the Style C

double-patterning options pass (both SRAM and Logic). • These DOF-MEF criteria for SRAM, however, can possibly be relaxed especially in the case of style C. The reason

is that the lowest DOF and highest MEF values occur in the Metal1 gaps between the Metal1 line segments. We mentioned before that we did our logic-cell layout such that these Metal1 line segments have a quite large extension over Contact and Via, which means that the CD control on the gaps can be relaxed. That then means that also the targets for DOF and MEF can be relaxed. If this is the case, possibly all single-patterning results from the style C logic are good enough. Final decision on the acceptability of single patterning for the style C cases (down to PY = 80 nm) should however best be verified from printed wafers, to be certain of this.

• The ‘no-LI layer’ SRAM results are clear in indicating that single patterning is no option, except perhaps for the first pitch combination (110/90 nm). Less clear is whether the double-patterning process margins obtained are sufficient: especially the DOF seems marginal. The comparison with the ‘with-LI layer’ SRAM results shows in any case the advantage of the latter.

• The bottom row of the Figure 8 graphs show the DOF-MEF results for the Style C Logic clip. If we again decide that MEF>4 values are acceptable on the line ends, the single-patterning solutions seem acceptable, maybe even down to PY = ~80 nm. The DP results (referring to the M1-cut mask solution) seem OK for all.

• We’re not showing any Style B logic results, but as for the SRAM, DOF is again a problem here. An SRAM-Logic co-optimization did not improve things, so our conclusion is that the Style B Metal1-results are insufficient, except perhaps for the most relaxed pitch combination (i.e. the 28 nm node case).

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(source & threshold) to the Logic chip (i.e. no additional optimization done, except of course OPC and assist placement): case of style C only.

3.3. Contact results for style B and C (i.e. without and with a LI layer)

For the optimization of the Contact layers, we followed the same basic approach as for the Metal1 layers: we optimize (SMO) the SRAM pattern first, as they are more difficult to solve than the logic Contact layers; then we apply this solution to the logic layers (MO) and see whether this approach gives us enough process latitude. As we will see, this approach actually works very well for Contact. Even though the results we obtained on the metal layers indicate that layout styles that do not use a LI layer do not have enough margin when moving towards the 20 nm node, it is interesting to keep the noLI SRAM contact layers in the study, if only to see whether the contact results lead to a similar conclusion. So, let’s look at the SRAM patterns first, again treating the layouts with and without a LI layer separately. As already can be seen from Figure 2, both SRAM types have pairs of rectangular contacts separated by a narrow gap that essentially scales together with the poly-pitch, PX. As there unfortunately are no design tricks in this particular case that can eliminate or relax this gap, it is to be expected that a pattern split will impose itself, once the process margins of this gap (and of course also of any other critical point in the layout) become marginal. Figure 9 shows the DP pattern split we came up with to bring the two contacts of the rectangular contact pairs (encircled) to separate layers. It is clear, however, from Figures 9a and b that the SRAM contact pattern cannot be split into two layers in a ‘clean’ way: although other options than the ones we show in Figure 9 are possible, one always is left with pairs of contacts at a short (i.e. diagonal) distance on the same split layer. A split into three patterns, however, does produce a very satisfactory result, as is shown in Figures 9c and d. To be noted is that (for both SRAM layouts) two of these three layers are actually identical, so that only two separate optimizations need to be done.


(a)

(b)

(c)

(d)

Figure 9: Split of the SRAM contact layer into two (a and b) and three (c and d) split layers. The cases shown correspond to our SRAM layout with (a and c) and without (b and d) a LI layer

We did the SMO optimization for our two SRAM layout types, and for the 8 pitch combinations (nodes) of this study, considering single-, double- and triple-patterning. Goal is of course to see whether we obtain enough process latitude in all cases, and where the transitions from single to double and double to triple patterning are likely to occur. As we mentioned before, also all our contact-optimization work assumes the use of a negative-tone development process, as there is good evidence (both from simulations and from experimental work) that negative tone offers better contact-performance than the more traditional positive-tone development. Also we would like to remind that when changing the PX-PY pitch combinations (node), we do not scale down the size of the contact litho target - as was already shown in Table 1 – but keep the after-litho contact area roughly constant at ~48×48 nm2. The reason is that printing random contact arrangements with reasonable process latitudes is difficult if the contact size is smaller than that. Process and/or etch will then further have to downsize the contacts[25] to bring them to the design-target that belongs to each node, something which may well become a challenge of its own. The resulting minimum-DOF and maximum-MEF values are shown in Figure 10. The results are relatively clear: • As could be expected, single-patterning is perhaps still feasible for the most relaxed pitch combination (PX-PY) of

our study. At smaller pitch combinations, there is not enough DOF or EL margin any more, and eventually contacts start merging. Figure 10c illustrates such an ‘almost’ contact-merging failure.

• Double patterning only helps to a relatively small extent: when decreasing the PX-PY combinations DOF quickly drop below our 100 nm target, and again contact merging starts to occur around the 80-80 nm or 90-70 nm combinations. (See also again Figure 10c.)

• So it seems that if one of the pitches approaches the ~80 nm values, triple patterning appears to be the only alternative. It offers a very reasonable minDOF, the maxMEF is well below our maxMEF = 4 target, and contacts are now sufficiently separated such that contact merging does not occur.

• When comparing the with- and without-LI SRAM contact results, Figure 10 also shows that there is not a very large difference, even though the transition from single- to double- to triple-patterning seems to impose itself slightly earlier in the case without a LI layer. When comparing these results with the Metal1 results of the previous section, Metal1-performance differences seem to be a stronger driver to implement LI than contact-performance differences.

Next we investigated whether we can simply apply the optimum obtained from the SMO optimization on the SRAM layer only to the entire chip, i.e. whether this optimum also provides enough latitude in the Logic part of the chip. Again we need to consider the possibility of pattern split. Since the contacts are less densely packed in the Logic part of the chip than in the SRAM, a split into two patterns was sufficient for logic. In cases where we have to switch to triple patterning in the SRAM, the logic cell can still be handled with a split into two layers. Figure 11 shows our minDOF-maxMEF results for the style using LI (Style C). The results show that Single patterning is no option any more beyond the PX-PY = 110-90 nm pitch case, and that Triple Patterning seems to be a must for the most aggressive pitch cases (i.e. 22/20 nm node).


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Figure 10: minDOF and maxMEF results from the SMO optimization of the SRAM contact layer (SMO on SRAM only). Figure c shows two examples of merging-contact failures; these occur in the SP and DP cases.

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Figure 11: minDOF and maxMEF results for the Logic part of the (style C) chip, when applying the SRAM optimum to the logic part of the chip, without further optimization (except, of course, OPC and assist placement on the logic)

3.4. Via, Metal2 and Via2: SRAM

As our Logic chip has no cell-to-cell routing, the Metal2 layer is essentially incomplete, and it makes little sense to include the Logic Metal2 in any optimization exercise, so we will limit the Metal2 discussion to SRAM only. Via should in principle be complete: as it is known which Metal1 wires (or ‘nets’) need to be connected to elsewhere in the chip, Vias can be placed. But we will also confine the Via discussion to SRAM only, as the Via in the SRAM cell is likely to be denser than in the Logic part of a chip (as also Table 2 suggests). From Figure 2 we can see that there is not much difference in the Via, Metal2 and Via2 layers of the two SRAM layouts (with or without LI), so we also do not need to make that distinction in this section. In conclusion, we will simply consider the litho performance of these three layers in SRAM, taking the example of the layout with LI. Once again, we will assume a negative-tone development (NTD) process for all three layers, when doing the SMO optimizations. For Via we only tried a single-patterning approach, as the Via pitches are relaxed compared to e.g. the pitches in the contact layer: the smallest via-via (center-to-center) distances are 2PX in the x-direction, 1.5PY in the y-direction and (PX

2+PY2)1/2 in the diagonal direction. Figure 12a shows that single patterning seems indeed a viable option, except

perhaps for the last two pitch combinations, for which the DOF is just below our 100 nm target value. If this perfor-mance is insufficient, also Via would have to be split in two patterns; a straightforward split without coloring conflicts. The Metal2 situation is a little more complicated. As can be seen from Figure 2, the SRAM Metal2 layer consists of a succession of short wires and long lines. They are all vertical and at a pitch PX. The lowest PX value for the cases included in this study is 80 nm, a pitch that does not enforce double patterning in itself, but this succession of long and short trenches actually leads to marginal SP litho performance, so we included both a single- and double-patterning option in our optimization. For double patterning, we chose to go for the cut-mask (actually a ‘fill-mask’, to be more


precise) approach, even though a simple pattern split would have been an obvious alternative. The results in Figure 12b show that the single-patterning option does not hold throughout our pitch-combination sequence. The failure points are in fact all the short vertical trenches: they suffer from an increasing MEF and a decreasing exposure latitude (and hence DOF at 6% EL), already in cases where the Metal2 gaps are still relatively large (>~60 nm). This can be understood from the alternation of dashed and continuous trenches (absorber lines on the mask, in the case of NTD!): as a consequence each of the line-end gaps is flanked by a continuous line at either side, which leads to a low image contrast in the gap. This makes the Metal2 layer non-trivial, and imposes the adoption of a double-patterning step somewhere in our pitch-sequence. The minimum Via2-pitch in our layouts is 1.5PY, making this a relatively ‘easy’ layer, as can be seen from Fig. 12c.

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3.5. Poly-cut mask (style B and C)

In section 3.1 we showed that for the technology nodes we are considering in this paper, poly needs to be printed with the cut-mask approach. Then, we also have to consider the litho performance of the cut-mask step.

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and MEF-evaluation lines and the predicted PV band. (The red lines are the to-be-cut poly lines.) In doing the SMO we performed the optimization for this layer on the entire test chip (i.e. SRAM + logic), deviating from the simpler approach (optimize on SRAM only) we were able to follow for several of the layers we discussed earlier. The reason is that in some respects the cut-mask is easier in the SRAM than in the logic: in SRAM the cut always runs over two adjacent poly lines, whereas single-line cuts are often required in the logic. As a (partial) compensation, the height of the cutting rectangle can be made a little larger in the logic. In the SRAM the height of the cutting rectangles (equal to the ‘Poly-gap size’ values in Table 1) are set by the amount of poly-over-active extension that is required, taking into account some minimum overlay-CDU tolerance. In our current exercise, we increased the cut-height in the Logic (somewhat arbitrarily) with 10 nm, as compared to the cut height in the SRAM.


The resulting DOF-MEF performance is shown in Figure 13c. Since it is important that the cut-pattern cuts the poly lines well, without touching the neighboring lines, we place the evaluation points (for DOF and MEF calculation) a few nm ‘outside’ the poly-line edges, and along the horizontal cut axis, as shown in Figures 13a and b. The simulated litho performance shows results that are well within the litho targets we are using in this paper.

3.6. Active We will end our discussion of the individual layers with Active. Active is perhaps not so often cited among the more difficult layers, but we will show in this section that this is likely to change, or that at least new restrictions will need to be placed on Active. The reason for that is that, traditionally, Active is a layer with a relatively strong 2D character, especially in the Logic, as can be seen from the layers clips shown in Figure 1. The reason for this is threefold: • In layout styles that do not use a LI layer, the connections between transistors and the gds or power rail are usually

made by extensions of the Active layer (the narrow, vertically oriented Active strips seen in Figure 1). Local Interconnect – if used – can take over that function, consequently making Active somewhat less 2-dimensional.

• When optimizing the (electrical) design of standard cells, each transistor gets its own ‘width’ (W), something that is then translated in a different y-dimension of the Active area. Although the active area of neighboring transistors are laid out in ‘longer islands’, this W-variations imply that these islands are not mere rectangles, but include this width-variation.

• And finally, these Active-islands are separated by from each other by a (narrow) non-active region (STI), whenever the source-drain of neighboring transistors does not have to be connected.

For less aggressive nodes, this 2D character of the Active layer was not so much of an issue, but for the technology nodes considered in this paper, this is no longer the case, an argument that in fact has been made in the past in several papers already[8,9]. To quantify this argument and see what the consequences are, we will in this section disregard the SRAM and do an SMO optimization on our full Logic-clip only (as the 2D character can be more extreme in Logic than in the SRAM). We will consider 3 types of Active layout: the ones on Style B and C of our study, and an extra one – which we will call Style D - in which we have almost reduced the width of the Active-islands to a single value (actually allowing a few arbitrary jogs only). These three ‘Active styles’ are illustrated in Figure 14. As everywhere in this study, we did a separate SMO optimization for each active-style and pitch combination. The results are quite remarkable. Figure 15 first of all shows the DOF-MEF metric that we have been using throughout this study. Note that the evaluation lines (i.e. the locations where these metrics were calculated) are placed 5 nm away from the nominal Poly-edge position (to include the effect of a 5 nm overlay error between Poly and Active). In the case of Style B, we have no latitudes at all at transistor locations where the Active width is changing very rapidly (the worst points being where Active makes this vertical extension to gnd or power). The situation of Style C is clearly better (which is yet another illustration that LI really helps the patterning of several aggressive-node layers), but it may be questionable whether the performance with Style C is sufficient: every time the Active jog is ‘large’ we see the process latitudes get worse. The best results are obtained with Style D, where these jogs are (almost) eliminated, and Active-width changes primarily occur at the edges of the active islands. This implies that a design rule is needed that defines the maximum allowed Active step. Simulations of the electrical transistor performance[26,27] may be helpful (or necessary) in determining an appropriate value for this design rule.

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Figure 14: Examples of three active-layout styles, with increasing shape regularity. Note that the last example actually corresponds to different transistor characteristics (transistor widths, W) than the first two.


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Figure 15: DOF-MEF comparison from an SMO optimization on the Logic-Active only. The image on the right shows an example of a DOF@6%=0nm failure mechanism: if the Active step height is too large, there is no 6% exposure

latitude left any more (⇒ DOF@6%EL = 0nm).

3.7. Summary Figure 16 tries to summarize our observations of section 3. Layout styles that allow Poly- or Metal1-2D shapes cannot be extended beyond the 28 nm node. We found that the same is in fact true for layouts that do not use a local-interconnect layer, essentially because of the bi-directionality of Metal1 in the SRAM cell and the difficult Active CD control. The only layout style that was found to have the potential to extend to the 20 nm node is our Style C, the main characteristics of which are the uni-directionality of all layers and the incorporation of a LI layer. That being said, the margins seem to become small anyway once approaching the 20 nm node, and careful layout optimization, also in the cell details, will be mandatory. Multiple patterning will be almost everywhere, something that we try to express in Figure 16 by doubling and tripling the arrows per layer, when we think that double- and triple patterning will need to be used.

Figure 16: Short summary of how the three layout styles of this study can be applied at the pitch-combinations (nodes)

we studied. Only Style C (uni-directional layouts with use of an Local Interconnect layer) shows potential to be extended to the 22/20 nm nodes. Single-, double- and triple-arrows symbolize single-, double- and triple- patterning.

4. CONCLUSIONS There exists general consensus that further area scaling in microlithography will impose restrictions on what critical layers will be allowed to look like. From the cases studied in this paper, it is clear that the time for this is now: even for the most relaxed pitch combination we included in our study (which we loosely relate to what could be called the 28 nm node) we already found important differences between the different layout styles we looked at. If the cases studied, as


well as the method and metric used, are accepted as relevant and meaningful, a few general conclusions seem unavoidable (see below). To that we also add a few general remarks on important elements we did not consider in this study. • There are a number of important enablers for scaling down to the 28 nm node, and even more so beyond:

o Uni-directional, single pitch type layouts offer very clear lithographic printability benefits over layouts with less regularity. This trend has started at previous nodes especially in Poly, but will have to be extended to most (if not all) non-contact type layers, including Active, when approaching the 20 nm node. At the most aggressive nodes, also the use of cut-masks is likely find use in most of these layers. In the cases we studied, we found no area penalty from the use of such unidirectional layouting (rather the contrary, in fact), even though that is sometimes thought. As layout changes of one or the other type will become mandatory anyway (layout changes would also be needed, for example, to make older-node cases DP-compatible) it seems very meaningful to consider to go for a more drastic change in the layout style and adopt one of the very regular layout styles, of which style C of this study is one example. Apart from the large style differences we highlighted in this paper, also detail-layout optimization (i.e. in particular cell areas) can significantly help improve (or even create any) litho process margins and the definition of design rules. Future nodes will not exist unless they are built on joint optimization of layout and lithography.

o We have shown that the Local-Interconnect layer relieves strain on several layers, in particular on Metal1 and Active, and – to a lesser extent - on Contact. Metal1 appears very difficult (if not impossible) to make uni-directional if no LI is used; double-patterning Metal1 cannot ensure sufficient process margin (esp. in the SRAM) already at 28 nm node and even more beyond. LI also allows to make the Active layer more regular.

o Some of the process layers that are most difficult today, such as contact- and metal-type layers, traditionally use dark-field masks. There is increasing evidence that negative-tone developers can bring substantial improvement in process margins and hence in the practical resolution limits of the current lithography tools.

o The recent introduction of new and powerful computational tools (for layout-dedicated source-mask optimization, the use of ‘freeform’ sources, model-based assist placement, and – hopefully soon – reliable assist-printing predictability) gives lithographers the possibility to more thoroughly search for the settings that can push a technology into a manufacturable regime.

• Poly-Metal1 pitch combinations that correspond to essentially the same SRAM bit-cell area (80/80 and 90/70 nm for example) sometimes show a quite different litho performance for at least some layers. So a careful choice of these basic pitches can in fact be quite important.

• The 22/20 nm nodes then appear feasible, at least from a patterning point of view, even though the process margins obtained in this study are becoming quite small. As this study was based on simulations only, simulations that did not even incorporate a resist model, the absolute values of all the quantities we obtained should moreover be handled with care. Clearly, only on-wafer data can validate whether the pass/fail decisions we have taken are reasonable, or identify where transitions from e.g. single- to double patterning actually occur.

• Pass/fail decisions are also based on assumed target values for the metric used in the evaluation, but these themselves are subject to uncertainty. The possibilities to extend litho results into predictions of the electrical behavior[26-27] of the structures under consideration can therefore be a valuable addition to this kind of study.

• The actual pass/fail verdict on future technologies will also be influenced to an increasing extent by the impact of overlay errors between layers, an element that was not included in our study. As the overlay specs of the litho tools are not expected to scale with the node any more, it is likely that also more self-aligned technologies will find their place in the production of future node devices.

The development of advanced nodes relies of course on much more than just solving the lithographic patterning problem, and the definition of the most appropriate layout style will also need to consider electrical cell-performance, including a study of parasitics. But the lithographic challenges seem to become increasingly important and will continue to shape cell layout.

ACKNOWLEDGEMENTS We acknowledge the support of the management of all co-author companies for this project and of Brion for helping us do the many SMO runs that were needed in this study. We also thank Fujifilm for providing their negative-tone developer, and Toppan for making a mask with many of the optimized masks from this study. Both will soon allow us to make more on-wafer versions of many of the simulated patterns. Also thanks to Staf Verhaegen and Jeroen Van de Kerkhove (imec), as well as everybody who helped us with their discussions and their interest in this topic.


REFERENCES

[1] L. Capodieci, “Design for Manufacturability, from 45 to 32 to 22 nm and beyond: Challenges and opportunities for extending the IC Technology Roadmap,” DFM Outlook (2007).

[2] H. Muta and H. Onodera, “Manufacturability-aware design of standard cells,” IEICE Trans. Fundamentals, Vol. E90-A, No. 12, 2682 (2007).

[3] T. Jhaveri, V. Rovner, L. Pileggi, A. Strojwas, D. Motiani, V. Kheterpal, K. Tong, T. Hersan, D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” JM3 Vol.6, 1 (2007).

[4] B. Taylor and L. Pileggi, “Exact combinatorial optimization methods for physical design of regular logic bricks,” Proc. 44th Design Automation Conference, DAC2007, 344 (2007).

[5] M. C. Smayling, H. Y. Liu, L. Cai, “Low k1 logic design using gridded design rules,” Proc. SPIE 6925, 69250B1-7 (2008). [6] H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi and H. Onodera, “Effect of regularity-enhanced layout on printability and

circuit performance of standard cells,” 10th Int’l Symposium on Quality Electronic Design, 195 (2009). [7] M. C. Smayling, V. Axelrad, “32nm and below Logic Patterning using Optimized Illumination and Double Patterning,” Proc.

SPIE 7274, 72740K1-8 (2009). [8] L. Liebmann, “DfM, the Teenage Years,” Proc. SPIE 6925, 692502-1-14 (2008). [9] D. Abercrombie, P. Elakkumanen and L. Liebmann, “Restrictive design rules and their impact on 22 nm design and physical

verification,” Electronic Design Processes Symposium (EDPS) 2009. [10] C. Bencher, H. Dai, Y. Chen, “Gridded Design Rule Scaling: Taking the CPU toward the 16nm node,” Proc. SPIE 7274,

72740G1-14 (2009). [11] C. Webb, “Intel design for manufacturability and evolution of design rules,” Proc. SPIE 6925, 692503-1 (2008). [12] D. James, “Design-for-manufacturing features in nanometer logic processes – A reverse engineering perspective,” IEEE 2009

Custom Integrated Circuits Conference, 207 (2007). [13] S. R. Nassif and K.J. Nowka, “Physical design challenges beyond the 22 nm node,” ISPD 19, 13 (2010). [14] A. E. Rosenbluth et al, “Optimum Mask and Source pattern to print a given shape,” JM3 Vol. 1, 13 (2002). [15] J. Bekaert, B. Laenens, S. Verhaegen, L. Van Look, D. Trivkovica, F. Lazzarino, G. Vandenberghe, P. Van Adrichem, R. Socha,

S. Baron, M.C. Tsai, K. Ning, S. Hsu, H.Y. Liu, M. Mulder, A. Bouma, E. van der Heijden, O. Mouraille, K. Schreel, J. Finders, M. Dusa, J. Zimmermann, P. Graüpner, J.T. Neumann, C. Hennerkes “Freeform illumination sources: An experimental study of source-mask optimization for 22 nm SRAM cells,” Proc. SPIE 7640, 764008 (2010).

[16] T. Mülders, V. Domnenko, B. Küchler, T. Kimpel, H.-J. Stock, A. Poonawala, K. Taravade, W. Stanton, “Simultaneous source-mask optimization: a numerical combining method,” Proc. SPIE 7823, 782335 (2010).

[17] H. Hayashida, Y. Toyoshima, H. Shinagawa, Y. Suizu, I. Kunishima, K. Suguro, K. Hashimoto, “Manufacturable local interconnect technology fully compatible with titanium salicide process,” VLSI Multilevel Interconnection Conference Proceedings., Eighth International IEEE, (1991).

[18] C.R. Bachelu, M.C. Lefebre, “A study of the use of local interconnect in CMOS leaf cell design,” International Symposium on Circuits and Systems, ISCAS, 1258 (1992).

[19] M.C. Smayling & S.T. Becker, “Methods, Structures and designs for self-aligning local interconnects used in integrated circuits,” US patent No. US7.763,534 B2 (2010).

[20] M. C. Smayling, M. Dusa, R. Socha, “22nm Logic Lithography in the Presence of Local Interconnect”, Proc. SPIE 7640, 764043 (2010).

[21] S. Verhaegen, A. Nackaerts, V. Wiaux, E. Hendrickx, “Impact of lithography on the design of next generation logic cells,” Semicon Japan (2006).

[22] S. Verhaegen, M. Smayling, P. De Bisschop, B. Laenens, “Joint-Optimization for SRAM and Logic for 28nm node and below,” Proc. SPIE 7641, 764107 (2010).

[23] L. Van Look, J. Bekaert, V. Truffert, V. Wiaux, F. Lazzarino, M. Maenhoudt, G. Vandenberghe, Mario Reybrouck, Shinji Tarutani, “Printing the Metal and Contact Layers for the 32 and 22 nm Node: Comparing positive and negative Tone Development Process,” Proc. SPIE 7640, 764011 (2010).

[24] S. Tarutani, S. Kamimura, K. Fujii, K. Katou, Y. Enomoto, “High volume manufacturing capability of negative tone development process,” Proc. SPIE 7972, 7972-22 (2011).

[25] X. Miao, L. Huli, H. Chen, X. Xu, H. Woo, C. Bencher, J. Shu, C. , C. Borst, “Double Patterning Combined with Shrink Technique to Extend ArF Lithography for Contact Holes to 22nm Node and Beyond,” Proc. SPIE 6924, 69249 (2008).

[26] W. Poppe, L. Capodieci, J. Wu, and A. Neureuther, “From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors,” Proc. SPIE 6156, 615626 (2006).

[27] T-B. Chan, P. Gupta, “On electrical modeling of imperfect diffusion patterning,” Int. Conf. on VLSI Design, 224 (2010).


Joint optimization of layout and litho for SRAM and logic towards … · 2013-03-15 ·...

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