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Transcript of John Zhao Product Manager - · PDF fileSoftware Defined Radio with MATLAB John Zhao Product...
1 © 2014 The MathWorks, Inc.
Software Defined Radio with MATLAB
John Zhao
Product Manager
2
Agenda
Software Defined Radio (SDR) Support in MATLAB
– As radio peripheral
– As FPGA target
– MathWorks Support Package
SDR hardware as radio peripheral
– RTL-SDR
SDR hardware as FPGA target
– Xilinx FPGA based SDR
Summary
3 © 2014 The MathWorks, Inc.
Software Defined Radio (SDR) Support
in MATLAB
Overview
4
Typical SDR System
Baseband
Processing
Modulation
Digital Front End
Digital Filters,
Sample Rate Conversion
Analog Front End
Filters, Mixer,
ADC/DAC
Tunable RF Card FPGA Board Host computer
GigE FMC
Commercial-off-the-shelf hardware
5
SDR hardware Supported by MathWorks
RTL-SDR ($25)
– Ultra low-cost, low-bandwidth (up to ~3MHz)
– Rx Only
USRP2, N210 ($3000)
– Customizable RF front-end
Xilinx FPGA-based radio ($2500)
– High bandwidth (~25MHz)
– Possible FPGA target
6
SDR as Radio Peripheral
• Configure radio hardware from MATLAB and Simulink
• Acquire live radio signals
• Stream baseband real-time data to MATLAB and Simulink
NooElec RTL-SDR
7
SDR as FPGA Target
Design custom algorithms in MATLAB/Simulink
Verify algorithms with real radar data
Generate HDL Code for FPGA implementation
Simulink
HDL Code
Ettus Research
USRP® N210 Xilinx ML605 and
ADI FMComms1
Or
8 © 2014 The MathWorks, Inc.
SDR Hardware as Radio Peripheral
RTL-SDR
9
SDR as Radio Peripheral: RTL-SDR
• Connect to computer running MATLAB through USB
• Receive streaming RF signals
• Configure center frequency and sample rate in MATLAB
10
RF
An
ten
na
NooElec SDR Mini Receiver
• fs – I/Q Data Sampling Frequency
• Gain Control Parameters
• Frequency Correction
The RTL-SDR USB RF Receiver
Configuring SDR parameters (via USB port)
• fRF - RF Center frequency
7cm
to PC
USB
Port
at
fs Hz
11
fRF RF VCO Frequency (50MHz to 1GHz)
LNA/AGC Tuner Gain Control
VCO Voltage Controlled Oscillator
Analogue
Raphael Micro R820T Silicon Tuner
Digital
RTL2832U – Digital IF to Baseband Receiver
RF
An
ten
na
fs Sampling frequency (up to 2.8MHz)
ADC Analogue to Digital Converter
I / Q In-phase & Quadrature-phase Channel
FIR Finite Impulse Response
NCO Numerically Controlled Oscillator
RF
Filter
IF
Filter
LNA AGC
cos2pfRFt VCO
NooElec SDR Mini Receiver
ADC
cos2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
fs
Re-
Sampler/
Synch.
sin2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
Re-
Sampler/
Synch.
7 bits
7 bits
I
NCOs
Q
to PC
USB
port
An IF Software Defined Radio
12
RF
fc = fRF – fIF
400 MHz
0.2 MHz
Sig
na
l P
ow
er
(dB
)
0
fre
qu
en
cy
An IF Software Defined Radio (design flipped left to right now!)
RF
An
ten
na
RF
Filter
IF
Filter
LNA AGC
cos2pfRFt VCO
ADC
cos2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
fs
Re-
Sampler/
Synch.
sin2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
Re-
Sampler/
Synch.
7 bits
7 bits
I
NCOs
Q
13
RF
fc = fRF – fIF
Analog IF
fIF
400 MHz
0.2 MHz 0.2 MHz
Sig
na
l P
ow
er
(dB
)
0
fre
qu
en
cy
An IF Software Defined Radio (design flipped left to right now!)
RF
An
ten
na
RF
Filter
IF
Filter
LNA AGC
cos2pfRFt VCO
ADC
cos2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
fs
Re-
Sampler/
Synch.
sin2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
Re-
Sampler/
Synch.
7 bits
7 bits
I
NCOs
Q
14
14.4 MHz
fs/2
RF
fc = fRF – fIF
Digitized IF
fIF
400 MHz
0.2 MHz 0.2 MHz
Sig
na
l P
ow
er
(dB
)
0
fre
qu
en
cy
fs = 28.8MHz
An IF Software Defined Radio (design flipped left to right now!)
RF
An
ten
na
RF
Filter
IF
Filter
LNA AGC
cos2pfRFt VCO
ADC
cos2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
fs
Re-
Sampler/
Synch.
sin2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
Re-
Sampler/
Synch.
7 bits
7 bits
I
NCOs
Q
15
Baseband
14.4 MHz
fs/2
RF
fc = fRF – fIF
400 MHz
0.2 MHz 0.2 MHz
0.2 MHz -0.2 MHz
Sig
na
l P
ow
er
(dB
)
0
fre
qu
en
cy
fs = 28.8MHz
An IF Software Defined Radio (design flipped left to right now!)
RF
An
ten
na
RF
Filter
IF
Filter
LNA AGC
cos2pfRFt VCO
ADC
cos2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
fs
Re-
Sampler/
Synch.
sin2pfIF(n/fs)
Low Pass
FIR Filter +
Decimation
Re-
Sampler/
Synch.
7 bits
7 bits
I
NCOs
Q
fs2 = 2.8MHz
Digitized IF
fIF
16
RF
An
ten
na
NooElec SDR Receiver fs
And what RF signals can we find?
FM Radio 87.5 – 108 MHz
Aeronautical 108 – 117 MHz
Meteorological ~ 137 MHz
Fixed mobile 140 – 150 MHz
Special events broadcast 174 – 217 MHz
Fixed mobile, (space to Earth) 267 – 272 MHz
Fixed mobile, (Earth to space) 213 – 315 MHz
ISM band (short range) ~433 MHz
Emergency services 450 – 470 MHz
UHF TV Broadcasting 470 – 790 MHz
Fixed mobile telephony 862 – 890 MHz
GSM-R band (UK) 921 – 925 MHz
Parameters from Simulink (via USB port)
• fRF- RF Centre frequency
• fs – Sampling Frequency
• Gain Control Parameters
• Frequency Correction
Range: ~80 MHz to 1GHz
to USB
port
17
MathWorks RTL-SDR Driver (Simulink)
I/Q data (complex)
fs Sampling frequency (up to 2.8MHz)
fRF RF Center Frequency (50MHz to 1GHz)
+ Tuner gain parameters
Frequency correction parameters
fs
fRF
18
MathWorks RTL-SDR Driver (MATLAB)
fs
Get more information in the MATLAB doc
on using the RTL-SDR System Object.
fRF
fs Sampling frequency (up to 2.8MHz)
fRF RF Center Frequency (50MHz to 1GHz)
+ Tuner gain parameters
Frequency correction parameters
19
Example: RTL-SDR
Airplane detection
20
Other Examples of RTL-SDR
FM Radio Receiver
RF Spectrum Analyzer
Frequency Offset Calibration
FRS/GMRS receiver
21
SDR as Radio Peripheral - Summary
Work with real signals
– Audio, video, RF
Radio peripherals
– Low-cost alternative to test & measurement instruments
Support packages extend connectivity
MathWorks RTL-SDR Page http://www.mathworks.com/hardware-support/rtl-sdr.html
22 © 2014 The MathWorks, Inc.
SDR Hardware as FPGA Target
Xilinx FPGA based radio
23
SDR as FPGA Target: Xilinx FPGA
Design custom algorithms in MATLAB/Simulink
Verify algorithms with real radar data
Generate HDL Code for FPGA implementation
Simulink
HDL Code
Xilinx ML605 and
ADI FMComms1
24
Xilinx FPGA-Based Radio
FPGA Board
– Xilinx ML 605 Evaluation board (Virtex 6 FPGA)
RF FPGA Mezzanine Card (FMC)
– Analog Devices - FMCOMMS1-EBZ
400 MHz to 4 GHz; 50MHz Analog BW
– Bitshark FMC-1RX from Epiq Systems
300 MHz to 4 GHz; 50MHz Analog BW
25 G
ig-E
FM
C
FPGA Top Level for SDR
Host FPGA RF Card
uController
Analog
FE
Control I/O
MATLAB
or
Simulink
User
Design ADC
DAC Analog
FE
NCO
Decimation
Filtering Mixer
User
Design
NCO
Interpolation
Filtering Mixer
Transmit Data path
Receive Data path
RFOUT
RFIN
26
RF Control from MATLAB and Simulink
27
Generate optimized HDL Code
Guided workflow from model to programming FPGA
FPGA-in-the-loop verification
FPGA Targeting with HDL Coder
28
Examples for Xilinx based radio
WLAN Beacon Frame Receiver
QPSK Receiver
29
SDR as FPGA Target – Summary
Connect reconfigurable SDR hardware with MATLAB
– USRP N210
– Xilinx Virtex-6 FPGA + RF card
Extend the radio peripheral capability to SDR target
– Run user algorithms on FPGA
Integrated with HDL Coder
– Automated workflow for programming FPGA
30
More information
Product Manager John Zhao ([email protected])
Technical Resources MathWorks SDR solution
http://www.mathworks.com/sdr.html
Communications System Toolbox
http://www.mathworks.com/products/communications/
YouTube of Simulink RTL-SDR receiving desktop transmitted AM
http://tinyurl.com/n2dccsz
31
Thank you!