John Aynsley, Doulos - Accelleravideos.accellera.org/tlm20tutorial/pdf/part_2_tlm20... ·...
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DVCon 2009
TLM-2.0 in Action: An Example-based Approach to Transaction-level Modeling and the New World of Model Interoperability
John Aynsley, Doulos
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TLM Introduction
CONTENTS
• What is TLM and SystemC?
• Creating a virtual platform model
• The OSCI TLM-2.0 standard
• Achieving speed and interoperability
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Transaction Level Modeling
3
RTL
Pin Accurate
Simulate every event!
RTL
Functional Model
Functional Model
100-10,000 X faster simulation!
Function Call
write(address,data)
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Reasons for using TLM
Software development Firmware / software
Accelerates product release schedule
Test bench
Hardware verification
RTL
TLM = golden model
Performance analysis TLM
Fast
Ready before RTL
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Multiple Languages
Mixed language environments Firmware / software
Test bench
RTL VHDL, Verilog, SystemVerilog
TLM SystemC used as golden reference
Home grown C++ / SystemC
VHDL, Verilog for design
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Reasons for using SystemC
Robust open source proof-of-concept C++ simulator
Flexibility re platforms and licensing
Common language across disciplines Builds bridges between system, s/w and h/w
Easy integration
Tool vendors add value
Only requires a C++ compiler
6
Industry standard IEEE 1666™
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TLM Introduction
• What is TLM and SystemC?
• Creating a virtual platform model
• The OSCI TLM-2.0 standard
• Achieving speed and interoperability
CONTENTS
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FUNCTIONAL VIEW
Algorithm developer
PROGRAMMERS VIEW
Software developer
ARCHITECTURE VIEW
Tuning the platform
VERIFICATION VIEW
Functional verification
RTL Implementation
Untimed
Approximately-timed Loosely-timed
Untimed through Cycle Accurate
Use Cases
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Typical Use Case: Virtual Platform
CPU ROM DMA RAM
Interrupt Timer Bridge
Bridge
DSP ROM RAM
A/D Interrupt Timer I/O
Memory interface I/O DMA RAM Custom
peripheral
Software
D/A
Software
9
Multiple software stacks
Digital and analog hardware IP blocks
Multiple buses and bridges
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Virtual Platform Characteristics 1
• Register accurate, functionally complete
• No clock, no pins, no implementation detail
• Loose or approximate timing only
• Fast enough to boot software O/S in seconds
• Available months before RTL
• Accurate enough to stay in use post-RTL
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Virtual Platform Characteristics 2
Instruction Set Simulator or software stubs
Transaction-Level Model RTL
Available early Available early Much later
Fast enough to run applications
Fast enough to run applications
Too slow to run applications
Little or no hardware detail
Register-accurate Register-accurate and pin-accurate
No timing information Some timing information Cycle-accurate timing
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Transaction-Level Modeling
Simple functional models, e.g. C programs
Transaction + timing
Concurrent simulation environment
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SystemC / TLM is the Glue!
13
VHDL Verilog
• Transaction-level modeling is communication-centric
ISS
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TLM Introduction
• What is TLM and SystemC?
• Creating a virtual platform model
• The OSCI TLM-2.0 standard
• Achieving speed and interoperability
CONTENTS
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OSCI TLM-2.0 Standard
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• Transaction-level memory-mapped bus modeling
• Based on SystemC
• Released in June 2008
• OSCI LRM in 2009
between TLM models of IP blocks
comparable to ISS
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Coding Styles and Mechanisms
Blocking transport
Non-blocking transport DMI Sockets Quantum Generic
payload
Mechanisms (definitive API for TLM-2.0 enabling interoperability)
Use cases
Software development
Architectural analysis
Hardware verification
Software performance
Loosely-timed
Approximately-timed
TLM-2 Coding styles (just guidelines)
Phases
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Coding Styles
• Loosely-timed = as fast as possible
• Only sufficient timing detail to boot O/S and run multi-core systems
• Processes can run ahead of simulation time (temporal decoupling)
• Each transaction completes in one function call
• Uses direct memory interface (DMI)
• Approximately-timed = just accurate enough for performance modeling
• aka cycle-approximate or cycle-count-accurate
• Sufficient for architectural exploration
• Processes run in lock-step with simulation time
• Each transaction has 4 timing points (extensible)
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Interoperability Layer
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Target Initiator
1. Core interfaces and sockets
2. Generic payload
Command Address Data Byte enables Response status
Extensions
3. Base protocol
BEGIN_REQ
END_REQ
BEGIN_RESP
END_RESP
Maximal interoperability for memory-mapped bus models
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Example – Initiator & Target Sockets
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struct Initiator: sc_module { tlm_utils::simple_initiator_socket<Initiator> socket; SC_CTOR(Initiator) : socket("socket") { SC_THREAD(thread_process); } ... }; struct Target: sc_module { tlm_utils::simple_target_socket<Target> socket; SC_CTOR(Target) : socket("socket") { socket.register_b_transport (this, &Target::b_transport); } virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay ); ... };
Default: 32-bits wide, base protocol
Construct and name socket
Blocking transport Sockets
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Example – Socket Binding
20
struct Top: sc_module { Initiator *initiator; Target *target; SC_CTOR(Top) { initiator = new Initiator ("initiator"); target = new Target ("target"); initiator->socket.bind( target->socket ); } };
Sockets
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Example - Initiator
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void thread_process() { tlm::tlm_generic_payload* trans; sc_time delay; ... trans = m_mm.allocate(); trans->acquire(); trans->set_command( tlm::TLM_WRITE_COMMAND ); trans->set_data_length( 4 ); trans->set_streaming_width( 4 ); trans->set_byte_enable_ptr( 0 ); trans->set_address( addr ); trans->set_data_ptr( (unsigned char*)( &word ) ); trans->set_dmi_allowed( false ); trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE ); init_socket->b_transport( *trans, delay ); if ( trans->get_response_status() <= 0 ) SC_REPORT_ERROR("TLM-2", trans->get_response_string().c_str()); trans->release(); ... }
Get transaction object from pool
8 attributes you must set
Blocking transport
Generic payload
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Example - Target
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virtual void b_transport( tlm::tlm_generic_payload& trans, sc_core::sc_time& t ) { tlm::tlm_command cmd = trans.get_command(); sc_dt::uint64 adr = trans.get_address(); unsigned char* ptr = trans.get_data_ptr(); unsigned int len = trans.get_data_length(); unsigned char* byt = trans.get_byte_enable_ptr(); unsigned int wid = trans.get_streaming_width(); if ( byt != 0 || len > 4 || wid < len ) { trans.set_response_status( tlm::TLM_GENERIC_ERROR_RESPONSE ); return; } if ( cmd == tlm::TLM_WRITE_COMMAND ) memcpy( &m_storage[adr], ptr, len ); else if ( cmd == tlm::TLM_READ_COMMAND ) memcpy( ptr, &m_storage[adr], len ); trans.set_response_status( tlm::TLM_OK_RESPONSE ); }
Execute command
Successful completion
6 attributes you must check
Target supports 1-word transfers
Blocking transport
Generic payload
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Interconnect component
0, 1 or many
Initiators, Targets and Interconnect
Initiator Target
Initiator socket
Target socket
Initiator socket
Target socket
Forward path
Backward path
Forward path
Backward path
Transaction object
23
Sockets Generic payload
• Single transaction object
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Core Interfaces
Initiator Target
Target socket
Backward path
nb_transport_bw()
invalidate_direct_mem_ptr()
Initiator socket Forward path
b_transport ()
nb_transport_fw()
get_direct_mem_ptr()
transport_dbg()
• Sockets group interfaces, bind both paths with one call, and are strongly typed
Interface methods
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TLM Introduction
• What is TLM and SystemC?
• Creating a virtual platform model
• The OSCI TLM-2.0 standard
• Achieving speed and interoperability
CONTENTS
Copyright © 2007-2009 by Doulos. All rights reserved.
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Core interfaces
Sockets
Generic payload
Base protocol
Interoperability versus Internals
26
Initiator
Interoperability layer
Target
Coding Style
Loosely- or Approximately-timed
Utilities
Convenience sockets
Quantum keeper (LT)
Payload event queues (AT)
Instance-specific extensions (GP)
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Loosely-timed
Cycle-accurate simulation
Initiators
Ticks
Quantum
Temporally decoupled simulation
Quantum
Process scheduling and context switching
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• Each initiator runs ahead to quantum boundary before context switching • Limited synchronization between initiators • Used with DMI to bypass interconnect DMI Quantum Blocking
transport
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Approximately-timed
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Process 1
Process 2
Process 3
0 10 20 30 40 50
Annotated delays
• Transactions are annotated with delays
• Each process is synchronized using the SystemC scheduler
• A transaction has multiple phases Non-blocking
transport Phases
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b/nb Conversion
LT Initiator
simple_target_socket simple_initiator_socket
b_transport LT Target
b_transport Interconnect
AT Initiator
nb_transport_fw
socket.register_b_transport
29
Non-blocking transport
Blocking transport Sockets
nb_/b_transport adaptor
• Models should be performance-matched
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The Generic Payload
• Typical attributes of memory-mapped busses • reads, writes, byte enables, single word transfers, burst transfers, streaming
• Off-the-shelf general purpose payload • used with the Base Protocol for abstract bus modeling
• ignorable extensions allow full interoperability
• Used to model specific bus protocols • mandatory extensions
• can only bind sockets with same protocol type (compile-time check)
• use the same generic payload machinery
• low implementation cost when bridging protocols
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Generic payload
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Extensions
Target
Base Protocol Router
Initiator
Initiator Target
Generic Payload
Extension
Interconnect
Generic Payload
Extension
Generic Payload
Extension
Generic Payload
Extension
Generic Payload
Extension
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Private extension
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Kinds of Extension
• Generic payload extensions can be
• Ignorable – compliant to the base protocol
• Mandatory – necessitates a new protocol type
• Private – only used by a single module (hence ignorable)
• Instance-specific – usually private (hard to access elsewhere)
• Sticky – remain when transaction is returned to a pool
• Auto – freed when transaction is returned to a pool
• Base protocol phases BEGIN_REQ, END_REQ, BEGIN_RESP, END_RESP
• Extended phases
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Initiator Interconnect Target
Kinds of Interoperability
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• Base protocol, generic payload + ignorable extensions • Functional incompatibilities still possible
• New protocol, generic payload + extensions • Cannot bind sockets of differing protocols • Generic payload and base protocol still exploited for consistency of coding style • Generic payload extension mechanism exploited for ease-of-adaption
Target Adaptor Initiator
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Levels of Use
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1. Buy models with the TLM-2.0 sticker
2. Write LT components
Beware: nb_transport & endianness
3. Write AT components
4. Support LT/AT switching
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