Jeff Allen Jacob Biamonte

ECE 572/672 Project: Testing

Other important moments in the history of quantum test set generation

• Original Idea from right here at PSU!• Markov/Hayes at the U.M. work was done on reversible test set

generation that at least made one think about quantum test set generation (We are the only group in the world to cite this paper thus far) This is one of the most fundamental papers published in recent times!

• Many papers exist on regular testing, U.M. group and us are the only ones doing this research now (I think anyway), when reversible computers become commercial 1,000s of test set generation papers will be written, we just don’t know when this will happen but we hope it will be in our life times.

• Ed Perkins wrote some reversible test generation software last year, he did a good job but I have a new method and new software

Goal Number One

• Illustrate classical known method to detect and localize faults on a simple AND gate

• Explain the classical fault model

• Explain the use of this in large scale binary and analog circuit design

Classical Fault Localization• Example 1: AND gate inserting stuck-at

faults.• Seven possible situations:

a

by

a

by

a

by

Sa1

a

by

a

by

a

by

Sa0

Sa0Sa0

Sa1Sa1

Stuck-at-1 at a

Stuck-at-0 at a

Stuck-at-1 at b Stuck-at-1 at y

Stuck-at-0 at yStuck-at-0 at b

a

by

Good Circuit

Classical Fault LocalizationCreate truth table showing good circuit and all cases of faults

a b Good Circuit

sa1 a sa1 b sa1 y sa0 a sa0 sa0 y

0 0 0 0 0 1 0 0 00 1 0 1 0 1 0 0 01 0 0 0 1 1 0 0 01 1 1 1 1 1 0 0 0

Indicates a faulty output (output different than that of good circuit)

• Goal: minimize the number of test vectors needed to detect and localize all faults

Classical Fault Localization

1

0

1

0

b

XXX1

XX1

XX0

X0

sa0 ysa0sa0 asa1 ysa1 bsa1 aGood Circuit

aInput Vectors Chosen so as to

detect and localize all faults with minimum number of test

vectorsT1

T2

T3

T4

T2P F

1

0

0

b

XXX1

X1

0

sa0 ysa0sa0 asa1 bGood Circuit

a

T1T3

T4 1

0

0

b

1

X1

X0

sa1 ysa1 aa

T1T3

T4

Possible: Good Circuit, sa1 a, sa1 b, sa1 y, sa0 a, sa0 b, sa0 y

Possible: sa1 a, sa1 y

Before Test:

After Test:

Fault Table of AND gate with stuck at faults

Applying Test Vector 01:

Possible: Good Circuit, sa1 b, sa0 a, sa0 b, sa0 y

1

0

0

b

XXX1

X1

0

sa0 ysa0sa0 asa1 bGood Circuit

a

T1T3

T4 1

0

0

b

1

X1

X0

sa1 ysa1 aa

T1T3

T4

Good Circuit, sa1 a, sa1 b, sa1 y, sa0 a, sa0 b, sa0 y

Good Circuit, sa1 b, sa0 a, sa0 b, sa0 y sa1 a, sa1 y

Because all of the stuck-at-0 faults have the same entries in the fault table, there is no way to localize them, unless we can measure all parts of the circuit.

Good Circuit, sa0 a, sa0 b, sa0 y

1

0

b

XXX1

0

sa0 ysa0sa0 aGood Circuit

a

T1T4

P F

T2

P F

T3

P F

T3

Sa1@a Sa1@ySa1@b

Sa0@a, Sa0@b, Sa0@yGood Circuit

P F

T4

1

0

1

0

b

XXX1

XX1

XX0

X0

sa0 ysa0sa0 asa1 ysa1 bsa1 aGood Circuit

a

T1

T2

T3

T4

Original Fault Table

If we would have tested exhaustively it would have taken all 4 tests, we did it in 3, (and we know

the type of error present!)

Goal Number Two

• Show another example, but this time with a reversible circuit and Markov, Hayes stuck-at technique

• Explain some of the differences between classical fault detection and reversible fault detection

Example 2, a reversible circuit

b'

a

b

a '0 0 0 00 1 0 11 0 1 11 1 1 0

a b a b

Stuck-at-0Stuck-at-1

Sa0

Sa1

0011

1100

Example 2 continued…

b'

a

b

a 1

3 4

2

Locations for faults

a b GC Sa0@1 Sa0@2 Sa0@3 Sa0@4 Sa1@1 Sa1@2 Sa1@3 Sa1@4

00 00 00 00 00 00 11 10 01 01

01 01 01 01 00 00 10 11 01 01

10 11 00 00 11 10 11 11 10 11

11 10 01 00 11 10 10 10 10 11

Table comparing the correct value of the circuit (GC) with the incorrect values

b'

a

b

a sa0'

0 0 0 00 1 0 11 0 0 01 1 0 1

a b a b

Example 2 continued…a b GC Sa0@1 Sa0@2 Sa0@3 Sa0@4 Sa1@1 Sa1@2 Sa1@3 Sa1@4

00 00 0 0 0 0 1 1 1 1

01 01 0 0 1 1 1 1 0 0

10 11 1 1 0 1 0 0 1 0

11 10 1 1 1 0 0 0 0 1

1’s show cell that can detect an error

a b GC Sa0@1 Sa0@2 Sa0@3 Sa0@4

01 01 0 0 1 1

10 11 1 1 0 1

11 10 1 1 1 0

Table after test vector 00 was selected

a b GC Sa0@4

01 01 1

10 11 1

Table after test vector

Complete Test set:{00, 11, 10}

This will detect all possible faults in circuit provided all faults are of the type specified by the model. Stuck-at fault model, etc.

Example 2 B, localization

a b GC Sa0@1 Sa0@2 Sa0@3 Sa0@4 Sa1@1 Sa1@2 Sa1@3 Sa1@4

00 00 00 00 00 00 11 10 01 01

01 01 01 01 00 00 10 11 01 01

10 11 00 00 11 10 11 11 10 11

11 10 01 00 11 10 10 10 10 11

T1(00)

b'

a

b

a 1

3 4

2

Example 2 B, localizationSa0@3 Sa1@4

00 01

00 01

11 11

T2

ab GC Sa0@4 Sa1@1 Sa1@2 Sa1@3

00 00 00 11 10 01

01 01 00 10 11 01

10 11 10 11 11 10

T2

|11>

Sa0@1

Sa0@2

|01>

Sa1@4Sa0@3

|10>

Sa0@4

Sa1@1

Sa1@2

|00>

?

01

GC,Sa1@3

00

00

0111

10

10

11

00 01

GC Sa1@3

00 01

GC,Sa1@4, Sa1@1,Sa1@2, Sa1@3

Sa0@3, Sa1@4

T1

T2

T2

T3

ab GC Sa1@3

00 00 01

01 01 01

T3

Compare Scaling Reversible v. Classical

• Small reversible circuits have small gains compared to classical

• Large Classical circuits often cannot be localized, where all reversible circuits can be localized

Reversible scaling

• Each level of a reversible circuit can be partially tested with any test

• A first test will test every C-NOT gates input, output and control half way

Example 2 revisited…

b'

a

b

a 1

3 4

2

Locations for faults

a b GC Sa0@1 Sa0@2 Sa0@3 Sa0@4 Sa1@1 Sa1@2 Sa1@3 Sa1@4

00 00 00 00 00 00 11 10 01 01

01 01 01 01 00 00 10 11 01 01

10 11 00 00 11 10 11 11 10 11

11 10 01 00 11 10 10 10 10 11

So why not two tests!

b'

a

b

a sa0'

0 0 0 00 1 0 11 0 0 01 1 0 1

a b a b

Reversible scaling (cont)

• The best each subsequent test can do is half of what is left.

• Test overlap exists and can lower each successive test’s effectiveness

My Approach

• Path propagation as opposed to fault tables

• The Stuck-at model is incomplete– What about missing gate?– Bridging faults

What’s wrong with fault tables?

• Memory requirements, a non linear increase exists when lines, stages, and or gates are added.

• Good tables may require conditional branch solutions for localization.

Why Path Propagation?

• Dynamic on the fly localization• Circuit can be loaded and testing can be

started immediately.• Can be optimized to find known issues• Capable of providing OTF coverage specs

Path Propagation Example (Step One)

1

1

0

1

1

1

s0

s0

S1

S0

S0 S1 s1

!s0

S0

S0

S0

Path Propagation Example (Step Two)

1

1

0

s0

s0

S1

S0

S0 S1 s1

s0

S0

S1

S0

S00

S10

1s0

s0

S0

S1 S0s1

!

S0

0

1

1

Path Propagation Example (Step Three)

**

s0

**

S0

** ** **

s0

S0

**

**

**

s1

**

0**

s1

S0

0**

s1

S1

0

1

S1

0

1

Note Y-Stuck at 0 stage 1 never tested.And Stuck @ 0 can be missed in case of missing gates

Our Test Set

• 110

• 011

• 001

• 10* to test Y-stuck@0 stage 1

What does this mean?

• The stuck at method can miss errors involving missing gates

• 50% likely to miss, missing gate in stage 1

• Law of diminishing returns, how does it apply here?

Bridging Faults

• In order to truly test bridging across lines one-hot and one-cool versions should be done

• If single fault model used, implied bridging could be attempted

Implied Bridging Technique

• At each connection and or xor two lists of all other lines for 1-0 and 0-1 oppositions

• Percent bridge tested equals– ((tested 1-0) + (tested 0-1)) / (2 * totalnodes)

Thanks!

• As can be seen by the example there are more calculations then what can be done by hand for larger circuits

• Typically there is redundancy in the exhaustive method, this is far to complicated to be seen for people, but computers can remove it. The goal of this method is to remove the useless tests, and focus on the tests that give the most information about the circuit.