JAZiO ™ Incorporated 1 JAZiO ™ Incorporated Incorporated Digital Signal Switching Technology.
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Transcript of JAZiO ™ Incorporated 1 JAZiO ™ Incorporated Incorporated Digital Signal Switching Technology.
JAZiO™ Incorporated1
JAZiOJAZiO™™
IncorporatedIncorporatedwww.JAZiO.comwww.JAZiO.com
Digital Signal Switching Technology
JAZiO™ Incorporated2
What is JAZiO Technology?• A new method of interchip I/O switching
– At high data rate with low latency
– With low power
– At low cost
• Effectiveness is due to using – Differential sensing with a single pin per bit
– Built in timing
– Look for change-of-data first
– Transition detection
JAZiO™ Incorporated3
Traditional Signal Driving(Peak Detection)
All information is transmitted during tRF
(1/3 of bit time)
The rest of the bit time is just wasted!
One bittime
Next bittime
tRF tSU tHD
Sharp Edges Cause:
Ground Bounce!Cross Talk!
Ringing!EMI!
High Power!
JAZiO™ Incorporated4
Pseudo Differential Signal Sensing
Sensing level about1/3 of switching levelThe rest of the switching
level is just wasted!
Large switching levels cause:
Ground Bounce!Cross Talk!
Ringing!High Power!
One bittime
Next bittime
Sensing Level
VREF
SwitchingLevel
0.8V
JAZiO™ Incorporated5
JAZiO Solution
• JAZiO has invented a system which– Achieves very high performance – Has edges which can take the whole bit time– Detects data value as soon as transition occurs– Uses differential sensing with low signal levels– Yet has only 1 pin per data signal
JAZiO™ Incorporated6
What’s the Secret? A Re-think• For each data signal, there is either a change
or no-change from the previous bit time• Traditional systems are good on no-change
but bad on change• JAZiO looks for change first and then
adjusts if no-change occurs• For JAZiO the decision binary is change or
no-change rather than high or low voltage
JAZiO™ Incorporated7
JAZiO Solution
SteeringLogic
DataOutput
VTR
DataInput
VTRB
A Dual Comparators are used
In cases 1 and 6 Comparator A makes a differential comparisonIn cases 2 and 5 Comparator B makes a differential comparisonIn the other four cases Data Input does not change
Data is driven coincidentally with Voltage/Timing References
DataInput
VTR
VTR
One Bit Time
Provide alternating Voltage/Timing References switching at the data rate
Next Bit Time
8 different combinations of VTR and Data Input
712
3
4 8
56
JAZiO™ Incorporated8
Steering Logic
The trick is to know how to select between Comparators A and B and what to do when Data Input does not change
JAZiO™ Incorporated9
Steering Logic
• Generate Steering Logic signals (SL and SL)• Use them with Data Output from previous Bit Time to
select between Comparators A and B
• Also use them for data latching
SL
SL
ReceiverOutput
XORin
inout
XORin
in
out
Data Input
VTR
VTR A
B
VTR
VTR
VTRLatchingSystem
LatchedOutput
JAZiO™ Incorporated10
DataOutput
SL
Initializationor
Receiver Enable
SL
VTR
VTRDataInput
DataInput
XOR
XOR
55 Small Transistors Per BitNo PLL/DLL Required
No die size penalty!!!
JAZiO™ Incorporated11
The receiver cell is: 22um x 55um
(Including routing channels)
The pad cell is: 70um x 80um
JAZiO™ Incorporated12
Time Domain
Decision is made in the Time Domain rather voltage domain
VTR
DataInput
First Look forchange
Determine no-change and
switch toComparator B
0.5V
SL
SL
DataOutput
XORin
inout
XORin
in
out
Data Input
VTR
VTR A
B
VTR
VTR
VTR
JAZiO™ Incorporated13
JAZiO™ Receiver OperationA
SL
SL
XOR-B
DataOutput
in
in
in
inout
out
Data Input
VTR
VTR
B
VTR
VTR
VTR
XOR-A
TheNo-change
Cases
Initialize 0 1 1 0 0 1DataInput
DataOutput
VTRVTR
SL
SL
CompA
CompB
XOR-B
XOR-A
JAZiO™ Incorporated14
Change /No Change ConceptComp A
Data In
VTR VTR
Data In Comp A
No Change
This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.).
3
• Case 3: Comp A remains High past the point of change and the Data Output retains the previous data
• Case 1: Comp A amplifies the change and the data passes through the Steering Logic
Change
1
Change
• The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output
1
THE GAP1
THE GAPTHE GAP BECOMES INFINITE
JAZiO™ Incorporated15
The No-Change Case
But!The handoff from Comparator A to B is smooth since both comparators and Data Output are all high
After the handoff, Comparator Bis ready to make the nextdifferential comparison
Since Comparator A is selected itshigh value causes Data Output to remain high
DataOutput
XOR-B
in
in
in
inout
outXOR-A SL
SL
Comparator A is selected and as the differential on its inputs disappears the outputremains high temporarily
However, Comparator B is gaining a differential and itsOutput becomes a solid high
VTR
DataInput
VTR
B
A
(High)
Bit Time
But eventually the SLs will switch causing the XORs to switch and Comparator B will be selected
JAZiO™ Incorporated16
vtr
Data Input
xnora Xnorb
Data Output
Time (nS)4 5 6
0
1
1.8
Vol
tage
(V
)
4nH Package
Break-Before-Make (Break-And-Remake)
JAZiO™ Incorporated17
Data Skew at Receiver
Simulations show that width of Skew Band can be up to 40% of bit time
VTR
DataInput
500mV+ 100mV
- 150mV RecommendedSkew band
1.25V/ns
Bit time = 0.5ns
JAZiO™ Incorporated18
data_in0
vtr
sl slb
vtrb
data_out 0
SIG
NA
LS
F
RO
M
PA
DS
xora
xora
xorb
xora
xorb
xora xo
rb
xorb
data_in1 data_in2 data_in3
data_out 1 data_out2 data_out 3
4 Bit JAZiO Receiver From Test Chip
JAZiO™ Incorporated19
4-bitJAZiO Receiver
4-bitJAZiO Receiver
4-bitJAZiO Receiver
4-bitJAZiO Receiver
4 of 16Serial to Parallel
4 of 16Serial to Parallel
4 of 16Serial to Parallel
4 of 16Serial to Parallel
Latch (latching at ¼ the data rate)
data
_in
0
data
_in
1
data
_in
2
data
_in
3
data
_in
4
data
_in
5
data
_in
6
data
_in
7
data
_in
8
data
_in
9
data
_in
10
data
_in
11
data
_in
12
data
_in
13
data
_in
14
data
_in
15vtr
vtrb
16 JAZiO™ Receivers From Test Chip
JAZiO™ Incorporated20
Transition Detection• Higher frequency components, above the
maximum operating frequency, can be filtered out at the receiver.
• Narrower voltage band for differential amplifier operation (300mV).
• Self aligned data and VTRs shifts the steering logic time, latching window and change/no-change gap in real time relative to Vcc, temperature, manufacturing variations.
Transition Detection
Pseudo Differential Peak Detection
• Frequency components higher than the maximum frequency need to be present at the receiver (setup and hold time at VOH/VOL).
• Wider voltage band for differential amplifier operation is required (600mV).
• Vref is a voltage average (Vcc, temperature and manufacturing, and noise).
• Clock is a time average based on PLL/DLL.
VrefBand
VH
VL
600mVDiff Amp
Band300mV
Diff AmpBand
JAZiO™ Incorporated21
2nH Package & ESD Model
Low Pass Filter
0.6pf
1nH 0.24
Lead frame
0.6pf
1nH 0.2
Bond Wire
1pf
N-Ch Clamp
P-Ch Clamp
0.1pf
Pad0.1pf
200
Cint
ToReceiver
Input Protection Resistor
JAZiO™ Incorporated22
Simulation at 2Gb/s
Middle of transmission line Package inductance 2nH
Data Output
VTR
Data Input
Time (nS)5 6 7 8 9
0
1
1.8
Vol
tage
(V
)
Data Output
VTR
Data Input
Time (nS)5 6 7 8 9
0
1
1.8
Vol
tage
(V
)
At Pin
AtReceiver
Input
JAZiO™ Incorporated23
Data Rate vs Slew Rate Comparison
• Slower edges
• Lower switching levels
• Reduced slew rate
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Slew Rate (V/nS)
Dat
a R
ate
per
Pin
(b
/S)
10M
100M
1G
10G
EDO-33
SDRAM-66
SDRAM-100 DDR
RDRAM
JAZiO™
JAZiO™
JAZiO™
Better
Higher Performance at Lower Power with Higher Robustness
JAZiO™ Incorporated24
VTTVTT
Signal
VTR
VTTVTT
Signal
VREF
1. VSSQ noise between signal and VREF2. VTT noise and/or VTT mismatch on either end3. VREF impedance to Signal impedance mismatch
JAZiO Is Entirely Common-Mode
JAZiO
Pseudo Differential
JAZiO™ Incorporated25
Applying JAZiO Technology• JAZiO is the physical I/O layer only
– JAZiO provides no protocol– Works with any protocol– Like steel belted radial tires that work for Honda Civic,
Ferrari Sports Car, or Ford Explorer
• Easy to use– No die size penalty– No PLL/DLL or special semiconductor technology– Low Power
• Can be used anywhere that fast switching or low power is useful
JAZiO™ Incorporated26
JAZiO for DRAM• JAZiO Technology can be applied to
scaled-up versions of existing protocols like DDR or RDRAM
• Or new protocols can be developed to match JAZiO’s low latency and high bandwidth to reduce pins and increase parallelism
JAZiO™ Incorporated27
16-WideMP Server
L3
BSB
CONTROLLER
FSB
CPU
1GHz CPU
I/O
DRAM
2GHz Data Rate
Quad Processor Module
Quad Processor Module
Quad Processor Module
2GHz Interprocessor
Communication (Scalable to 4GHz)
Quad Processor Module
CPU
L3
CPU
L3
CPU
L3with 2GHz FSB & BSB
All scalable to 2x
frequencies
JAZiO™ Incorporated28
Notebook / Internet Appliance
Pavg = K•v•VTT K (Cf+1/Rt)
Therefore
Power Ratio = (0.5v•1)/(0.8v•1.8) When compared to existing pseudo differential with VTT=1.8v, VLOW=1.0v, similar
load capacitance, operating frequency and termination resistance
Small swing and slower transition time reduces
EMI allowing it to meet FCC limits for radiation
SOC DRAM
Power consumed in the memory interface is reduced due to low
switching levels of VTT=1.0v and VLOW=0.5v
JAZiO™
JAZiO™ Incorporated29
How Can JAZiO Be Used?• JAZiO is “essentially” an Open Standard• All technology is publicly visible w/o NDA• Anyone can see it, study it, simulate it, design it in,
build test chips, build prototypes, etc• Just don’t sell products without licensing it• A JAZiO demonstration chip has been designed by
Micro Magic, Inc – a JAZiO Design Services partner (www.micromagic.com)
JAZiO™ Incorporated30
Conclusion• JAZiO uses lower levels and slower edges• Achieves high performance, low power, high
robustness• JAZiO technology is fundamentally different from
traditional methods– Transition Detection rather than Peak Detection– Time domain rather than voltage domain– Look for change first– Change vs No-change rather than High or Low
• JAZiO is available to everyone at low cost and applies to any application