Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 8 Optimizing Power @ Standby Circuits and...
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Transcript of Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 8 Optimizing Power @ Standby Circuits and...
Jan M. Rabaey
Low Power Design Essentials ©2008 Chapter 8
Optimizing Power @ Standby
Circuits and Systems
Low Power Design Essentials ©2008 8.2
Chapter Outline
Why Sleep Mode Management? Dynamic power in standby
– Clock gating Static power in standby
– Transistor sizing– Power gating– Body biasing– Supply voltage ramping
Low Power Design Essentials ©2008 8.3
Arguments for Sleep Mode Management
Many computational applications operate in burst modes, interchanging active and non-active modes– General purposes computers, cell phones, interfaces,
embedded processors, consumer applications, … Prime concept: Power dissipation in standby should
absolutely minimum, if not zero Sleep mode management has gained importance with
increasing leakage
Fixed Activity
Variable Activity
No Activity - Standby
ActiveDesign Time Run Time
Static
Clock gating
Leakageelimination
Low Power Design Essentials ©2008 8.4
Standby Power - Was Not A Concern In Earlier Days
Pentium-1: 15 Watt (5V - 66MHz)Pentium-2: 8 Watt (3.3V- 133 MHz)
Floating Point Unit and Cache powered down when not in use
Processor in idle mode!
[Source: Intel]
Low Power Design Essentials ©2008 8.5
Dynamic Power - Clock Gating
Turn off clocks to idle modules– Ensure that spurious activity is set to zero
Must ensure that data inputs to module are in stable mode – Primary inputs are from gated latches or
registers– Or, disconnected from interconnect network
Can be done at different levels of system hierarchy
Low Power Design Essentials ©2008 8.6
Clock Gating
Turning off the clock for non-active components
Register File
Logic Module
Clk
Enable
Logic Module
Enable
Bus
Disconnecting the inputs
Low Power Design Essentials ©2008 8.7
DSP/HIF
DEU
MIF
VDE
896Kb SRAM
10
8.5mW
0 155
30.6mW
20 25
Without clock gating
With clock gating
Power [mW]
Clock-gating Efficiently Reduces Power
[Ref: M. Ohashi, ISSCC’02]
90% of F/F’s clock-gated.
70% power reduction by clock-gating alone.
MPEG4 decoder
© IEEE 2002
Low Power Design Essentials ©2008 8.8
Clock Gating
Challenges to skew management and clock distribution (load on clock network varies dynamically)
Fortunately state-of-the-art design tools are starting to do a better job– For example, physically aware clock-gating inserts gaters in clock-tree
based on timing constraints and physical layout
CG
CG
CG
CG
CG
Simpler skew management, less areaPower savings
Low Power Design Essentials ©2008 8.9
Clock Hierarchy and Clock Gating
Example: Clock distribution of dual-core Intel Montecito processor
“Gaters” provided at lower clock tree levelsAutomatic skew compensation
[Ref: T. Fischer, ISSCC’05]
© IEEE 2005
Low Power Design Essentials ©2008 8.10
Trade-Off between Sleep-Modes and Sleep-Time
Active modenormal processing
Standby modefast resume
high passive power
Typical operation modes
Sleep modeslower resume
low passive power
Resume time from clock gating determined by the time it takes to turn on the clock distribution network Standby Options:
Just gate the clock to the module in question Turn off phased-locked loop(s) Turn off clock completely
Low Power Design Essentials ©2008 8.11
Sleep Modes in mProcessors and mControllers
[Ref: S. Gary, Springer’95]
[Ref: TI’06]
• 0.1-μA power down• 0.8-μA standby• 250-μA / MIPS @ 3
V
TI MSP430™From standby to active in 1 ms Using dual clock system
Low Power Design Essentials ©2008 8.12
The Standby Design Exploration Space
Standby Power
Wak
e-up
Del
ay
Standby
Sleep
Nap
Doze
Trade-off between different operational modesShould blend smoothly with run-time optimizations
Low Power Design Essentials ©2008 8.13
Also the Case for Peripheral Devices
[Ref: T. Simunic, Kluwer’02]
TX RX Doze Off
Power 1.65W 1.4W 0.045W 0 W
Transitions To Off:62 msec
To Doze:34 msec
Wireless LAN Card
Hard diskPsleepW
PactiveW
Tsleepsec
Tactivesec
IBM 0.75 3.48 0.51 6.97
Fujitsu 0.13 0.95 0.67 1.61
Low Power Design Essentials ©2008 8.14
The Leakage Challenge – Power in Standby
With clock-gating employed in most designs, leakage power has become the dominant standby power source
With no activity in module, leakage power should be minimized as well– Remember constant ratio between dynamic
and static power … Challenge – how to disable unit most
effectively given that no ideal switches are available
Low Power Design Essentials ©2008 8.15
Standby Static Power Reduction Approaches
Transistor stacking Power gating Body biasing Supply voltage ramping
Low Power Design Essentials ©2008 8.16
Transistor Stacking
Off-current reduced in complex gates (see leakage power reduction @ design time)
Some input patterns more effective than others in reducing leakage
Effective standby power reduction strategy:– Select input pattern that minimizes leakage current of
combinational logic module– Force inputs of module to correspond to that pattern
during standby
Pro’s: Little overhead, fast transition Con: Limited effectiveness
Low Power Design Essentials ©2008 8.17
Transistor Stacking
Combinational Module
Lat
ches
Lat
ches
… …Clk Standby
[Ref: S. Narendra, ISLPED’01]
Low Power Design Essentials ©2008 8.18
Forced Transistor Stacking
[Ref: S. Narendra, ISLPED’01]
Useful for reducing leakage in non-critical shallow gates(in addition to high VTH)
Low Power Design Essentials ©2008 8.19
Power Gating
[Ref: T. Sakata, VLSI’93; S. Mutoh, ASIC’93]
Disconnect module from supply rail(s) during standby
Footer or header transistor, or both Most effective when high VT transistors
are available Easily introduced in standard design
flows But … Impact on performance
Very often called “MTCMOS” (when using high- and low- threshold devices)
Logic
sleep
sleep
Low Power Design Essentials ©2008 8.20
Power Gating ─ Concept
Leakage current reduces because Increased resistance in leakage path Stacking effect introduces source
biasing
(similar effect at PMOS side)
IN (= 0)
VDD
OUT
VS = Ileak RS
RSSleep
IN = 0
M1
VS
Ileak
RS
M1
VTH shift
Extra resistance
Low Power Design Essentials ©2008 8.21
Power Gating Options
Low VT
sleep
sleep
Low VT
sleep
Low VT
sleep
footer + header footer only header only
NMOS sleeper transistor more area efficient than PMOS Leakage reduction more effective (under all input patterns)
when both footer and header transistors are present
Low Power Design Essentials ©2008 8.22
Other option: Boosted-Gate MOS (BGMOS)
Leak cut-off Switch (LS) - high VTH
- thick TOX
(eliminates tunneling)
VDD
Virtual GND
CMOS logic - low VTH
- thin TOX
[T. Inukai, CICC'00]
0VVDD
VBOOST
<Standby> <Active>
Low Power Design Essentials ©2008 8.23
Other Option: Boosted-Sleep MOS
Leak cut-off Switch (LS) - normal (or high) VTH
- normal TOX
Area efficient
VDD
Virtual GND
CMOS logic - low VTH
- thin TOX
[Ref: T. Inukai, CICC’00]
-Vboost
0VDD
<Standby> <Active>
(also called Super-Cutoff CMOS or SCCMOS)
Low Power Design Essentials ©2008 8.24
Virtual Supplies
ON
...
VDD
Virtual VDD
GND
Virtual GND
ON
[Ref: J. Tschanz, JSSC’03]
...
VDD
Virtual VDD
Virtual GND
OFF
OFFGND
Virtual supply collapse
Active Mode Standby Mode
Noise on virtual supplies
© IEEE 2003
Low Power Design Essentials ©2008 8.25
Decoupling Capacitor Placement
Oxide leakage
Logic
Performance
Convergence time
Oxide leakage savings
[Ref: J. Tschanz, JSSC’03]
Reduced leakage
Longer time
constant
Logic
Decap on supply rails Decap on virtual rails
© IEEE 2003
Low Power Design Essentials ©2008 8.26
Leakage Power Savings versus Decap
Idle time
10ns 1ms 100ms 10ms10msNo
rmal
ized
lea
kag
e p
ow
er
in id
le
mo
de
90%
40%
Low-leakage 133nF decap on
virtual VCC
No decap on virtual VCC
[Ref: J. Tschanz, JSSC’03]
0
0.2
0.4
0.6
0.8
1
1.32V75°C
© IEEE 2003
Low Power Design Essentials ©2008 8.27
How to Size the Sleep Transistor?
Sleep transistor is not free – it will degrade the performance in active mode
Circuits in active mode see the sleep transistor as extra power line resistance– The wider the sleep transistor, the better
Wide sleep transistors cost area– Minimize the size of the sleep transistor for given
ripple (e.g. 5%)– Need to find the worst-case vector
Low Power Design Essentials ©2008 8.28
Sleep Transistor Sizing
High-VTH transistor must be very large for low resistancein linear region.
Low-VTH transistor needs less areafor same resistance.
[Ref: R. Krishnamurthy, ESSCIRC’02]
MTCMOS Boosted Sleep
Non-Boosted Sleep
Sleep-TRsize 5.1% 2.3% 3.2%
Leakage power reduction
1450x 3130x 11.5x
Virtual supply bounce
60 mV 59 mV 58 mV
Low Power Design Essentials ©2008 8.29
Preserving State
Virtual supply collapse in sleep mode causes the loss of state in registers
Keeping the registers at nominal VDD preserves the state– These registers leak …
Can lower the VDD in sleep– Some impact on robustness, noise and soft-
error immunity
Low Power Design Essentials ©2008 8.30 [Ref: S. Mutoh, JSSC’95]
Latch Retaining State during Sleep
Clk
sleep sleep
sleep sleep
D Q
Black-shaded devices use low-VTH tranistorsAll others are high VTH.
Transmission gate
Low Power Design Essentials ©2008 8.31
MTCMOS Derivatives Preventing State Loss
low VTH
logic
sleep
VDD
virtual VDD
High VTH
(small W)HVT
Vretain
RetentionClamping
low VTH
logic
sleep
virtual GND
High VTH
VDD
Reduce voltage and retain state
Low Power Design Essentials ©2008 8.32
Sleep Transistor Placement
No sleep transistors
Standard cell row“strapper”
cells
VDD
GND
GNDVDD
VDD’
GND’
GNDVDD
VDD’
GND’
With headers and footers
M4
M3
M3
M4
Low Power Design Essentials ©2008 8.33
Sleep Transistor Layout
Sleep transistor
cells
ALU
Area overhead
PMOS 6%
NMOS 3%
[Ref: J. Tschanz, JSSC’03]
Low Power Design Essentials ©2008 8.34
Dynamic Body Biasing
Increase thresholds of transistors during sleep using reverse body biasing – Can be combined with forward body biasing in active
No delay penaltyBut Requires triple-well technology Limited range of threshold adjustments (<100mV)
– Not improving with technology scaling Limited leakage reduction (<10x) Energy cost of charging/discharging the substrate
capacitance
Low Power Design Essentials ©2008 8.35
Dynamic Body Biasing
... ...
FBB
FBB
VDD
GND
PMOS body
NMOS body
PMOS bias
NMOS bias
PMOS bias
... ...NMOS
bias
RBB
RBB
VDD
GND
PMOS body
NMOS body
VHIGH
VLOW
Active mode: Forward Body Bias Standby mode: Reverse Body Bias
[Ref’s: T Kuroda ISSCC’96; J. Tschanz, JSSC’03]
Low threshold, high performance High threshold, low leakage
Can also be used to compensate for threshold variations
© IEEE 2003
Low Power Design Essentials ©2008 8.36
The Dynamics of Dynamic Body Bias
[Ref: K. Seta, ISSCC’95]
Needs level shifting and voltage-switch circuitry
© IEEE 1995
Low Power Design Essentials ©2008 8.37
Body Bias Layout
Sleep transistor LBGs
Number of ALU core LBGs 30
Number of sleep transistor LBGs
10
PMOS device width 13 mm
Area overhead 8%
ALU core LBGs
Sleep transistor LBGs
ALU core LBGs
ALU
[Ref: J. Tschanz, JSSC’03]
LBG: Local bias generator
Low Power Design Essentials ©2008 8.38
DBB for Standby Leakage Reduction - Example
Application-specific processor(SH-mobile)
250 nm technology core at 1.8 V I/O at 3.3 V 3.3M transistors
[Ref: M. Miyazaki, Springer’06]
© Springer 2006
VBC (0.13 mm2)
Low Power Design Essentials ©2008 8.39
Effectiveness of Dynamic Body Biasing
0
0.1
0.2
0.3
0.4
0.5
0.6
-2 -1 0 1 2
VBS (V)
VT
H (
V)
Reversed VBS
Forward VBS
Practical VTH tuning range less than 150 mV in 90 nm technology
Low Power Design Essentials ©2008 8.40
Supply Voltage Ramping (SVR)
Reduce supply voltage of modules in sleep mode – Can go to 0 V if no state retention is necessary– Down to state retention voltage otherwise,
(see Memory in next Chapter), or move state to persistent memory before power-down
Most effective leakage reduction technique– Reduces current and voltage
But Needs controllable voltage regulator
– Becoming more often present in modern integrated system designs Longer re-activation time
Simplified version switches between VDD and GND (or VDDL)
[Ref: M. Sheets, VLSI’06]
Low Power Design Essentials ©2008 8.41
Supply Ramping
Standby power = VDD(standby) x Ileak(standby)
Modules must be isolated from neighbors Creating “voltage islands”
Module
0
VDD
Module
DRV
VDD
Full power down Power down with data retention
Low Power Design Essentials ©2008 8.42
Supply Ramping ─ Impact
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
0.5
1
1.5
2
2.5
3
3.5
4x 10
-9
VDD
Ple
ak
Leakage power as a function of the supply voltage (90 nm)
Factor 8.5
Inverter
Nand4
Because of DIBL, dropping supply voltage causes dramatic reduction in leakage – Can go as low as 300 mV before data retention is lost
Low Power Design Essentials ©2008 8.43
Integration in Standard Cell Layout Methodology
Power switch cell easily incorporated into standard design flow
– Cell has same pitch as existing components– No changes required to cell library from foundry
Switch design can be independent of block size
Vvdd
GND
VDDH VDDL (RV)
Awake
Awake_buf
Vvdd
GND
Vvdd
GND
Vvdd
GND
VD
DH
GN
DV
DD
L
Power switch cell Integration into power grid
VD
DH
GN
DV
DD
L
VD
DH
GN
DV
DD
L
Low Power Design Essentials ©2008 8.44
Standby Leakage Management ─ A Comparison
Transistor Stacking
Power Gating Dynamic Body Biasing
Supply Voltage Ramping
Pro’s Conventional technology No performance impact
Conventional technology Conceptually simple Most effective
Reuse of standard designs No performance impact
Most effective Also available in switched version
Con’s Limited impact Special registers
Performance impact of serial transistor Changes in design flow
Triple well Slow activation Does not fare well with technology scaling
Needs voltage regulator or extra rails Slow activation
PotentialSavings
5 - 10 2 - 40 2 - 1000 Huge
Low Power Design Essentials ©2008 8.45
Some Long-Term Musings
Ideal power-off switch should have zero leakage current (S = 0 mV/decade)
Hard to accomplish with traditional electronic devices Maybe possible using MEMS – mechanical switches
have a long standing reputation for good isolation
[Ref: N. Abele, IEDM’05]
Low Power Design Essentials ©2008 8.46
Summary and Perspectives
Today’s designs are not leaky enough to be truly power-performance optimal! Yet, when not switching, circuits should not leak!
Clock gating effectively eliminates dynamic power in standby
Effective standby power management techniques are essential in sub-100 nm design– Power gating the most popular and effective technique– Can be supplemented with body biasing and transistor stacking– Voltage ramping probably the most effective technique in the
long range (if gate leakage becomes a bigger factor)
Emergence of “voltage or power” domains
Low Power Design Essentials ©2008 8.47
References
Books and Book Chapters V. De et al, “Techniques for Leakage Power Reduction,” in A. Chandrakasan et al, Design of
High-Performance Microprocessor Circuits, Ch. 3, IEEE Press, 2001. K. Roy et al, “Circuit Techniques for Leakage Reduction,” in C. Piguet, Low-Power Electronics
Design, Ch. 13, CRC Press, 2005. S. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Springer , 2006.
Articles Abele, N.; Fritschi, R.; Boucart, K.; Casset, F.; Ancey, P.; Ionescu, A.M., “Suspended-gate
MOSFET: bringing new MEMS functionality into solid-state MOS transistor,” Proc. Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp 479-481, Dec. 2005
T. Fischer, et al., “A 90-nm variable frequency clock system for a power-managed Itanium® architecture processor,” IEEE J. Solid-State Circuits, pp.217–227, Febr. 2006.
S. Gary, “Low-Power Microprocessor Design,” in Low Power Design Methodologies, Ed. J. Rabaey and M. Pedram, Chapter 9, pp. 255-288, Kluwer Academic, 1995.
T. Inukai et al., “Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration,” CICC, pp. 409-412, May 2000.
H. Kam et al., “A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics, “ IEDM Tech. Digest, pp. 463- 466, Dec. 2005.
R. Krishnamurthy et al, “High-performance and low-power challenges for sub-70nm microprocessor circuits,” 2002 IEEE ESSCIRC Conf., pp. 315-321, Sept. 2002.
T.Kuroda et al., “A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme,” JSSC, vol. 31, no. 11, pp. 1770-1779, Nov. 1996.
Low Power Design Essentials ©2008 8.48
References (cntd)
M. Miyazaki et al., “Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors”, in A. Narendra, Leakage in Nanometer CMOS Technologies, Ch 10., Springer, 2006.
S. Mutoh et al., 1V high-speed digital circuit technology with 0.5 mm multi-threshold CMOS,“ Proc. Sixth Annual IEEE ASIC Conference and Exhibit, pp. 186-189, Sept. 1993.
S. Mutoh et al., “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS”, IEEE Journal of Solid-State Circuits, vol. 30, pp. 847 - 854, August 1995.
S. Narendra, et al., “Scaling of Stack Effect and its Application for Leakage Reduction,” ISLPED, pp. 195-200, Aug. 2001.
M. Ohashi et al, “A 27MHz 11.1mW MPEG-4 Video Decoder LSI for Mobile Application,” ISSCC, pp. 366-367, Feb. 2002.
T. Sakata, M. Horiguchi, K. Itoh; Subthreshold-current reduction circuits for multi-gigabit DRAM's, Symp. VLSI Circuits Dig. , pp. 45 - 46, May 1993.
K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, "50% active-power saving without speed degradation using standby power reduction (SPR) circuit," IEEE International Solid-State Circuits Conference, vol. XXXVIII, pp. 318 - 319, February 1995.
M. Sheets et al, J, "A Power-Managed Protocol Processor for Wireless Sensor Networks," Digest of Technical Papers 2006 Symposium on VLSI Circuits, pp. 212-213, June 15-17, 2006.
T. Simunic, "Dynamic Management of Power Consumption", in Power Aware Computing, edited by R. Graybill, R. Melhem, Kluwer Academic Publishers, 2002.
TI MSP430 Microcontroller family, http://focus.ti.com/lit/ml/slab034m/slab034m.pdf J. W. Tschanz, S. G. Narendra, Y. Ye, B. A. Bloechel, S. Borkar, and V. De, "Dynamic sleep
transistor and body bias for active leakage power control of microprocessors," IEEE Journal of Solid-State Circuits, vol. 38, pp. 1838 - 1845, November 2003.