Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin...
-
date post
20-Dec-2015 -
Category
Documents
-
view
213 -
download
1
Transcript of Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin...
![Page 1: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/1.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 1
Spectral RTL Test Generation for Microprocessors
Nitin Yogi and Vishwani D. AgrawalAuburn UniversityDepartment of ECE
Auburn, AL 36849, USA
![Page 2: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/2.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 2
Outline
Microprocessor testing Issues Problem and Approach RTL faults Spectral analysis & test generation Test set compaction RTL DFT Experimental Results Conclusion
![Page 3: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/3.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 3
Microprocessor Testing Issues
Issues arising from Increased Design Complexity Increased Test Generation Complexity
Viable Test Method: RTL test generation Advantages:
Low testing complexity Early detection of testability issues
Increased Demands on Testing Viable Test Method: Functional at-speed tests Advantages:
Better defect coverage Detection of delay faults
![Page 4: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/4.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 4
Problem and Approach
The problem is … Develop an RTL-based ATPG method to
generate functional at-speed tests. And our approach is …
Circuit characterization using RTL: RTL test generation Analysis of information content and noise in RTL
vectors. Test generation for gate-level implementation:
Generation of spectral vectors Fault simulation and vector compaction
![Page 5: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/5.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 5
Faults Modeled for an RTL Module
CombinationalLogic
FF
FF
Inputs Outputs
RTL stuck-at fault sites
A circuit is an interconnect of several RTL modules.
![Page 6: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/6.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 6
Walsh Functions and Hadamard Spectrum
1 1 1 1 1 1 1 11 -1 1 -1 1 -1 1 -11 1 -1 -1 1 1 -1 -11 -1 -1 1 1 -1 -1 11 1 1 1 -1 -1 -1 -11 -1 1 -1 -1 1 -1 11 1 -1 -1 -1 -1 1 11 -1 -1 1 -1 1 1 -1
H8 =
w0
w1
w2
w3
w4
w5
w6
w7
Wal
sh f
unct
ions
(or
der
8)
• Walsh functions form an orthogonal and complete set of basis functions that can represent any arbitrary bit-stream.
• Walsh functions are the rows of the Hadamard matrix.
• Example of Hadamard matrix of order 8:
![Page 7: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/7.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 7
Analyzing Bit-Streams
0 to -1
Bit-stream
Vector 1Vector 2
.
.
.
Inp
ut
1
Inp
ut
2
. . .
Bit-stream ofInput 2
![Page 8: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/8.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 8
Spectral Characterization of a Bit-Stream
Bit stream to analyze
Correlating with Walsh functions by multiplying with Hadamard matrix.
Essential component (others regarded noise)
Hadamard Matrix
Bit stream
Spectral coeffs.
![Page 9: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/9.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 9
Generation of New Bit-Streams
Perturbation
Generation of new bit-stream by multiplying with Hadamard matrix
Spectral components
Essential component
retained; noise components
randomly perturbed
New bit stream
Bits changed
Sign function
-1 to 0
![Page 10: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/10.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 10
PARWAN Processor
Reference: Z. Navabi, Analysis and Modeling of Digital Systems. New York: McGraw-Hill, 1993.
![Page 11: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/11.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 11
Power Spectrum for “Interrupt” Bit-Stream
Spectral Coefficients
Nor
mal
ized
Pow
er
Essential components
Some noise components
Randomlevel
(1/128)
Analysis of 128 test vectors.
![Page 12: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/12.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 12
Power Spectrum for “DataIn[5]” Signal
Theoretical random noise
level(1/128)
Nor
mal
ized
Pow
er
Spectral Coefficients
Some essential
components
Some noise components
Analysis of 128 test vectors.
![Page 13: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/13.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 13
Power Spectrum for Random SignalN
orm
aliz
ed P
ower
Theoretical random noise
level(1/128)
Spectral Coefficients
Analysis of 128 random vectors.
![Page 14: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/14.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 14
Selecting Minimal Vector Sequences Using ILP
Fault simulation of new sequences A set of perturbation vector sequences {V1, V2, .. , VM} is
generated. Vector sequences are simulated and all gate-level faults
detected by each are obtained. Compaction problem
Find minimum set of vector sequences that cover all detected faults.
Minimize Count{V1, … ,VM} to obtain compressed seq. {V1,… ,VC}, where {V1, … ,VC} {V1, … , VM}, and Fault Coverage{V1, … ,VC} = Fault Coverage{V1, … ,VM}
Compaction problem is formulated as an Integer Linear Program (ILP) [1].
[1] P. Drineas and Y. Makris, “Independent Test Sequence Compaction through Integer Programming," Proc. ICCD’03, pp. 380-386.
![Page 15: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/15.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 15
RTL DFT Goals of DFT:
Improve controllability and observability Most hard-to-detect faults were experimentally found to
have poor observability XOR tree as DFT
Low area overhead Low performance penalty Hard-to-detect RTL faults used for observation test points 10 observation test points selected
Hard-to-detect RTL faults
To test output
XOR tree
![Page 16: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/16.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 16
Experimental Results
No of RTL Faults
No. of vectors
CPU (s) RTL coverage (%)
Gate-level fault
coverage(%)
737 134 640 96.30% 81.22%
RTL characterization
PARWAN processor
![Page 17: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/17.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 17
Experimental Results
Gate-level Fault Coverage
Circuit
RTL Spectral ATPG*Gate-level ATPG*
(FlexTest)Random vecs.
Cov. (%)
No. of vecs.
CPU (secs)
Cov. (%)
No. of vecs.
CPU (secs)
Cov. (%)
No. of vecs.
Parwan 98.23% 2327 2442 93.40% 1403 26430 80.95% 2814
Parwan (with DFT)
98.77% 1966 2442 95.78% 1619 20408 87.09% 2948
*Sun Ultra 5, 256MB RAM
![Page 18: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/18.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 18
Experimental Results
Parwan processor
0
20
40
60
80
100
1 10 100 1000 10000
No. of vectors
Te
st
co
ve
rag
e (
%)
RTL spectralATPG
Gate-levelATPG
Randomvectors
RTL faultvectors
![Page 19: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/19.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 19
Experimental Results
Parwan processor (with DFT)
0
20
40
60
80
100
1 10 100 1000 10000
No. of vectors
Te
st
co
ve
rag
e (
%)
RTL spectralATPG
Gate-levelATPG
Randomvectors
RTL faultvectors
![Page 20: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/20.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 20
Conclusion
Spectral RTL ATPG technique applied to PARWAN processor.
Proposed ATPG method provides: Good quality “almost” functional at-speed tests Lower test generation complexity Enables testability appraisal at RTL
RTL based XOR tree as DFT was found to improve results.
An alternative approach: Use functional vectors instead of RTL vectors. Yogi and Agrawal, “Spectral Characterization of Functional
Vcetors for Gate-Level Fault Coverage Tests,” Proc. VDAT, August 2006
![Page 21: Jan. 9, 2007 VLSI Design Conference 20071 Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.](https://reader030.fdocuments.us/reader030/viewer/2022032800/56649d4d5503460f94a2b3d8/html5/thumbnails/21.jpg)
Jan. 9, 2007 VLSI Design Conference 2007 21
Thank You !
Questions ?