Ivo Bolsens Xilinx Research Labs

Xilinx Confidential

Mission Statement

• Invent and discover technologies that create new business opportunities

• Track the external state-of-the-art and advise on the strategic implications of new technology

• Ensure that relevant internally- and externally-developed technology becomes a part of Xilinx's practice and products

• Participate in R&D reviews, assist in product evaluations, and consult with all parts of Xilinx on issues related to technology

• Demonstrate to the technical and business communities that Xilinx is the technological leader in its space, is committed to remaining the leader, and controls its own technological destiny

Xilinx Confidential

Research Programs

Multimedia NetworkingDig Com

System Capture

Low Power

Reconfigurable

Xilinx Confidential

Systems &Applications

• Advance, capture observations about – limitations of existing architectures– suggestions for new architectural features, memory hierarchy etc.– requirements for tools to support mixed HW/SW design flow, dynamic

reconfiguration etc

• Understand and influence the relationship between algorithms, architecture and design methodology in selected leading-edge application domains :– DSP (image processing, soft radio) and Network processing

• Facilitate research into design technology at ever increasing levels of abstraction.

• Develop complex demonstration vehicles for use in evaluating new design

methodologies and hardware architectures.

Xilinx Confidential

Design Technology

deliver innovative design methodologies, flows and tools

in partnership with the product divisions

that give Xilinx customers best-in-class solutions to their design challenges

Xilinx Confidential

FPGA’s are ahead of the curve

SIA Roadmap Xilinx

Pro

cess

Tec

hn

olog

y F

eatu

re S

ize

(nm

)

Year

350

250

180

150130

100

70

97 98 99 00 01 02 03 04 05

Cu/Low-K

Virtex-II FPGA to Market 1-Year Earlier

Xilinx is developing 90nm in 2002Xilinx is developing 90nm in 2002

Xilinx Confidential

A Decade of Progress

1

10

100

1000

1/91 1/92 1/93 1/94 1/95 1/96 1/97 1/98 1/99 1/00 1/01

Year

CapacitySpeedPrice Virtex &

Virtex-E(excl. Block RAM)

XC4000

100x

10x

1x

Spartan

1000x

Virtex-II(excl. Block RAM)

Xilinx Confidential

The Cost/Volume Crossover

Unit Volume

Rel

ativ

e C

ost

0.1

1

10

100

1000

10 100 1,000 10,000 100,000 1,000K

ASIC Cost

FPGA Cost

Xilinx Confidential

Time

Electronics Industry Dynamics

Cable Decoders

Custom Features

(Pay-Per-View)

DigitalVCR

Satellite/Cable+ Digital

VCR

Residential Gateway(Broadband access)

Mar

ket

Siz

e ($

)

NTSC

NTSCSmart cards

(DES)

NTSCDES

ATAPI

NTSCDES

ATAPIDBS

DOCSIS

NTSCDES

ATAPIDBS

DOCSISHomePNAHomeRF

HomePLUGBluetoothHiperlan2

DSL...

Dramatic increasein new

standards

• New Products– Take less time to reach high volumes– Shorter Product Life Cycles– Many standards / More Interoperability

Xilinx Confidential

Simpler/Faster Design Flows

• 2:1 proven Time-to-Market Advantage• No silicon design or verification steps• More design flexibility through later design

freeze

SpecASICASICFlowFlow

DesignDesignFreezeFreeze

Design andVerification

SiliconPrototype

SystemIntegration

SiliconProduction

SpecFPGAFPGAFlowFlow

DesignDesignFreezeFreeze

Design andVerification

SystemIntegration

Xilinx Confidential

Today’s Product Lifecycle

• 37% of new digital products were late to market• Entering the market first can result in up to a 40% greater total

profit contribution over the product’s life vs. the #2 entrant

Reduced profit Reduced profit for latecomersfor latecomers

Profit for first Profit for first to Marketto MarketProfit

Time

Xilinx Confidential

Today’s Product Lifecycle

• 37% of new digital products were late to market• Entering the market first can result in up to a 40% greater total

profit contribution over the product’s life vs. the #2 entrant

IRL extendsIRL extendsproduct life in marketproduct life in marketProfit

Time

Xilinx Confidential

PPC PPC

Virtex-II Pro PowerPC Technology

• 32-bit RISC CPU, Harvard Architecture• 130nm CMOS with 1.5V Operation• 456 Dhrystone MIPS at 300MHz• 32 x 32-bit General Purpose Registers• Hardware Multiply / Divide• 5-Stage Execution Pipeline• 16KB D-Cache, 16KB I-Cache• Memory Management Unit (MMU)• High-Bandwidth Interface to Logic• Built-In Hardware Timers• Built-In JTAG Debug and Trace support

IBM PowerPC™ 405 RISC CPU

I-Cache16KB

I-Cache16KB MMU

Fetch & Decode

Timers and

Debug Logic

Execution Unit32x32b GPRALU, MAC

Execution Unit32x32b GPRALU, MAC

D-Cache16KB

D-Cache16KB

3.8 sq mm = 1% of 2VP100

Xilinx Confidential

High Performance

400

800

1600

200

100

Virtex-II ProPowerPC 405

456

912

1824

AlteraExcalibur

Arm 9

220

Dh

ryst

on

e M

IPS

1 C

PU 2 C

PU

s 4 C

PU

s

Xilinx Confidential

Where are we today

Logic Cells

125K

105K

Block RAM

10Mb

3Mb

Multipliers

556

168

3.125Gb/sMGTs

424

PowerPCCPUs

840Mb/sLVDS

340

442

XC2VP125XC2V8000= 350M tranistors

Xilinx Confidential

“Low PowerPC”: 0.59mW/MIPSP

ower

(m

W)

Performance (Dhrystone MIPS)

50 100 200 300 400150 250 350

100

200

300

400

0

Full-Custom IBM CPU Design1.5V 130nm CMOS Technology

Low-K DielectricIP-Immersion

Full-Custom IBM CPU Design1.5V 130nm CMOS Technology

Low-K DielectricIP-Immersion

100mW = 1 LED Indicator

…or 169 MIPS!

Xilinx Confidential

IP-ImmersionEmbed multiple IP blocks of arbitrary shape with

high-bandwidth connectivity to FPGA core logic, memory & I/O

Technologies Enabling IP-Immersion

Active Interconnect™Segmented Routing

Metal 1

Metal 2

Metal 3

Metal 4

Metal 5

Metal 6

Metal 7

Metal 8

Silicon Substrate

Poly

Advanced hard-IP block(e.g. PowerPC CPU)

Metal ‘Headroom’

Metal 9

PPC PPC

Xilinx Confidential

HW/SW Interfacing• Provides Specialized Connectivity

Between PowerPC & FPGA Logic• Dual-Port BlockRAM Memory

– CPU & Logic Each Own 1 Port

• High-Bandwidth– 6.4Gb/sec

• Low-Latency• Non-Caching

– Designed for Communications Data Processing

• Enables PowerPC & FPGA Logic to Work together on Complex Problems

BlockRAMs

I-Cache16KB MMU

Fetch & Decode

Timers and

Debug Logic

Execution Unit32x32b GPRALU, MAC

D-Cache16KB

AccelerationLogic

6.4Gb/sec

6.4Gb/sec

6.4Gb/sec

6.4Gb/sec

Xilinx Confidential

System Level Design Flow

HW SynthesisEmbedded Software

HW-SW Co-HW-SW Co-designdesign

HDLHDLANSI C/C++ANSI C/C++

Behavioral C/C++

System Design

and Partitioning

Cycle-Accurate C/C++

FunctionalModeling

ImplementationArchitecture

ArchitecturalExploration

IPModels

Formal/ Plug&PlayFormal/ Plug&Play

Enabling Technologies