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My first program in Verilog
Feb-9-2014
Introduction
If you refer to any book on programming languages, it starts with an "Hello
orl!" program on#e you ha$e written it, you #an be sure that you #an !o
something in that language %
ell I am also going to show how to write a "hello world"program, followe! bya "counter"!esign, in &erilog%
Hello World Program
1 //----------------------------------------------------- 2 // This is my first Verilog Program
3 // Design Name : hello_world 4 // File Name : hello_world! " // F#n$tion : This %rogram will %rint &hello world& ' // (oder : Dee%a) * //----------------------------------------------------- + mod#le hello_world , 1. initial egin11 0dis%lay ello orld y Dee%a)5,12 61. 0finish,13 end141" endmod#le // 7nd of 8od#le hello_world
'ou #oul! !ownloa! file hello(worl!%$here
Object1
Object2
Object3
Object4Object5
Object6
Object7
Object8
Object9
Object10Object11
Object12
http://www.asic-world.com/code/verilog_tutorial/hello_world.vhttp://www.asic-world.com/code/verilog_tutorial/hello_world.vhttp://www.asic-world.com/index.htmlhttp://www.asic-world.com/sponsor.htmlhttp://www.asic-world.com/verilog/verifaq.htmlhttp://www.asic-world.com/verilog/verilinks.htmlhttp://www.asic-world.com/verilog/books.htmlhttp://www.asic-world.com/verilog/tools.htmlhttp://www.asic-world.com/verilog/questions.htmlhttp://www.asic-world.com/examples/verilog/index.htmlhttp://www.asic-world.com/verilog/index.htmlhttp://www.smart-dv.com/http://www.asic-world.com/code/verilog_tutorial/hello_world.v -
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or!s in green are #omments, blue are reser$e! wor!s% )ny program in &erilogstarts with reser$e! wor! *mo!ule* +mo!ule(name% In the abo$e eample line .
#ontains mo!ule hello(worl!% /ote e #an ha$e #ompiler pre-pro#essor
statements like in#lu!e*, !efine* before mo!ule !e#laration3
ine 10 #ontains the initial blo#k this blo#k gets ee#ute! only on#e after the
simulation starts, at time50 /0ns3% 6his blo#k #ontains two statements whi#h are
en#lose! within begin, at line 10, an! en!, at line 17% In &erilog, if you ha$emultiple lines within a blo#k, you nee! to use begin an! en!% 8o!ule en!s with
*en!mo!ule* reser$e! wor!, in this #ase at line 1%
Hello World Program Output
Hello World by Deepak
Counter Design Bloc
Counter Design !pecs
4-bit syn#hronous up #ounter%
a#ti$e high, syn#hronous reset%
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)#ti$e high enable%
Counter Design
1 //----------------------------------------------------- 2 // This is my se$ond Verilog Design 3 // Design Name : first_$o#nter 4 // File Name : first_$o#nter! " // F#n$tion : This is a 4 it #%-$o#nter with ' // 9yn$hrono#s a$ti!e high reset and * // with a$ti!e high enale signal
+ //----------------------------------------------------- mod#le first_$o#nter 1. $lo$) // (lo$) in%#t of the design11 reset // a$ti!e high syn$hrono#s ;eset in%#t12 enale //
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Counter est Bench
)ny !igital #ir#uit, no matter how #omple, nee!s to be teste!% For the #ounter
logi#, we nee! to pro$i!e #lo#k an! reset logi#% :n#e the #ounter is out of reset,we toggle the enable input to the #ounter, an! #he#k the wa$eform to see if the#ounter is #ounting #orre#tly% 6his is !one in &erilog%
6he #ounter testben#h #onsists of #lo#k generator, reset #ontrol, enable #ontrolan! monitor;#he#ker logi#%
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32 $o#nter_o#t33 5,343" endmod#le
'ou #oul! !ownloa! file first(#ounter(tb%$ here
time clk reset enable counter0 1 0 0 xxxx5 0 1 0 xxxx10 1 1 0 xxxx11 1 1 0 000015 0 0 0 000020 1 0 0 000025 0 0 1 000030 1 0 1 000031 1 0 1 0001
35 0 0 1 000140 1 0 1 000141 1 0 1 001045 0 0 1 001050 1 0 1 001051 1 0 1 001155 0 0 1 001160 1 0 1 001161 1 0 1 010065 0 0 1 010070 1 0 1 010071 1 0 1 010175 0 0 1 010180 1 0 1 010181 1 0 1 011085 0 0 1 01100 1 0 1 01101 1 0 1 01115 0 0 1 0111100 1 0 1 0111101 1 0 1 1000105 0 0 1 1000110 1 0 1 1000111 1 0 1 1001115 0 0 1 1001120 1 0 1 1001121 1 0 1 1010125 0 0 0 1010
Counter Wa#eform
http://www.asic-world.com/code/verilog_tutorial/first_counter_tb.vhttp://www.asic-world.com/code/verilog_tutorial/first_counter_tb.vhttp://www.asic-world.com/code/verilog_tutorial/first_counter_tb.v -
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Copyright $%%&'()$*
Deepa +umar ala ' ,ll rights reser#ed
Do you ha#e any Comment- mail me at.deepa/asic'world0com
My first program in Verilog
Feb-9-2014
Introduction
If you refer to any book on programming languages, it starts with an "Hello
orl!" program on#e you ha$e written it, you #an be sure that you #an !o
something in that language %
ell I am also going to show how to write a "hello world"program, followe! by
mailto:[email protected]://www.asic-world.com/examples/verilog/index.htmlhttp://www.asic-world.com/verilog/index.htmlhttp://www.smart-dv.com/http://www.asic-world.com/verilog/syntax.htmlhttp://www.asic-world.com/verilog/first.htmlhttp://www.asic-world.com/verilog/first.htmlmailto:[email protected] -
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a "counter"!esign, in &erilog%
Hello World Program
1 //----------------------------------------------------- 2 // This is my first Verilog Program 3 // Design Name : hello_world 4 // File Name : hello_world! " // F#n$tion : This %rogram will %rint &hello world& ' // (oder : Dee%a) * //-----------------------------------------------------
+ mod#le hello_world , 1. initial egin11 0dis%lay ello orld y Dee%a)5,12 61. 0finish,13 end141" endmod#le // 7nd of 8od#le hello_world
'ou #oul! !ownloa! file hello(worl!%$here
or!s in green are #omments, blue are reser$e! wor!s% )ny program in &erilog
starts with reser$e! wor! *mo!ule* +mo!ule(name% In the abo$e eample line .#ontains mo!ule hello(worl!% /ote e #an ha$e #ompiler pre-pro#essor
statements like in#lu!e*, !efine* before mo!ule !e#laration3
ine 10 #ontains the initial blo#k this blo#k gets ee#ute! only on#e after thesimulation starts, at time50 /0ns3% 6his blo#k #ontains two statements whi#h are
en#lose! within begin, at line 10, an! en!, at line 17% In &erilog, if you ha$emultiple lines within a blo#k, you nee! to use begin an! en!% 8o!ule en!s with
*en!mo!ule* reser$e! wor!, in this #ase at line 1%
Hello World Program Output
Hello World by Deepak
http://www.asic-world.com/code/verilog_tutorial/hello_world.vhttp://www.asic-world.com/code/verilog_tutorial/hello_world.vhttp://www.asic-world.com/jobs.htmlhttp://www.asic-world.com/faq.htmlhttp://www.asic-world.com/disclaimer.htmlhttp://www.asic-world.com/index.htmlhttp://www.asic-world.com/sponsor.htmlhttp://www.asic-world.com/verilog/verifaq.htmlhttp://www.asic-world.com/verilog/verilinks.htmlhttp://www.asic-world.com/verilog/books.htmlhttp://www.asic-world.com/verilog/tools.htmlhttp://www.asic-world.com/verilog/questions.htmlhttp://www.asic-world.com/code/verilog_tutorial/hello_world.v -
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Counter Design Bloc
Counter Design !pecs
4-bit syn#hronous up #ounter%
a#ti$e high, syn#hronous reset%
)#ti$e high enable%
Counter Design
1 //----------------------------------------------------- 2 // This is my se$ond Verilog Design
3 // Design Name : first_$o#nter 4 // File Name : first_$o#nter! " // F#n$tion : This is a 4 it #%-$o#nter with ' // 9yn$hrono#s a$ti!e high reset and * // with a$ti!e high enale signal + //----------------------------------------------------- mod#le first_$o#nter 1. $lo$) // (lo$) in%#t of the design11 reset // a$ti!e high syn$hrono#s ;eset in%#t12 enale //
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2. o#t%#t ?3:.@ $o#nter_o#t ,21 //-------------=n%#t %orts Data Ty%e-------------------22 // Ay r#le all the in%#t %orts sho#ld e wires23 wire $lo$) ,24 wire reset ,2" wire enale ,2' //------------->#t%#t Ports Data Ty%e------------------2* // >#t%#t %ort $an e a storage element reg5 or a wire2+ reg ?3:.@ $o#nter_o#t ,23. //------------(ode 9tarts ere-------------------------31 // 9in$e this $o#nter is a %ositi!e edge trigged one32 // e trigger the elow lo$) with res%e$t to %ositi!e33 // edge of the $lo$)34 always B %osedge $lo$)53" egin : (>CNT7; // Alo$) Name3' //
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2 mod#le first_$o#nter_t5, 3 // De$lare in%#ts as regs and o#t%#ts as wires 4 reg $lo$) reset enale, " wire ?3:.@ $o#nter_o#t, '* // =nitialiHe all !ariales
+ initial egin 0dis%lay timeIt $l) reset enale $o#nter5,1. 0monitor JgIt J J J J11 0time $lo$) reset enale $o#nter_o#t5,12 $lo$) 1, // initial !al#e of $lo$)13 reset ., // initial !al#e of reset14 enale ., // initial !al#e of enale1" 6" reset 1, //
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80 1 0 1 010181 1 0 1 011085 0 0 1 01100 1 0 1 01101 1 0 1 01115 0 0 1 0111100 1 0 1 0111101 1 0 1 1000105 0 0 1 1000110 1 0 1 1000111 1 0 1 1001115 0 0 1 1001120 1 0 1 1001121 1 0 1 1010125 0 0 0 1010
Counter Wa#eform
Copyright $%%&'()$*
Deepa +umar ala ' ,ll rights reser#ed
Do you ha#e any Comment- mail me at.deepa/asic'world0com
mailto:[email protected]://www.asic-world.com/verilog/syntax.htmlhttp://www.asic-world.com/verilog/first.htmlhttp://www.asic-world.com/verilog/first.htmlmailto:[email protected]
