IV Cycle Programs

IV CYCLE PROGRAMS

// relay//

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity relay is Port ( p : in std_logic; m : out std_logic);end realy;

architecture Behavioral of relay is

begin process(p) begin if (p='1')then m<='1'; else m<='0'; end if; end process;

end Behavioral;

// rw_dac //


entity rw_dac is Port ( clk,rst : in std_logic; op : out std_logic_vector(7 downto 0));end rw_dac;

architecture Behavioral of rw_dac is signal q: std_logic_vector(7 downto 0);

begin process(clk,rst)

begin

if(rst='0') then q<=(others=>'0');

elsif (clk'event and clk='1') then

q<= q+1; ----for step q<=q+8

end if; end process;

op<=q;

end Behavioral;

// tri_ dac//


entity tri_dac is Port ( clk,rst : in std_logic; op : out std_logic_vector(7 downto 0));end tri_dac;

architecture Behavioral of tri_dac is signal q: std_logic_vector(7 downto 0); signal ud:std_logic:='0';

begin process(clk,rst)

begin

if(rst='0') then q<=(others=>'0');

elsif (clk'event and clk='1') then

if (ud='0')then q<=q+1; elsif (ud='1')then q<=q-1; end if;

end if; end process; op<=q;

process (clk) begin if (clk'event and clk='1')then if(q="11111110")then ud<='1'; elsif(q="00000001")then ud<='0'; end if; end if; end process;

end Behavioral;

// DC MOTOR //


entity TKBDCM is Port ( psw : in std_logic_vector(2 downto 0);

pdcm : out std_logic; p100k : in std_logic );

end TKBDCM;

architecture behavioral of TKBDCM issignal sclkdiv : std_logic_vector(11 downto 0);

begin

-- count upto 3000process(p100k)begin--+

if( rising_edge(p100k)) thensclkdiv <= sclkdiv+1;

end if;

if(sclkdiv = "101110111000") thensclkdiv <= "000000000000";

end if;end process;

process(psw,sclkdiv)variable vdcm : bit;begin

if(sclkdiv = "000000000000") thenvdcm := '1';

end if;

-- 1f4, 320, 44c, 578, 6a4, 7d0, 8fc, 9c4

if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0';elsif(psw = "010" and sclkdiv = "010001001100") then vdcm := '0';elsif(psw = "011" and sclkdiv = "010101111000") then vdcm := '0';elsif(psw = "100" and sclkdiv = "011010100100") then vdcm := '0';elsif(psw = "101" and sclkdiv = "011111010000") then vdcm := '0';elsif(psw = "110" and sclkdiv = "100011111100") then vdcm := '0';elsif(psw = "111" and sclkdiv = "100111000100") then vdcm := '0';end if;

if(vdcm = '1') then pdcm <= '1';else pdcm <= '0';end if;

end process;

end behavioral;

// V CYCLE PROGRAMS

//HEXKEYPAD


entity TKBHKY is Port ( pkeyret : in std_logic_vector(3 downto 0);

pkeyscn : out std_logic_vector(3 downto 0); pdspseg : out std_logic_vector (6 downto 0); pdspmux : out std_logic_vector (3 downto 0); pclk100K : in std_logic

);

end TKBHKY;

architecture behavioral of TKBHKY issignal skeyval : integer range 0 to 15;signal skeyhit : std_logic; signal skeyscn : std_logic_vector(3 downto 0);signal sclkdiv : std_logic_vector(7 downto 0);signal skeyclk : std_logic;

begin-------- process clk dividerprocess(pclk100k)begin

if( rising_edge(pclk100k)) thensclkdiv <= sclkdiv+1;

end if;

skeyclk <= sclkdiv(6);end process;

-------- process for key scan clkscan

process(skeyclk)begin

if(rising_edge(skeyclk)) thenif skeyscn = "1110" then skeyscn <= "1101";elsif skeyscn = "1101" then skeyscn <= "1011";elsif skeyscn = "1011" then skeyscn <= "0111";elsif skeyscn = "0111" then skeyscn <= "1110";else skeyscn <= "1110";end if;

end if;pkeyscn <= skeyscn;

end process;

--------- process keypressprocess(pkeyret)begin

case pkeyret iswhen "1110" => skeyhit <= '1';when "1101" => skeyhit <= '1';when "1011" => skeyhit <= '1';when "0111" => skeyhit <= '1';when others => skeyhit <= '0';

end case;end process;

--------- process keyvalprocess(skeyhit)begin

if( rising_edge(skeyhit)) thenif(skeyscn = "1110" and pkeyret = "1110")

then skeyval <= 0;elsif(skeyscn = "1110" and pkeyret = "1101")











then skeyval <= 11; elsif(skeyscn = "0111" and pkeyret = "1110")




then skeyval <= 15;end if;

end if;end process;

-------- process display 7segprocess(skeyval)type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);constant segval : tseg7 :=

("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000111","1111111","1101111","1110111","1111100","1011000","1011110","1111001","1110001"); begin

pdspseg <= segval(skeyval);

pdspmux <= "1101";end process;

end behavioral;#PINLOCK_BEGIN HEXKEYPAD

#Mon Apr 26 15:30:27 2010

NET "pclk100K" LOC = "S:PIN55";

NET "pkeyret<0>" LOC = "S:PIN1";NET "pkeyret<1>" LOC = "S:PIN2";NET "pkeyret<2>" LOC = "S:PIN3";NET "pkeyret<3>" LOC = "S:PIN4";

NET "pkeyscn<0>" LOC = "S:PIN5";NET "pkeyscn<1>" LOC = "S:PIN6";NET "pkeyscn<2>" LOC = "S:PIN7";NET "pkeyscn<3>" LOC = "S:PIN9";

NET "pdspmux<0>" LOC = "S:PIN14";NET "pdspmux<1>" LOC = "S:PIN15";NET "pdspmux<2>" LOC = "S:PIN17";NET "pdspmux<3>" LOC = "S:PIN18";

NET "pdspseg<0>" LOC = "S:PIN31";NET "pdspseg<1>" LOC = "S:PIN32";NET "pdspseg<2>" LOC = "S:PIN33";NET "pdspseg<3>" LOC = "S:PIN34";NET "pdspseg<4>" LOC = "S:PIN35";NET "pdspseg<5>" LOC = "S:PIN36";NET "pdspseg<6>" LOC = "S:PIN37";

#PINLOCK_END

//ELEVATOR


entity TKBELE is Port ( pkeyret : in std_logic_vector(3 downto 0);

pkeyscn : out std_logic_vector(3 downto 0); pdspseg : out std_logic_vector (6 downto 0); pdspmux : out std_logic_vector (3 downto 0); pclk100K : in std_logic

);end TKBELE;

architecture behavioral of TKBELE is

signal scurflr,snxtflr,skeyflr : integer range 0 to 15;signal sdir, skeyhit : std_logic; signal skeyscn : std_logic_vector(3 downto 0);signal sclkdiv : std_logic_vector(15 downto 0);signal sflrclk,skeyclk : std_logic;

begin

------- process clk divider--process(pclk100k)begin


end if;

skeyclk <= sclkdiv(6);sflrclk <= sclkdiv(15);

end process;

-------- process for key scan clkscanprocess(skeyclk)begin

if(rising_edge(skeyclk)) thenif skeyscn = "1110" then skeyscn <= "1101";elsif skeyscn = "1101" then skeyscn <= "1011";elsif skeyscn = "1011" then skeyscn <= "0111";elsif skeyscn = "0111" then skeyscn <= "1110";else skeyscn <= "1110";end if;

end if;pkeyscn <= skeyscn;

end process;

-------- process keypressprocess(pkeyret)begin

case pkeyret iswhen "1110" => skeyhit <= '1';when "1101" => skeyhit <= '1';when "1011" => skeyhit <= '1';when "0111" => skeyhit <= '1';when others => skeyhit <= '0';

end case;end process;

--------- process keyvalprocess(skeyhit)begin

if( rising_edge(skeyhit)) thenif(skeyscn = "1110" and pkeyret = "1110")

then skeyflr <= 0;elsif(skeyscn = "1110" and pkeyret = "1101")











then skeyflr <= 11; elsif(skeyscn = "0111" and pkeyret = "1110")




then skeyflr <= 15;end if;

end if;end process;

-------- process floor motionprocess(sflrclk)begin

if(rising_edge(sflrclk)) thenif(not (skeyflr = scurflr) ) then

if(skeyflr > scurflr) then scurflr <= scurflr+1;else scurflr <= scurflr-1;

end if;end if;

end if;end process;

-------- process display 7segprocess(scurflr)type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);constant segval : tseg7 :=

("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000111","1111111","1101111","1110111","1111100","1011000","1011110","1111001","1110001"); begin

pdspseg <= segval(scurflr);pdspmux <= "1110";

end process;

end behavioral;

#pin2ucf - #The following constraints were newly added ELEVATOR

NET "pclk100K" LOC = P55;

NET "pkeyscn<0>" LOC = P5;NET "pkeyscn<1>" LOC = P6;NET "pkeyscn<2>" LOC = P7;NET "pkeyscn<3>" LOC = P9;

NET "pkeyret<0>" LOC = P1;NET "pkeyret<1>" LOC = P2;NET "pkeyret<2>" LOC = P3;NET "pkeyret<3>" LOC = P4;

NET "pdspmux<0>" LOC = P14;NET "pdspmux<1>" LOC = P15;NET "pdspmux<2>" LOC = P17;NET "pdspmux<3>" LOC = P18;

NET "pdspseg<0>" LOC = P31;NET "pdspseg<1>" LOC = P32;NET "pdspseg<2>" LOC = P33;NET "pdspseg<3>" LOC = P34;NET "pdspseg<4>" LOC = P35;NET "pdspseg<5>" LOC = P36;NET "pdspseg<6>" LOC = P37;

---------------------------------------------------------------------------------- STEPPER MOTOR-- Company: -- Engineer: -- -- Create Date: 14:05:57 03/30/2010 -- Design Name: -- Module Name: stp_motor - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity TKBSTP is Port ( pkeycol : in std_logic_vector (3 downto 0);

pkeyrow : out std_logic_vector (3 downto 0); pstpsig : out std_logic_vector(3 downto 0); pclk100K : in std_logic );

end TKBSTP;

architecture behavioral of TKBSTP issignal sclkdiv : std_logic_vector(20 downto 0);signal sstpcnt : std_logic_vector(1 downto 0);signal sstpclk,skeyhit : std_logic;signal skeysts :std_logic_vector (3 downto 0);

begin

------- clkdividerprocess(pclk100k)begin


end if;

sstpclk <= sclkdiv(15);end process;

-------- key process-------- out key row = 0 check key colpkeyrow <= "0000";process(pkeycol)begin

if(pkeycol(0) = '0' or pkeycol(1) = '0' or

pkeycol(2) = '0' orpkeycol(3) = '0' ) then skeyhit <= '0';

else skeyhit <= '1';end if;

end process;

-------- latch key pressprocess(skeyhit)begin

if( falling_edge(skeyhit)) thenskeysts <= pkeycol;

end if;end process;

-------- 4 step counterprocess(sstpclk)begin

if(rising_edge(sstpclk)) thenif(skeysts(0) = '0') then

sstpcnt <= sstpcnt+1;elsif(skeysts(1) = '0') then

sstpcnt <= sstpcnt-1;end if;

end if;end process;

------ outputs signal pstpsig = D, C, B & A for stepper motor------ TKBase from ucf file = 14,13,12, 11------ als stepper controller = 4, 6, 3 & 5

process(sstpcnt)begin

if (sstpcnt = "00") then pstpsig <= "0001";elsif(sstpcnt = "01") then pstpsig <= "0111";elsif(sstpcnt = "10") then pstpsig <= "1110";elsif(sstpcnt = "11") then pstpsig <= "1000";end if;

end process;

end behavioral;

#pin2ucf - #The following constraints were newly added STEPPER MOTOR

NET "pclk100K" LOC = P20;

NET "pstpsig<0>" LOC = P14;NET "pstpsig<1>" LOC = P15;NET "pstpsig<2>" LOC = P17;NET "pstpsig<3>" LOC = P18;

NET "pkeycol<0>" LOC = P1;NET "pkeycol<1>" LOC = P2;NET "pkeycol<2>" LOC = P3;NET "pkeycol<3>" LOC = P4;

NET "pkeyrow<0>" LOC = P5;NET "pkeyrow<1>" LOC = P6;NET "pkeyrow<2>" LOC = P7;NET "pkeyrow<3>" LOC = P9;

------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 16:02:33 04/21/2010 -- Design Name: -- Module Name: movdsp - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity movdsp is Port ( pdspseg : out STD_LOGIC_VECTOR (6 downto 0); pdspmux : out STD_LOGIC_VECTOR (3 downto 0); pclk100k : in STD_LOGIC);end movdsp;

architecture Behavioral of movdsp is

signal sclkdiv : std_logic_vector(15 downto 0);signal sdspnum : integer range 0 to 15;signal sdspseq : std_logic_vector(2 downto 0);signal sdspmux : std_logic_vector(3 downto 0);signal smuxclk,sdspstp : std_logic;

begin

-------- process clk divider

process(pclk100k)begin


end if;

smuxclk <= sclkdiv(0);sdspseq(0) <= sclkdiv(1);sdspseq(1) <= sclkdiv(2);sdspseq(2) <= sclkdiv(3);sdspstp <= sclkdiv(15);

end process;

------ process pdspmuxprocess(sdspseq)begin

if(sdspseq = "000") then sdspmux <= "1110";elsif(sdspseq = "010") then sdspmux <= "1101";elsif(sdspseq = "100") then sdspmux <= "1011";elsif(sdspseq = "110") then sdspmux <= "0111";else sdspmux <= "1111";end if;pdspmux <= sdspmux;

end process;

------ process muxdispprocess(sdspmux)type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);constant segval : tseg7 :=

("0000000","0000000","0000000","0000000", "1111100","0000110","1111000","1000000", "0110000","1011011","1001111","1100110", "0000000","0000000","0000000","0000000");

beginif(sdspmux = "1110") then pdspseg <= segval(sdspnum);

elsif(sdspmux = "1101") then pdspseg <= segval(sdspnum+1);



else pdspseg <= "0000000";end if;

end process;

------ process dspnoprocess(sdspstp)

beginif(rising_edge(sdspstp)) then

sdspnum <= sdspnum+1;

end if;

end process;

end Behavioral;

#pin2ucf - Wed#The following constraints were newly added moving dsp

NET "pdspmux<0>" LOC = P14;NET "pdspmux<1>" LOC = P15;NET "pdspmux<2>" LOC = P17;NET "pdspmux<3>" LOC = P18;

NET "pclk100k" LOC = P52;

NET "pdspseg<0>" LOC = P31;NET "pdspseg<1>" LOC = P32;NET "pdspseg<2>" LOC = P33;NET "pdspseg<3>" LOC = P34;NET "pdspseg<4>" LOC = P35;NET "pdspseg<5>" LOC = P36;NET "pdspseg<6>" LOC = P37;

DAC MOV DISPLAYFPGA/DAC

2------CLK

3------RST

4------21

5------22

7------19

9------20

10----17

11----18

12----15

13----16

26 PIN OF DAC TO GNDOF FPGA

CPLD/MUX/SEG

2------MUX1

3-----MUX2

4-----MUX3

5-----MUX4

31----A

32----B

33----C

34----D

35----E

36----F

37----G

52---- CLK(100)

IV Cycle Programs

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