ITT430 Microprocessor

CONFIDENTIAL CS/APR2010/ITT430

UNIVERSITI TEKNOLOGI MARA FINAL EXAMINATION

COURSE

COURSE CODE

EXAMINATION

TIME

MICROPROCESSOR

ITT430

APRIL 2010

3 HOURS

INSTRUCTIONS TO CANDIDATES

The question paper consists of three (3) parts PART A (25 Questions) PART B (25 Questions) PART C (6 Questions)

Answer ALL questions from all three (3) parts. ) Answer Part A in the Objective Answer Sheet ) Answer Part B in the True / False Answer Sheet ) Answer Part C in the Answer Booklet. Start each answer on a new page.

Do not bring any material into the examination room unless permission is given by the invigilator.

Please check to make sure that this examination pack consists of: the Question Paper an Answer Booklet - provided by the Faculty a True / False Answer Sheet - provided by the Faculty

iv) an Objective Answer Sheet - provided by the Faculty

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 12 printed pages © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL

CONFIDENTIAL 2 CS/APR2010/ITT430

PART A (25 MARKS)

For each of the following questions, choose ONE (1) suitable answer and mark the answer on the Objective Answer Sheet provided.

1. If the ASCII representation for character " f is 66H, what is the ASCII representation for character "t" ?

A. 72H B. 73H C. 74H D. 75H

2. The content of AH register to invoke the interrupt 21H so that it display a string of data to the screen is

A. (AH)=03H B. (AH)=05H C. (AH)=07H D. (AH)=09H

3. What is the duration of the bus cycle in the 8088-based microcomputer if the clock is 8 MHz and two wait states are inserted?

A. 500 ns B. 625 ns C. 750 ns D. 875 ns

4. The bus activity when the bus status code S2S1S0 equals 011 is

A. read I/O port B. write I/O port C. halt D. instruction fetch

© Hak Cipta Universiti Teknologi MARA CONFIDENTIAL


5. The timing properties defined for the read cycle of an EPROM will be

I access time (tACc) II chip-enable time (tCE) III chip-deselect time (tDF)

A. I B. I, II C. II, III D. I, II, III

6. In a sixty-four-line parallel output circuit for an 8088-based microcomputer, if the address put on the bus during an output bus cycle is 800A16, the output port that the data will be written to will be

A. Port 0 B. Port 2 C. Port 4 D. None of the above

7. The flag tested for the loop instruction LOOPE is

A. CF B. SF C. OF D. ZF

8. The content of DX after executing the following instructions in the DEBUG trace is

MOV DX, 7676H MOV CL, 4 STC RCL DX, CL

A. 6763H B. 676BH C. 6767H D. 0767H


CONFIDENTIAL 4 CS/APR 2010/ITT430

9. The following statements are all true EXCEPT

A. I/O data transfers in the 8088 and 8086 microcomputers can be either byte-wide or word-wide.

B. In 8088 microcomputer, the word transfer is performed as two consecutive byte-wide data transfer and takes two bus cycles.

C. In 8086 microcomputer, the word transfer takes one bus cycle. D. Word-wide I/O should be aligned at even-address boundaries.

10. The status flags will be shown after executing the following instructions in the DEBUG

trace is .

MOV AL, - 5 CMP AL, - 9 ADD AL, 7 CMP AL, - 2

A. NV UP DI PL NZ AC PO CY B. NV UP DI PL NZ NA PE NC C. NV UP DI NG ZR AC PE CY D. NV UP DI PL ZR NA PO CY

11. The key differences between NMI and the other external hardware initiated interrupts are _.

I NMI is masked out by IF II NMI is initiated from the NMI input lead instead of from the INTR input. III NMI input is edge-triggered instead of level sensitive.

A . I, II B . I, III C . II, III D. I, II, III

12. The number of bytes required to encode the instruction "MOV [ D I ] + 123H, 1234H" is

A. 3 bytes B. 4 bytes C. 5 bytes D. 6 bytes




A. The read bus cycle begins with state J,. B. Signals IO/M and DT/R are set to 1 and 0 logic levels respectively at the start

ofT,. C. Status bits S3 through S6 are output on the upper four address bus lines Ai6

through A-,9 at the beginning of T2. D. Signal RD is switched to logic 1 at the later part of T2.


A. If an external device wants to take control of the system bus, it signals this fact to the MPU by switching HOLD to logic 1.

B. In the hold state, signal lines AD0 through AD7 will be switched to logic 1. C. Other signal lines such as SSO, IO/M, DT/R, DEN and INTR are all put into

high-Z state during the hold state. D. The 8088 signals external devices that the signal lines are in the high-Z state

by switch its HLDA output to logic 1.

15. If the content of (SP)=FF2EH, (AX)=3291H, (BX)=F43CH, and (CX)=09H. What is the content of the stack pointer after the execution of the following instructions?

PUSH AX POP BX PUSH CX POP DX

A. FF2EH B. FF2CH C. FF2AH D. FF28H

16. What value must be written to the control register of the 82C55A to configure the device such that port A and port B are configured as output ports and port C is set up as input port in mode 0 operation ?

A. 88H B. 89H C. C8H D. C9H



17. This program is known as a delay program. In this program, the "JNZ DLY" instruction is executed for

A. B. C. D.

MOV CX, 100H DLY: DEC CX

NOP LOOP DLY

NXT:

128 times 255 times 256 times 277 times

18. The content of AX after executing the following sequence of instructions is

MOV AH, FF MOV AL, F7 MOV BL, 2 IDIV BL

A. (AX)=FFFAH B. (AX)=FFFBH C. (AX)=FFFCH D. (AX)=FFFDH


A. The maximum-mode configuration is mainly used for implementing a multiprocessor/coprocessor system environment.

B. In the maximum-mode, 8088/8086 outputs a status code on three signal line S0, ST and S2 prior to the initialization of each bus cycle.

C. The 3-bit bus status code identifies which type of bus cycle is to follow and are input to the external bus controller device, 8288.

D. The 8088 produces one command signals for each bus cycle.

20. When the instruction POP CX is executed, the address bus status code and memory bus cycle code output by the 8088 in a maximum mode microcomputer system are

A. S4S3=01 andS2S1S0=101 B. S4S3=01 andS2S1S0=110 C. S4S3=10 and S2S1S0=101 D. S4S3=10 and S2S1S0=110



21. In the maximum-mode I/O interface of 8088 system, the logic levels of IORC, IOWC, and AIOWC during an output bus cycle are .

A. IORC= 1, IOWC=0, and AIOWC=0 B. IORC= 1, IOWC=0, and AIOWC=0 C. IORC= 0, IOWC=1, and AIOWC=1 D. IORC= 0, IOWC=1, and AIOWC=1

22. The address of the vector 47, CS47 and IP47 stored in the interrupt vector table is

A. CS47=BCH and IP47=BEH B. CS47=BEH and IP47=BCH C. CS47=BCH and IP47=BAH D. CS47=BAH and IP47=BCH


A. The read bus cycle begins with state Ti. B. Signals IO/M and DT/R are set to 1 and 0 logic levels respectively at the start

ofTi . C. Status bits S3 through S6 are output on the upper four address bus lines A16

through A19 at the beginning of T2. D. Signal RD is switched to logic 1 at the later part of T2.

24. When the MPU recognizes the RESET input, it initiates its internal initialization routine and flags are all cleared. As a result of this process, the content of the CS register is .

A. 0000H B. 00FFH C. FF00H D. FFFFH

25. The 8255A PPI has three 8-bit ports for implementing inputs or outputs. The I/O addresses where the ports PA, PB, and PC reside are .

A. 005016, 005116, and005216

B. 006016, 006116, and006216

C. 007016, 007116, and007216

D. 008016, 008116, and008216



PART B (25 MARKS)

For each of the following questions, answer either TRUE or FALSE and mark your answer on the TRUE/FALSE Answer Sheet provided.

1. Pointer and index registers can be accessed either as a whole 16 bits for word data operations or as two 8-bit registers for byte-wide data operations.

2. RET instruction will return execution to the main program by restoring IP and CS registers.

3. CMP instruction alters the contents of it operands and status flags of the 8086/8066.

4. An internal clock synchronises computer operations.

5. When direct memory access (DMA) is working, the CPU is working too.

6. In based addressing mode, the effective address is obtained from the contents of a base register and a displacement.

7. In a LOOPZ instruction, the instruction will jump to the label if CX is not equal to zero and zero flag is set.

8. All registers within the 8088/8086 microprocessor is located at the Execution Unit (EU).

9. The SS and CS registers have their contents changed during the intrasegment jump.

10. The reserved memory which are saved for the storage of the pointers that are used for the 8088's user-defined interrupts are located at 0001416- 0007F16.

11. SRAM is normally used in application that requires a large amount of memory.

12. The name given to the part of the I/O address space from 0000i6 through 00FFi6 is Page 0.

13. The maximum number of repeats that can be implemented with a loop instruction is 65535.

14. The interrupt function service routine specified by CS5:IP5 is overflow routine.

15. A UART can be programmed to operate in "polled mode" or in "interrupt-driven" mode.

16. When the I/O address on the bus is 800616, port 2 of the sixty-four-line parallel input circuit of an 8088-based microcomputer is selected.



17. When the memory address on the bus is 0040216, Port B on PPI 0 is selected for memory-mapped 82C55A parallel I/O port in an 8088-based microcomputer.

18. When a peripheral device wants to perform DMA operations, it makes a request for service at its DREQ input by switching it to logic 0.

19. The storage array in the bulk-erase device is a single block, whereas the memory array in both the boot block and FlashFile is organized as multiple independently erasable blocks.

20. In an 8086-based microcomputer system, the logic levels of Ao and BHE when a byte of data being written to I/O address 400216 is 0 and 1 respectively.

21. If the contents of registers AL and BL are -1 and 4 respectively, then the content of AX is FFFCH after executing the instruction " I M U L BL".

22. C416 is the control word of the 82C55A to configure the device such that port A is configured for bi-directional operation and port B is set up for mode 0 output operation.

23. In a maximum mode system, 8288 device produces the input, output, and bus control signals for the I/O interface.

24. If (AX)=8FFFH, the new contents of AX and DX are 8FFFH and FFFFH respectively after executing the instruction "CWD".

25. A read bus cycle will have six clock states when it has two wait cycles.



PART C (50 MARKS)

Answer ALL questions.

QUESTION 1

Encode (in hexadecimal) the following instructions using the information given in Table 1 and Table 2. Assume that the opcode for the MOV, ADD and LEA operations are 100010, 000000 and 10001101 respectively.

a) MOV AX, [ B P ] [ S I ] + 194H

(2 marks)

b) ADD [DI ] , AX

(2 marks)

C) LEA D I , [ S I + BX + 5H]

(2 marks)

Table 1: Register Field Encoding

REG 000 001 010 011 100 101 110 111

w=o AL CL DL BL AH CH DH BH

W=1 AX CX DX BX SP BP SI DI

Table 2: Register/Memory Encoding Field

MOD=1 R/M 000 001 010 011 100 101 110 111

1 w=o AL CL DL BL AH CH DH BH

W=1 AX CX DX BX SP BP SI DI

EFFECTIVE ADDRESS CALCULATIO R/M 000 001 010 011 100 101 110 111

MOD=00 (BX)+(SI) (BX)+(DI) (BP)+(SI) (BP)+(DI) (SI) (DI) Dir. address (BX)

MOD=01 (BX)+(SI)+D8 (BX)+(DI)+D8 (BP)+(SI)+D8 (BP)+(DI)+D8 (Sl)+D8 (Dl)+D8 (BP)+D8 (BX)+D8

N MOD=10 (BX)+(SI)+D16 (BX)+(DI)+D16 (BP)+(SI)+D16 (BP)+(DI)+D16 (Sl)+D16 (Dl)+D16 (BP)+D16 (BX)+D16



QUESTION 2

a) Name and state TWO (2) functions of the internal processing units of 8088/8086 microprocessor.

(3 marks)

b) Name THREE (3) elements that belong to the above internal processing units.

(3 marks)

c) Define the signal applied to configure the 8088 microprocessor to work in minimum-mode and maximum-mode system. State the type of system and the number of microprocessor offered in both configurations.

(3 marks)

QUESTION 3

Determine whether the following instructions can be executed by the 8086/8088 and state the reason.

a) SUB [ D I ] , 1234H;

(2 marks)

b) MOV DS, 1234H;

(2 marks)

C) IN BL, AL;

(2 marks)

d) XCHG [ D I ] , [ S I ] ;

(2 marks)

QUESTION 4

a) Define a bus cycle of the 8086/8088 microprocessor. Give the minimum clock period for a bus cycle required by 8086/8088 microprocessor.

(2 marks)

b) Define the bus cycle of the 8086/8088 microprocessor for a read cycle. (3 marks)

c) Define the bus cycle of the 8086/8088 microprocessor for write cycle. (3 marks)

© Hak Cipta Universiti Toknologi MARA CONFIDENTIAL


QUESTION 5

A memory-mapped 82C55A parallel I/O interface resides in the 1 Mbyte memory of the 8088 microprocessor.

a) Determine the memory address of the control register for PPI4. (1 mark)

b) Determine the control byte so that Port A is an input port, ports B and C are input ports and all three ports are configured for mode 0 operation.

(1 mark)

c) Determine the addresses of the three I/O ports on PPI4. (3 marks)

QUESTION 6

a) Determine whether or not the jump will occur at the end of the following sets of instructions. Shows the final content of AL register.

i)

iii)

MOV XOR SHL JZ

MOV MOV OR SHL JC

MOV SUB OR MOV AND SHR JNC

CL, AL, AL,

8 AL CL

TARGET

BH, AL, AL, AL,

65H 1111 BH 1

TARGET

AL, DL, AL, CL, CL, AL,

27H DL DL AH OFH CL

TARGET

(2 marks)

(2 marks)

(2 marks)

b) Develop a program to COUNT the data byte in memory that equal to 43H starting at memory location 1000H through 1050H. Place the OUTPUT in BX register.

(8 marks)

END OF QUESTION PAPER


ITT430 Microprocessor

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