ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides6.ppt Modification date: Oct 30, 2014 1...
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Transcript of ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides6.ppt Modification date: Oct 30, 2014 1...
ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides6.ppt Modification date: Oct 30, 2014 1
Processor DesignSpecifying the Actions
Internal Architecture of a Simple Processor
2
ControlUnit
IR
ALURegisters
PC
Main memory
ControlData Address
Processor(representative)
Controlsignals
signals
Systembus
Internal bus
Holds machine instructionto be/being executed
Arithmetic and logic unitfor performing arithmeticand logical operations
Main registersholding operands
Program counterholding addressof next instruction
say R0 to R31
R0
R31
Program Counter more accurately called the Instruction Pointer, IP.
Internal Architecture of a Simple Processor(Not representative of modern computer, later on that)
3
MDR and MAR registers
Added to hold data or from memory and address to select memory location:
ControlUnit
IR
ALURegisters
PC
Main memory
ControlData Address
Controlsignals
signals
Systembus
Internal bus
MARMemoryaddressregister
MDRMemorydataregister
MDR MAR
4
Internal Operation
Operation of processor divided into two phases:
• Fetch cycleNext instruction is fetched from memory
• Execute cycleFetched instruction is executed
These cycles are repeated as each instruction is executed.
Fetch cycle
Execute cycle
5
Fetch CycleSelect instruction:
ControlUnit
IR
ALURegisters
PC
Main memory
ControlData Address
Processor
Controlsignals
signals
Systembus
Internal bus
Select nextinstruction
MDR MAR
6
Fetch instruction:
ControlUnit
IR
ALURegisters
PC
Main memory
ControlData Address
Processor
Controlsignals
signals
Systembus
Internal bus
Instruction
MDR MAR
7
Register Transfer Notation
Mostly, actions within processor can be described by the transfer of the contents of one location to another location (registers or units).Use a register transfer language (RTL) notation.
ExampleTo transfer the contents of register MDR to register IR, we write:
IR MDR
IR MDR
8
May add time of action:
T2: IR MDR
The transfer is to take place at time period T2.
IR MDR
This occurs at time period T2
9
Fetch Cycle
Fetch cycle actually breaks down into several steps:
T0: MAR PC Select next instruction
T1: MDR [MAR] Memory read operation, get instr. from memory
T2: IR MDR Load instruction into instruction register
T3: PC PC + 4 Increment program counter in preparationfor next fetch cycle
Could be done simultaneously
10
Fetch Cycle
Fetch cycle with last two steps done simultaneously:
T0: MAR PC Select next instruction
T1: MDR [MAR] Mem. read op., get instr. from mem.
T2: IR MDR; PC PC + 4 Load instruction into instr. registerIncrement prog. counter in prep.for next fetch cycle
11
Execute Cycle
Breaks down into several steps depending upon instruction fetched.
In our design, execution cycle steps start at T3.
To be able to specify certain steps, need to know machine instruction format.
We will give representative formats, which will be used in subsequent designs later.
12
Source and destination registers
We will use the notation:
Rs1 for the first source register Rs2 for the second source registerRd for the destination register
for register-register instructions as specified in the instruction.
Some instructions may only have one source register and/or no destination register.
13
Temporary registers
In some designs, it may be necessary to introduce temporary registers to hold Rs1, Rs2, Rd, say called A, B, and C. Then:
A Rs1 Contents of first source register copied to AB Rs2 Contents of second source register copied to B
will occur automatically whether or not they required by the instruction. If not required, A and B are not accessed subsequently.
Similarly if C is loaded, the operation:
Rd C Copy C to destination register
occurs automatically.
14
Execute Cycle for Add Instruction
Register-register addressing
Example:
ADD Rd, Rs1, Rs2
T3: Rd Rs1 + Rs2 Perform addition and pass result back to Rd
ADD Rd Rs1
0151631
Machine instruction format:
Rs2 Not used
2021 10112526
15
Execute Cycle for Add Instruction
Immediate Addressing
ADDI Rd, Rs1, 123
T3: Rd Rs1 + IR15-0 Perform addition and pass result back to Rd
IR15-0 means here bits 15 to 0 of IR registerAssumes bits 15 to 0 in IR holds the constant (123 above)
ADDI Rd Rs1 Constant
0151631
Machine instruction format:
2526 2021
16
Other Arithmetic/Logic Instructions
Other arithmetic and logic instructions have similar sequences of steps. Simply replace the add operation in:
T3: Rd Rs1 + Rs2 Perform addition and pass result back to Rd
or
T3: Rd Rs1 + IR15-0 Perform addition and pass result back to Rd
with the appropriate arithmetic or logic operation.
17
Execute Cycle for Memory Reference Instructions
Load Instruction
LD Rd, 100[Rs1]
where 100 is a constant in the instruction (IR15-0)
T3: MAR Rs1 + IR15-0 Compute memory addressT4: MDR [MAR] Memory read operationT5: Rd MDR Get memory contents, load into Rd
ADDI Rd Rs1 Constant
0151631
Machine instruction format:
2526 2021
LD
18
Store Instruction
ST 100[Rs1], Rs2
where 100 is a constant in the instruction (IR15-0)
T3: MAR Rs1 + IR15-0 Compute memory addressT4: MDR Rs2 Get contents of registerT5: [MAR] MDR Memory write operation
ST Rs2 Rs1 Constant
0151631
Machine instruction format:
2526 2021
19
Branch Instructions
Bcond Rs1, L1
where cond specifies the condition, E, NE, L, G, GE, or LE.
T3: Rs1 - 0 Compare Rs1 with zeroT4: if (condition TRUE)
PC PC + IR15-0 Load PC with target address
Bcond Rs1 Offset
0151631
Machine instruction format:
Not used
Offset stored in instruction may need to be offset – 4 since PC already incremented by 4 by this time. Also need to take into account the offset is a word offset - not shown here.
20
Jump Instruction
PC-Relative Addressing
J L1
T3: PC PC + IR25-0 Load PC with target address
J Offset
0252631
Machine instruction format:
Again offset stored in instruction may need to be offset - 4
21
Jump Instruction
Register-Indirect Addressing
J 100[Rs1]
where the offset (100 above) is held in IR15-0
T3: PC Rs1 + IR15-0 Compute effective address and load PC with final target address
J Rs1 Offset
0151631
Machine instruction format:
Not used
2526 2021
22
Jump and Link Instruction
JAL L1
T3: R31 PC Store return address in R31T4: PC PC + IR25-0 Goto L1
JAL Offset
0252631
Machine instruction format:
23
CALL/RET Instructions
Even though our design does not have CALL and RET instructions, let us just list the steps for these instructions:
CALL proc1T3: SP SP – 4 Decrement stack pointer (by 4 if 32-bit addresses)T4: MAR SPT5: MDR PC PC holds return addressT6: [MAR] MDR Copy PC onto stack (return address)T7: PC IR25-0 Goto to procedure (address of proc1 held in IR25-0)
RETT3: MAR SPT4: MDR [MAR] Get return address from stackT5: PC MDR ReturnT6: SP SP + 4 Increment stack pointer (by 4 if 32-bit addresses)
24
State Diagram for Processor
MAR PC
IR MDR
PC PC + 4
Fetch cycle
Instruction decode
Register-register Register-constant Branch JumpMemoryreference
(load/store)
Executecycles
Memory read
(assumed not needing a state)
......
0
1
2
States numbered 0, 1 ...
MDR [MAR]
After previousinstructionexecuted orprocessor reset
Assuming separate logic to increment PC (not using ALU)
(Several) (Several) (Several)
25
Register-Register Instructions
The arithmetic and logic instructions operating upon pairs of registers - Could be many such instructions.
For simplicity, let us assume the following six operations:
ADD AdditionSUB SubtractMULT MultiplyDIV DivideAND Logical ANDOR Logical OR
26
State diagram for register-register instructions
All very similar form:
MUL/DIV almost certain to require more that one cycle but this is ignored here.
ADD
Rd Rs1 + Rs2
Return to fetch cycle
3
SUB
Rd Rs1 - Rs2
4
AND
RdRs1AND Rs2
7
OR
Rd Rs1 OR Rs2
8
Register-register
Rd Rs1<op>Rs2
3 - 8
For simplicity of drawing state diagram:
27
Register-Constant Instructions
The arithmetic and logic instructions operating upon one register and an immediate constant For simplicity, let us assume the following six operations:
ADDI AdditionSUBI SubtractANDI Logical ANDORI Logical ORSHL Logical shift left (number of places given by constant)SLR Logical shift right (number of places given by constant)
The “I” is used here to indicate immediate addressing.
28
State diagram for register-constant instructions
All very similar form:
ADDI
RdRs1 + IR15-0
Return to fetch cycle
9
SUBI
Rd Rs1 - IR15-0
10
SHL
Rd Rs1<< IR15-0
13
SHR
Rd Rs1 >> IR15-0
14
Register-constant
Rd Rs1<op> IR15-0
9 - 14
For simplicity of drawing state diagram:
29
State Diagram with Load and Store instructions
Register-register Register-constant StoreLoad
Rd Rs1<op>Rs2 Rd Rs1<op>IR15-0 MAR Rs1+IR15-0
MDR[MAR]
Rd MDR
MAR Rs1+IR15-0
MDR Rs2
[MAR]MDR
Return to fetch cycle
3-8 9-14 15
16
17
18
19
20
30
Conditional Branch Instructions
Let us assume the conditional branch instruction of the format:
Bcond, Rs1, L1
(not using a CCR) and the following four operations:
BL Branch if Rs1 less than zeroBG Branch if Rs1 greater than zeroBE Branch if Rs1 equal zeroBNE Branch if Rs1 not equal zero
Question – is that sufficient?
31
Execute Cycle for Branch Instruction
In this case we need to select on of two sets of actions:
• If branch condition true = do actions (alter PC)• If branch condition false, generally do nothing.
PC PC+IR15-0
Rs1 - 0;
ConditionTrue
Yes
No
Fetch sequentialFetch instructioninstructionfrom target address
32
State Diagram of Branch Instructions
All of similar format:
Return to fetch cycle
21
22
BL
i f Rs1 < 0
PC PC+IR15-0
Rs1 0
23
24
BG
i f Rs1 > 0
PC PC+IR15-0
Rs1 0
25
26
BE
i f Rs1 = 0
PC PC+IR15-0
Rs1 0
27
28
BNE
i f Rs1 0
PC PC+IR15-0
Rs1 0
33
State Diagram of Jump Instructions
Return to fetch cycle
29 30 31
32
Jump - PC relative Jump - Reg. indirect JAL
PC PC+IR25-0 PCRs1+ IR15-0 R31 PC
PC PC+IR25-0
34
Could combine states 22, 24, 26, and 28 into one state, and combine states 29 and 32 into one state. However in our design will only combine 29 and 32 to get 32 states in total (0 to 31):
Return to fetch cycle
29
3031
Jump - PC relative Jump - Reg. indirectJAL
PC PC+IR25-0
PCRs1+ IR15-0R31 PC
35
Questions
Next step is to implement state diagrams.