Issues with NoC(Naseef Mansoor)meseec.ce.rit.edu/722-projects/fall2012/2-1.pdf1. Introduction: Why...

Naseef Mansoor

1. Introduction: Why Multi-Core Chips?2. The NoC Paradigm

• Basic Architectures• Layers• Topologies• Performance Metrics.

3. Issues with NoCSwitchingInterconnectsRoutingIssues with WiNoC

Placing the WI’sReliability

Security 4. Summary

Today, we have loads of computation hungry applications.

e.g. • Weather prediction• Astrophysics• Bioinformatics• Language processing• Graphics• Animation

So we need systems with explosive computational power.

As per Moore’s Law we have number of transistor increasing by 2X time in 18 months.

But we are still stuck with 3GHz speed for a single processor. Source: wikipedia

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Power Projections Too High!Power Projections Too High!

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Source: Intel

Scaling up frequency causes soaring power dissipation.

So to keep up with the demands of increasing computational requirements

Increase number of cores (Multi-Core Chips)– parallelism- Intel, AMD dual-core and quad-core CPUs- Custom Systems-on-Chip (SoCs)

Number of cores will increase manifold in the next 5-10 years.

Plus we need to connect these cores.

Initial Attempts:Bus Based Architectures.- Advantage: Simplicity and ease of use- Limitation: With increasing components, a physical

capacitance on the bus wires grows and as a result its wiring delay grows even further.

Solution: Advanced bus architectures - ARM’s� AMBA- OpenCore’s WISHBONE System-on-

Chip (SoC) interconnection- IBM CoreConnect�



3. Issues with NoCSwitchingInterconnectsRoutingWiNoC


Security4. Summary

Limitation to the Bus Architectures:

Problem with Reusability of Design

Solution: Network On Chip. - So we have, “Packet switched

on-chip network”- And “Decoupled functional

block and communication block” or dedicated data transport infrastructure.

Advantage: - Scalable- No complex wiring.

NoC infrastructure

AMBA bus: ARM

High-bandwidthmemory interface

High-performanceARM processor

High-bandwidthARM processor

DMA Busmaster

BRI

DGE

UART

PIOKeypad

TimerAHB APB





Security4. Summary

A simplified NoC contains the following fundamental components1. Network Adapters/Network Interfaces2. Router Nodes/ Switches3. Links4. IP Cores

Liu, Yet al. “Problems on Network-on-Chip”, Conference on Computer Aided Design and Computer Graphics, IEEE 2007.





Security4. Summary

Liu et al. ”Key Problems on Network-on-Chip”, Conference on , Computer Aided Design and Computer Graphics, IEEE 2007.



3. Issues with NoCSwitchingInterconnectsRoutingSecurityWiNoC


4. Summary

Some more regular topologies:- Spin- Cliché- Folded Torus



3. Issues with NoCSwitchingInterconnectsRoutingIssue with WiNoCs


Security4. Summary

Message Throughput:(Total messages successfully completed)x(Message Length)/(Number of IP

blocks x Total time)

Latency: Time difference between injecting a header flit from source and receiving the tail flit at destination.

Energy: Total switch and interconnect energy required for a message on average.

Apart from this Metrics, when comparing two topologies, scalability can be one important factor.



3. Issues with NoCSwitchingRoutingInterconnectsWiNoC


Security4. Summary

NoC’s are packet switched networks.No prior path is setup. Packets are routed by each switch. But the packets increases the storage requirement in the switches.Wormhole Switching:• Divide the messages into smaller fixed length flow

control unit called ‘flits’. • Route the header flit. Rest of the flits follow the same

path.• This reduces the buffer sizes for the switches(area

overhead is less)


• Basic Architectures• Topologies• Layers• Performance Metrics.



Security Issues4. Summary

Deadlock: When two packets are waiting for resources reserved by each other.Starvation: When lower priority packets starve for higher priority packets.Livelock: Packet never reaches destination.

Thankfully we do have algorithms that do so but the problem with the ‘scalability’ of the algorithm. As the system size increase the size of the routing table increases, causing higher area for memory. Solution:

Routing table free routing algorithms e.g. TRAIN



3. Issues with NoCSwitchingRoutingInterconnects

Alternative interconnects WiNoC


Security 4. Summary

-Wires are simply distributed RC Circuits.-The Elmore delay of a wire of length L is nearly 0.4rcL2

-So the delay increase by square of L.-What about energy?-Energy increases in L3

So for multi-hop wired network we have latency and high energy dissipation.

Solution:One possible solution for reducing latency

is to insert repeats or buffers. But this has area overhead.

However a more optimal solution is to use alternative interconnects.

Optical Interconnect -Photonic NoC

3D integration-3D NoC

Wireless/RF interconnect-Wireless NoC

Good with Bandwidth and power because of higher connectivity and lower path length.

Challenges:• For reduced footprints, less surface to dissipate

power.• Layer stacks should be perfectly aligned. So the

fabrication is much complex. • Have a lower chip yield.

Uses high bandwidth on chip photonic link.

Challenges:• Integrating photonic components on chip.• Crosstalk between adjacent photonic

waveguides reduce reliability.

Using the Wireless link gives- High Throughput- Low Energy

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1 Wi-Link 6 Wi-Links 24 Wi-Links 256 core Mesh

Ganguly et al., “Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems”, IEEE Transactions on Computers (TC), 2010.





Security4. Summary

The problem of paths with long hop size with system size can be mitigated by ‘small world’ topology. The network is divided into subnets where we connect the nodes by wire. Then connect this subnets with both wired and wireless links(Hybrid).The Wireless Switches have area overhead of the Transceiver circuit that consist of Antennas and Modulator/Demodulator Circuitry. So we can’t make all the subnets connected wirelessly each other. Then how do we place this WI(Wireless Interface)?Solution:

Place the WI with the help of SA(Simulated Annealing).

µ=average distance in hopsThe probability depends on the particular traffic pattern.

Deb et al. “Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects” , ASAP, 2010.





Security4. Summary

In case of wireless the bandwidth is limited. Which means only one wireless node can use the channel at a time.

Solution: Mechanism(Access Control) for the medium. Like: Token Passing.For multiple access to the channel we can use CDMA. (Lost synchronization between sender can cause error in the data.)





Security4. Summary

Different types of Attacks:• Denial of Service: Aimed to bring down network

performance.Scenarios:

Incorrect Path: Trap a packet in the network to make channels unavailable to the valid messages.Deadlock: Packet with path that disrespect the deadlock free rules.Livelock: Packet that turn infinitely in the network.

• Extraction of Secret Information: Read data from unauthorized secure target.

• Hijacking: Write access to secure area in order to modify system configuration.

• Reverse engineering and extraction of secret information by proximity access.

We can’t have the standard network cipher and authentication technique because of power and area constraint.

Solution:

Evain et al. “From NoC Security Analysis To Design Solutions” IEEE Workshop Signal Processing System Design and Implementation, 2005.

The major problems in future SoC design arises from the non scalable global wire delays.

• Alternate Interconnect technologies exists but still under research.

Reliability and security are important challenges to deal with.

We want Fault Tolerant, Scalable network systems on chip with higher Bandwidth, lower latency and power requirements. This motivates the future and ongoing researches in NoC: (Lot of work ☺)

• Adaptive/Reactive methods to overcome Security threats• Better optimization techniques for architecture design• RF transceiver/Photonic devices design• Lightweight signaling and MAC protocols to improve

performance and reliability of wireless/photonic linksCDMA/SDMA

Issues with NoC(Naseef Mansoor)meseec.ce.rit.edu/722-projects/fall2012/2-1.pdf1. Introduction: Why...

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