IP-QuadUART-485-DSP1 - dyneng.com · The IP-QuadUART-485-DSP1 supports both 8 and 32 MHz. IP Bus...

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Est. 1988

User ManualIP-QuadUART-485-DSP1

Two Channel Manchester Encoded RS-485 I/OIP Module

Revision ACorresponding Hardware: Revision BCorresponding Firmware: Revision A

10-2002-1702

Embedded Hardware and Software Solutions of 26

IP-QuadUART-485-DSP1Two Channel Manchester EncodedRS-485 I/O IP Module

Dynamic Engineering435 Park DriveBen Lomond, CA 95005831-336-8891831-336-3840 FAXwww.dyneng.com

This document contains information of proprietaryinterest to Dynamic Engineering. It has been suppliedin confidence and the recipient, by accepting thismaterial, agrees that the subject matter will not becopied or reproduced, in whole or in part, nor itscontents revealed in any manner or to any personexcept to meet the purpose for which it was delivered.

Dynamic Engineering has made every effort to ensurethat this manual is accurate and complete. Still, thecompany reserves the right to make improvements orchanges in the product described in this document atany time and without notice. Furthermore, DynamicEngineering assumes no liability arising out of theapplication or use of the device described herein.

The electronic equipment described herein generates,uses, and can radiate radio frequency energy.Operation of this equipment in a residential area islikely to cause radio interference, in which case theuser, at his own expense, will be required to takewhatever measures may be required to correct theinterference.

Dynamic Engineering’s products are not authorized foruse as critical components in life support devices orsystems without the express written approval of thepresident of Dynamic Engineering.

This product has been designed to operate with IPModule carriers and compatible user-providedequipment. Connection of incompatible hardware islikely to cause serious damage.

©2000-2005 by Dynamic Engineering.IndustryPack is a registered trademark of GreenSpring ComputersInc.Other trademarks and registered trademarks are owned by theirrespective manufactures.Manual Revision A. Revised January 17, 2006

Embedded Hardware and Software Solutions of 2 6

Table of Contents

Product Description and Operation ................................................................... 5Address Map .................................................................................................... 7Programming .................................................................................................... 8

Register Definitions .................................................................................................................................... 9BASE_CONTROL 9VECTOR 10INTERRUPT STATUS 10CHAN_A,B_CONTROL 11CHAN_A,B_FIFO_DATA 13CHAN_A,B_TEST_DATA 13CHAN_A,B_STATUS 14CHAN_A,B_FFAFL_LVL 15CHAN_A,B_FIFO_COUNT 15TIME_COUNT_LO 16TIME_COUNT_HI 16

Interrupts........................................................................................................................................................ 17ID PROM.......................................................................................................................................................... 18

IP-QuadUART-485-DSP1 Logic Interface Pin Assignment...............................19IP-QuadUART-485-DSP1 IO Interface Pin Assignment ....................................20Applications Guide ...........................................................................................21

Interfacing ...................................................................................................................................................... 21Loop-back Connections ......................................................................................................................... 22Construction and Reliability................................................................................................................ 22Thermal Considerations ....................................................................................................................... 23

Warranty and Repair ......................................................................................23Service Policy ............................................................................................................................................... 23

Out of Warranty Repairs 24For Service Contact:............................................................................................................................... 24

Specifications ..................................................................................................25Order Information............................................................................................26


List of FiguresFIGURE 1 IP-QUADUART-485-DSP1 INTERNAL ADDRESS MAP 7FIGURE 2 IP-QUADUART-485-DSP1 BASE CONTROL REGISTER BIT MAP 9FIGURE 3 IP-QUADUART-485-DSP1 INTERRUPT STATUS BIT MAP 10FIGURE 4 IP-QUADUART-485-DSP1 CHANNEL CONTROL REGISTER BIT MAP 11FIGURE 5 IP-QUADUART-485-DSP1 CHANNEL STATUS REGISTER BIT MAP 14FIGURE 6 IP-QUADUART-485-DSP1 ID PROM 18FIGURE 7 IP-QUADUART-485-DSP1 LOGIC INTERFACE 19FIGURE 8 IP-QUADUART-485-DSP1 IO INTERFACE 20


Product Description and OperationThe IP-QuadUART-485-DSP1 is part of the IP Module family of modular I/Ocomponents. It is based on the IP-QuadUART-485 with the UART and all of the IOremoved except for four RS-485 transceivers. Also the Xilinx FPGA has beenenhanced to an XC2S100.

The module consists of two independent channels that receive Manchesterencoded data consisting of 32-bit words plus one parity bit using RS-485transceivers. Each channel also contains a transmitter to send test data with thesame format. The data is sent lsb first at a 1, 2, 3, or 4 Mbit/sec rate with apreceding 3-bit start/sync pattern and a following parity bit. The default clockrate is 2 Mbit/sec and the parity can be either even or odd controlled by a bit inthe channel control register. The first word of a message has a transition fromhigh to low in the center of the 3-bit sync pattern, bits 8 to 0 are the message IDfield, and bits 17 to 9 are the number of words in the message. This numberincludes the start of message word but not the final word of the message whichis the CRC of the message. Therefore the number of words field will be one lessthan the total number of words in the message. All the words in the messagebesides the first have a transition from low to high in the center of the 3-bit syncpattern.

Each channel’s data is stored in a 1K by 16-bit FIFO as it is received. Thetransmit data is stored in a 256 by 16-bit FIFO and sent by a self-clearing bit inthe channel control register. It is assumed that the transmit FIFO contains asingle complete message, so the first word sent is treated as the first word of amessage and the FIFO data is sent continuously until the FIFO is empty.

A 32-bit counter running at 2 MHz is available to assign time-stamps to receivedmessages. The counter is enabled and cleared by control bits in the base controlregister. The count can be read at any time from two status ports that eachreturn 16-bits of the count. A control bit in the channel control registers enablessaving the time-stamp count for each message to the receive FIFO following themessage data. The count is latched as soon as the start-of-message sync isdetected and that value is written to the receive FIFO after the end of themessage with two successive 16-bit writes. The least significant 16 bits iswritten first followed by the most significant 16 bits


The IP-QuadUART-485-DSP1 supports both 8 and 32 MHz. IP Bus operation.Only the ID, IO, and INT IP spaces are used by the IP-QuadUART-485-DSP1design.

The IP-QuadUART-485-DSP1 conforms to the VITA standard. This guaranteescompatibility with multiple IP Carrier boards. Because the IP may be mounted ondifferent form factors, while maintaining plug and software compatibility, systemprototyping may be done on one IP Carrier board, with final systemimplementation on a different one. The PCI3IP card makes a convenientdevelopment platform in many cases. http://www.dyneng.com/pci_3_ip.html

Interrupts are supported by the IP-QuadUART-485-DSP1. These consist ofmessage received; FIFO almost full; and parity, word-count and framing errorinterrupts for each channel. The interrupt conditions are individually maskable.Channel A interrupt occurs on IntReq0 and channel B interrupt occurs onIntReq1. The vector is user programmable by a read/write register and can beread in the IO space or automatically when the INT space is accessed.


Address Map

Function Offset Width TypeIO spaceBASE_CONTROL 0x00 word read/writeVECTOR 0x02 byte read/writeINT_STATUS 0x04 word read onlyCHAN_A_CONTROL 0x06 word read/writeCHAN_A_FIFO_DATA 0x08 word read/writeCHAN_A_TEST_DATA 0x0A word read/writeCHAN_A_STATUS 0x0C word read/writeCHAN_A_FFAFL_LVL 0x0E word read/writeCHAN_A_FIFO_COUNT 0x10 word read onlyCHAN_B_CONTROL 0x12 word read/writeCHAN_B_FIFO_DATA 0x14 word read/writeCHAN_B_TEST_DATA 0x16 word read/writeCHAN_B_STATUS 0x18 word read/writeCHAN_B_FFAFL_LVL 0x1A word read/writeCHAN_B_FIFO_COUNT 0x1C word read onlyTIME_COUNT_LO 0x1E word read onlyTIME_COUNT_HI 0x20 word read only

FIGURE 1 IP-QUADUART-485-DSP1 INTERNAL ADDRESS MAP

The address map provided is for the local decoding performed within the IP-QuadUART-485-DSP1. The addresses are all offsets from a base address. Thecarrier board that the IP is installed into provides the base address.


ProgrammingProgramming the IP-QuadUART-485-DSP1 requires only the ability to read andwrite data in the host’s I/O space. The IP Carrier board determines the baseaddress of its IP modules. The carrier also supplies the IP clock and othercontrol interface signals including the interrupt connection. See your IP carrieruser manual for information on IP clock speed selection and other pertinentinterface controls.

Each channel has a separate control register to enable the receiver and theindividual interrupt conditions. The transmit test interface is also configured andcontrolled with this register.

If interrupts are to be used, typical sequence would be to first write to the vectorregister with the desired interrupt vector. Please note that some carrier boardsdo not use the interrupt vector. The interrupt service routine should be loadedand the mask set. The desired interrupt conditions enabled and the masterinterrupt enabled.


Register Definitions

BASE_CONTROL0x00 - Base Control Register Port - read/write

Base Control Register

DATA BIT DESCRIPTION

16-6 Spare5 Time count clear, 1 = clear4 Time count enable, 1 = enabled3 Spare2 Force interrupt, 1 = force1 Master interrupt enable, 1 = enabled0 Reset FIFOs, 1 = reset

FIGURE 2 IP-QUADUART-485-DSP1 BASE CONTROL REGISTER BIT MAP

Reset FIFOs: When set to ‘1’, this bit resets the two receive data FIFOs and thetwo transmit test FIFOs. Set to ‘0’ for normal operation.

Master interrupt enable: When set to ‘1’ this bit allows the IP interrupt to beasserted when an enabled interrupt condition occurs. When set to ‘0’, allinterrupts are disabled.

Force interrupt: When set to ‘1’ this bit forces an IP interrupt to occur if themaster interrupt enable is set. Set to ‘0’ for normal operation.

Time count enable: When set to ‘1’, this bit enables the 32-bit time-stampcounter. The counter is running at a 2 MHz rate yielding 500 nanosecondresolution and rolling over in approximately 35 minutes. Set to ‘0’ to disable thecounter.

Time count clear: When set to ‘1’, this bit clears the 32-bit time-stamp counter.Set to ‘0’ to allow normal operation of the counter.

Embedded Hardware and Software SolutionsPage 1 0 of 2 6

VECTOR0x02 - Interrupt Vector Port - read/write

The Interrupt vector for the IP-QuadUART-485-DSP1 is stored in this byte wideregister. This read/write register is initialized to ‘0XFF’ upon power-on reset.The vector is stored in the odd byte location [D7..0]. The vector should beinitialized before the interrupt is enabled or the mask is lowered.

INTERRUPT STATUS0x04 - Interrupt Status Port - read only

Interrupt Status


15-12 Xilinx design revision11-6 spare

5 Interrupt B 1 = request active4 Interrupt A 1 = request active3 Spare2 INTR1 1 = active1 INTR0 1 = active0 Interrupt request 1 = active

FIGURE 3 IP-QUADUART-485-DSP1 INTERRUPT STATUS BIT MAP

Interrupt request: When a ‘1’ is read, this bit indicates that an IP interrupt hasbeen requested. This will result in an interrupt being driven off the card if themaster interrupt enable is set to a ‘1’.

INTR0: When a ‘1’ is read, this bit indicates that IP interrupt 0 has beenasserted.

INTR1: When a ‘1’ is read, this bit indicates that IP interrupt 1 has beenasserted.

Interrupt A, B: When a ‘1’ is read, this bit indicates that an enabled interruptcondition for channel A or B respectively has occurred. This will result in aninterrupt being driven off the card provided the master interrupt enable is set to a


‘1’.

Xilinx design revision: These four bits encode the current revision of the Xilinxdesign. Currently the value should be 0x1, which represents revision A.

CHAN_A,B_CONTROL0x06, 0x12 - Channel Control Register Ports - read/write

Channel Control Register


15,14 Spare13 Save time-stamp enable12 FIFO loop-back test enable11 Test data send command10 Test data transmitter enable

9 Reset channel FIFOs, 1 = reset8 Parity select (1=odd parity, 0=even parity)7 Word-count error interrupt enable6 Framing error interrupt enable5 Parity error interrupt enable4 Receive FIFO almost full interrupt enable3 Received message interrupt enable2 Enable data receiver

0,1 Bit-rate select (0=2 Mbps)

FIGURE 4 IP-QUADUART-485-DSP1 CHANNEL CONTROL REGISTER BIT MAP

Bit-rate select: These two bits select the frequency that data is received and sentout of the module. When “00” this rate is 2 Mbits/second, when “01” it is 1Mbits/second, when “10” it is 3 Mbits/second, and when “11” the rate is 4Mbits/second.

Enable data receiver: When set to ‘1’, this bit enables the receiver to start lookingfor a data word. When set to ‘0’ data reception is disabled.

Data interrupt enable: When set to ‘1’ this bit allows an interrupt to be assertedwhen a complete message has been received. As with all the interrupts enablesin this register, the master interrupt enabled must be asserted for the interruptto be driven off the card. When set to ‘0’, the data interrupt is disabled.


Receive FIFO almost-full interrupt enable: When this bit is set to a ‘1’, an interruptis allowed to occur when the number of data-words in the receive FIFO is equal orgreater than the value entered in the FIFO almost full level register. When set to‘0’ the almost full interrupt is disabled..

Parity error interrupt enable: When this bit is set to a ‘1’, an interrupt is allowedto occur when a parity error is detected in a received data word. When set to ‘0’the parity error interrupt is disabled.

Framing error interrupt enable: When this bit is set to a ‘1’, an interrupt isallowed to occur when a framing error is detected in a received data word.When set to ‘0’ the framing error interrupt is disabled. A framing error occurswhen the received data word does not contain the correct number of bits or if thebit timing is incorrect.

Word-count error interrupt enable: When this bit is set to a ‘1’, an interrupt isallowed to occur when a word-count error is detected in a received datamessage. When set to ‘0’ the word-count error interrupt is disabled. A word-count error occurs when the number of received data words in a message doesnot match the value in the number of words field of the first message word.

Parity select: When set to ‘1’, odd parity is used for both the transmitter and thereceiver to calculate the parity bit at the end of each data-word. When set to ‘0’,even parity is used.

Reset channel FIFOs: When set to ‘1’, this bit resets the receive data FIFO andthe transmit test FIFO for the appropriate channel. Set to ‘0’ for normaloperation.

Test data transmitter enable: When set to ‘1’, this bit enables the transmitter tobe used to send data for test purposes. When set to ‘0’ the data transmitter isdisabled.

Test data send command: When a ‘1’ is written to this bit, the contents of thetest data FIFO will be sent out from the transmitter. The bit will be clearedautomatically at the end of the transmission and can be monitored as anindication that this event has completed.


FIFO loop-back test enable: When set to ‘1’, this bit enables reading from thetransmit FIFO and writing to the receive FIFO to allow FIFO data loop-backoperation for test purposes. When set to ‘0’, normal IO operation is enabled.

Save time-stamp enable: When set to ‘1’, this bit enables writing 32-bits of time-stamp data at the end of each received message. The time-stamp data is latchedin a register as soon as a start-of-message word sync is detected and then thatvalue is appended to the message data in the receive FIFO. When set to ‘0’,time-stamp data is not appended to the FIFO data.

CHAN_A,B_FIFO_DATA0x08, 0x14 - FIFO Data Port – read/write

The received data is read from this FIFO port. When the FIFO loop-back testenable bit is set, FIFO data can also be written to this port.

CHAN_A,B_TEST_DATA0x0A, 0x16 - FIFO Data Port – read/write

The test data is written to this FIFO port before being sent out for IO loop-backtesting. When the FIFO loop-back test enable bit is set, FIFO test data can alsobe read from this port.


CHAN_A,B_STATUS0x0C, 0x18 - Channel Status Ports - read/write

Channel Status Register


15-11 spare10 Tx FIFO data valid

9 Tx FIFO full8 Tx FIFO empty7 Rx FIFO almost full6 Rx FIFO data valid5 Rx FIFO full4 Rx FIFO empty3 Word-count error detected2 Framing error detected1 Parity error detected0 Message received

FIGURE 5 IP-QUADUART-485-DSP1 CHANNEL STATUS REGISTER BIT MAP

Message received: When ‘1’ is read it indicates that a complete message hasbeen received. This bit is latched until cleared by writing back a ‘1’ to the samebit position.

Parity error detected: When ‘1’ is read it indicates that a parity error has beendetected in a received word. This bit is latched until cleared by writing back a ‘1’to the same bit position.

Framing error detected: When ‘1’ is read it indicates that a framing error hasbeen detected in a received word. A framing error occurs when the number ofbits in a received word is incorrect. This bit is latched until cleared by writingback a ‘1’ to the same bit position.

Word-count error detected: When ‘1’ is read it indicates that a word-count errorhas been detected in a received message. A word-count error occurs when thenumber of words in a received message does not match the count specified inthe first word. This bit is latched until cleared by writing back a ‘1’ to the samebit position.


Rx FIFO empty: When ‘1’ is read it indicates that the received data FIFO is empty.

Rx FIFO full: When ‘1’ is read it indicates that the received data FIFO is full.

Rx FIFO data valid: The first word written into the FIFO is immediately read so thatit is available to the output data bus. When ‘1’ is read for this bit it indicates thatthere is at least one data word to read. As the data is read out of the FIFOeventually it will indicate that it is empty, but there will be one more valid word toread as indicated by this bit.

Rx FIFO almost full: When ‘1’ is read it indicates that the received data FIFO isalmost full as determined by the count entered into the receive FIFO almost fulllevel register.

Tx FIFO empty: When ‘1’ is read it indicates that the test data FIFO is empty.

Tx FIFO full: When ‘1’ is read it indicates that the test data FIFO is full.

Tx FIFO data valid: The first word written into the FIFO is immediately read so thatit is available to transmitter state machine. When ‘1’ is read for this bit itindicates that there is at least one data word left to send. As the data is sent outof the FIFO eventually it will indicate that it is empty, but there will be one morevalid word to send as indicated by this bit.

CHAN_A,B_FFAFL_LVL0x0E, 0x1A - FIFO Data Level Port – read/write

The value written to this register determines when the receive FIFO almost fullstatus is asserted. This value represents the number of 16-bit words in the FIFOthat will cause the almost full status to be true.

CHAN_A,B_FIFO_COUNT0x10, 0x1C - FIFO Data Count Port – read only

The value read from this port represents the number of 16-bit words currently inthe receive FIFO.


TIME_COUNT_LO0x1E – Time-stamp Data Low-Word Port – read only

The value read from this port represents the least significant 16-bits of thecurrent time count.

TIME_COUNT_HI0x20 - Time-stamp Data High-Word Port – read only

The value read from this port represents the most significant 16-bits of thecurrent time count.


InterruptsAll IP Module interrupts are vectored. The vector from the IP-QuadUART-485-DSP1 comes from a vector register loaded as part of the initialization process.The vector register can be programmed to any 8-bit value. The default value is0xFF which is sometimes not a valid user vector. The user is responsible forchoosing a valid vector value.

The IP-QuadUART-485-DSP1 state machines generate an interrupt request whena programmed condition is detected on the IO lines. The interrupt is mapped tointerrupt request 0 for channel A and interrupt request 1 for channel B. TheCPU will respond by asserting INT. The hardware will automatically supply theappropriate interrupt vector when accessed by the CPU. The interruptingchannel can be read from the interrupt status register. There are five interruptconditions for each channel: Rx message received, Rx data parity error, Rx dataframing error, Rx data word-count error, and Rx FIFO almost full. If more thanone type of interrupt is in use, then the channel status register should be readfirst to determine which interrupt cause is active. The exception handler can thenrespond to all of the current interrupt requests.

The interrupt level seen by the CPU is determined by the IP Carrier board beingused. The master interrupt can be disabled or enabled through the BASE_CNTLregister and the individual interrupts can be disabled or enabled through theCHAN_A,B_CONTROL registers. These enables operate after the interrupt statuslatches. The Interrupt acknowledge cycle fetches the vector, but does not clearthe latched interrupt requests in this design.

If operating in a polled mode and making use of the interrupts for status then themaster interrupt should be disabled.


ID PROMEvery IP contains an ID PROM, whose size is at least 32 x 8 bits. The ID PROMaids in software auto configuration and configuration management. The user’ssoftware, or a supplied driver, identifies the installed devices by reading the IDPROM. The ID PROM contains the manufacturing revision level of the IP. If adriver requires a particular revision to be present, it may check for it directly.

The location of the ID PROM in the host’s address space is dependent on thecarrier used.

Standard data in the ID PROM on the IP-QuadUART-485-DSP1 is shown in thefigure below. For more information on IP ID PROMs refer to the IP Module LogicInterface Specification, available from Dynamic Engineering.

Each of the modifications to the IP-QuadUART-485 board will be recorded with anew code in the DRIVER ID and reserved fields.

Address Data

01 ASCII “I” $4903 ASCII “P” $5005 ASCII “A” $4107 ASCII “H” $4809 Manufacturer ID $1E0B Model Number $070D Revision $A00F reserved $0911 Driver ID, low byte $0313 Driver ID, high byte $0015 No of extra bytes used $0C17 CRC $0E

FIGURE 6 IP-QUADUART-485-DSP1 ID PROM


IP-QuadUART-485-DSP1 Logic Interface PinAssignmentThe figure below gives the pin assignments for the IP Module Logic Interface onthe IP-QuadUART-485-DSP1. Pins marked n/c below are defined by thespecification, but not used on the IP-QuadUART-485-DSP1. Also see the UserManual for your carrier board for more information.

GND GND 1 26CLK +5V 2 27

Reset* R/W* 3 28D0 IDSEL* 4 29

D1 DMAReq0* 5 30D2 MEMSEL* 6 31

D3 DMAReq1* 7 32D4 IntSel* 8 33

D5 DMAck* 9 34D6 IOSel* 10 35

D7 n/c 11 36D8 A1 12 37

D9 DMAEnd* 13 38D10 A2 14 39

D11 n/c 15 40D12 A3 16 41

D13 IntReq0* 17 42D14 A4 18 43

D15 IntReq1* 19 44BS0* A5 20 45

BS1* n/c 21 46n/c A6 22 47

n/c Ack* 23 48+5V n/c 24 49

GND GND 25 50

NOTE 1: The no-connect signals above are defined by the IP Module Logic Interface Specification, but notused by this IP. See the Specification for more information.

NOTE 2: The layout of the pin numbers in this table corresponds to the physical placement of pins on theIP connector. Thus this table may be used to easily locate the physical pin corresponding to a desiredsignal. Pin 1 is marked with a square pad on the IP Module.

FIGURE 7 IP-QUADUART-485-DSP1 LOGIC INTERFACE


IP-QuadUART-485-DSP1 IO Interface Pin AssignmentThe figure below gives the pin assignments for the IP Module IO Interface on theIP-QuadUART-485-DSP1.

RXA+ n/c 1 26RXA- n/c 2 27

TSTA+ n/c 3 28TSTA- n/c 4 29

n/c n/c 5 30n/c n/c 6 31

n/c n/c 7 32n/c n/c 8 33

n/c n/c 9 34n/c n/c 10 35

n/c n/c 11 36n/c n/c 12 37

RXB+ n/c 13 38RXB- n/c 14 39

TSTB+ n/c 15 40TSTB- n/c 16 41

n/c n/c 17 42n/c n/c 18 43

n/c n/c 19 44n/c n/c 20 45

n/c n/c 21 46n/c n/c 22 47

n/c n/c 23 48n/c gnd 24 49

n/c gnd 25 50

NOTE 1: The layout of the pin numbers in this table corresponds to the physical placement of pins on theIP connector. Thus this table may be used to easily locate the physical pin corresponding to a desiredsignal. Pin 1 is marked with a square pad on the IP Module. Unused pins should not be connected.

FIGURE 8 IP-QUADUART-485-DSP1 IO INTERFACE


Applications Guide

InterfacingSome general interfacing guidelines are presented below. Do not hesitate tocontact the factory if you need more assistance.

Watch the system grounds. All electrically connected equipment should have afail-safe common ground that is large enough to handle all current loads withoutaffecting noise immunity. Power supplies and power-consuming loads should allhave their own ground wires back to a common point.

Keep cables short. Flat cables, even with alternate ground lines, are not suitablefor long distances. The IP-QuadUART-485-DSP1 does not contain special inputprotection.

We provide the components. You provide the system. Only careful planning andpractice can achieve safety and reliability. Integrated circuits can be damaged bystatic discharge. Proper anti-static handling procedures must be followed.

Terminal Block. We offer a high quality 50-screw terminal block that directlyconnects to the flat cable. The terminal block mounts on standard DIN rails.[http://www.dyneng.com/HDRterm50.html ]

Many flat cable interface products are available from third party vendors to assistyou in your system integration and debugging. These include connectors, cables,test points, 'Y's, 50 pin in-line switches, breakout boxes, etc.

IndustryPacks® are mezzanine cards which require an adapter to work in anysystem. IP Modules are commonly used and frequently systems have “extra”slots where the modules can be located. Dynamic Engineering has carriers forthe PCI, PC104p, and cPCI buses. IndustryPacks are portable and can be usedon third party carriers when the hardware is compliant with the IP specification.http://www.dyneng.com/pci_3_ip.htmlhttp://www.dyneng.com/pci5ip.htmlhttp://www.dyneng.com/cpci2ip.htmlhttp://www.dyneng.com/cpci4ip.htmlhttp://www.dyneng.com/pc104p_ip.htmlhttp://www.dyneng.com/pc104p4ip.html


Different platforms have different operating system requirements. If you need adriver please contact Dynamic Engineering. Dynamic Engineering has driverexpertise for Windows NT, 2000, and XP. Dynamic Engineering also writesdrivers for Linux and has plans for VxWorks and Labview. We can support youreffort with driver and application software or help for your software designers.Dynamic Engineering hardware designs have features to help the integrator towrite and test their software quickly and efficiently – we can help you.

Loop-back ConnectionsThe ATP software we use to test the IP-QuadUART-485-DSP1 includes loop-backtests. The Engineering Kit for the IP-QuadUART-485-DSP1 includes the sourcecode for the ATP. The loop-back test is facilitated with an IP-Debug-IO card withadded wire-wrapped interconnections.

Channel A

Pin1 to Pin3

Pin2 to Pin4

Channel B

Pin13 to Pin15

Pin14 to Pin16

Construction and ReliabilityIP Modules were conceived and engineered for rugged industrial environments.The IP-QuadUART-485-DSP1 is constructed out of 0.062 inch thick FR4 material.

Through hole and surface mounting of components are used. IC sockets use highquality plated screw machine pins. High insertion and removal forces arerequired, which assists in the retention of components. If the application requiresunusually high reliability or is in an environment subject to high vibration, the usermay solder the corner pins of each socketed IC into the socket, using a groundedsoldering iron.


The IP Module connectors are keyed and shrouded with Gold plated pins on bothplugs and receptacles. They are rated at 1 Amp per pin, 200 insertion cyclesminimum. These connectors make consistent, correct insertion easy andreliable.

The IP is secured against the carrier with four metric M2 stainless steel screws.The heads of the screws are countersunk into the IP. The four screws providesignificant protection against shock, vibration, and incomplete insertion. For mostapplications, they are not required. Dynamic Engineering IndustryPack Modulesare shipped with a mounting kit. [IP-MTG-KIT is available if you misplace themounting hardware or if another IP was not shipped with the standoffs andscrews]

The IP Module provides a low temperature coefficient of 0.89 W/oC for uniformheat. This is based upon the temperature coefficient of the base FR4 material of0.31 W/m-oC, and taking into account the thickness and area of the IP. Thecoefficient means that if 0.89 Watts are applied uniformly on the componentside, then the temperature difference between the component side and solderside is one degree Celsius.

Thermal ConsiderationsThe IP-QuadUART-485-DSP1 design consists of CMOS circuits. The powerdissipation due to internal circuitry is very low. It is possible to create higherpower dissipation with the externally connected logic. If more than one Watt isrequired to be dissipated due to external loading then forced-air cooling isrecommended. With the one degree differential temperature to the solder sideof the board external cooling is easily accomplished.

Warranty and RepairPlease refer to the warranty page on our website for the current warranty offeredand options.

http://www.dyneng.com/warranty.html

Service PolicyBefore returning a product for repair, verify as well as possible that thesuspected unit is at fault. Then call the Customer Service Department for a


RETURN MATERIAL AUTHORIZATION (RMA) number. Carefully package the unit,in the original shipping carton if this is available, and ship prepaid and insured withthe RMA number clearly written on the outside of the package. Include a returnaddress and the telephone number of a technical contact. For out-of-warrantyrepairs, a purchase order for repair charges must accompany the return.Dynamic Engineering will not be responsible for damages due to improperpackaging of returned items. For service on Dynamic Engineering Products notpurchased directly from Dynamic Engineering contact your reseller. Productsreturned to Dynamic Engineering for repair by other than the original customerwill be treated as out-of-warranty.

Out of Warranty RepairsOut of warranty repairs will be billed on a material and labor basis. The currentminimum repair charge is $100. Customer approval will be obtained beforerepairing any item if the repair charges will exceed one half of the quantity one listprice for that unit. Return transportation and insurance will be billed as part ofthe repair and is in addition to the minimum charge.

For Service Contact:Customer Service DepartmentDynamic Engineering

435 Park Dr.Ben Lomond, CA 95005831-336-8891831-336-3840 faxe-mail [email protected]


SpecificationsLogic Interface: IP Module Logic Interface

Features: 2 RS-485 Receivers and 2 RS-485 Transmitters

Software Interface: Control Registers, Status Ports, ID PROM, Vector Register

Initialization: Hardware Reset forces all registers except Vector Register to 0.

Access Modes: Word in I/O Space (see memory map)Word in ID SpaceVectored interrupt

Access Time: back-to-back cycles in 500 ns (8MHz.) or 125 ns (32 MHz.)

Wait States: 1 to all spaces

Interrupt: Data received, parity, word-count, and framing error interrupts and FIFOalmost full interrupt for each channel

DMA: No Logic Interface DMA Support implemented at this time.

Onboard Options: All Options are Software Programmable

Interface Options: 50 pin flat cable50 screw terminal block interface [HDRterm50]User cable

Dimensions: Standard Single IP Module. 1.8 x 3.9 x 0.344 (max.) inches

Construction: FR4 Multi-Layer Printed Circuit, Through Hole and Surface MountComponents. Programmable parts are socketed.

Temperature Coefficient: 0.89 W/oC for uniform heat across IP

Power: Typical 52 mA @ 5V unloaded. Additional current will be requireddepending on the loads applied


Order InformationTools for IP-QuadUART-485-DSP1: IP-Debug-Bus - IP Bus interface extender with

testpoints, isolated power & quickswitch technology to allowhot swapping or power cycling without powering down thehost.http://www.dyneng.com/ipdbgbus.html

IP-Debug-IO II - IndustryPack IO connector breakout withtestpoints, ribbon cable headers, and locations for usercircuits. http://www.dyneng.com/ipdbgio.html

HDRterm50 - Ribbon cable compatible 50 pin header to 50screw terminal header. Comes with DIN rail mountingcapability. http://www.dyneng.com/HDRterm50.html

HDRribn50 – Ribbon cable in several standard lengths pluscustom, with strain relief and cable pull attached.http://www.dyneng.com/HDRribn50.html

PCI3IP - 1/2 length PCI card with 3 IP slots.http://www.dyneng.com/pci_3_ip.html

PCI5IP - PCI card with 5 IP slots.http://www.dyneng.com/pci5ip.html

cPCI2IP - cPCI card with 2 IP slots.http://www.dyneng.com/cpci2ip.html

IP-MTG-KIT – 4 metric stainless screw and stand-off pairs toretain IP-QuadUART-485-DSP1 against the carrier board.Flat head screws match IP Specification mountingrequirements.http://www.dyneng.com/IPHardware.html

All information provided is Copyright Dynamic Engineering

IP-QuadUART-485-DSP1 - dyneng.com · The IP-QuadUART-485-DSP1 supports both 8 and 32 MHz. IP Bus...

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