IP Powering the Future of AI and Automotive Designs

October 2019

IP Powering the Future of AI and Automotive Designs

© 2019 Synopsys, Inc. 2Synopsys Confidential Information

SoCs Across All Markets Will Include AI

M O B I L E

All Premier

Smartphones will

integrate AI

Processing

Capabilities by

2021

D ATA C E N T E R

More than 50% of

enterprises will

deploy AI

accelerators in

their server

infrastructure by

2022

I O T

More than 20% of

IoT devices will have

AI processing

Capabilities by 2022

A U TO M O T I V E

Volume production

of autonomous

vehicles will begin

in 2020


-$ $500 $1000 $1500 $2000 $2500 $3000

Artificial Intelligence Revenue, Top 10 Use Case, World Markets 2025

Contract Analysis

AI Market Projection to $36.8B by 2025

Object and classification – avoidance , navigation

Object identification, detection, classification,

tracking from geospatial images

Automated geophysical feature detection

Text query of image

Content distribution on social media

Predictive maintenance

Efficient, Scalable processing of patient data

Static image recognition, classification and tagging

Algorithmic trading strategy performance improvement

Source: Tractica

© 2019 Synopsys, Inc. 4

Market Growth for Automotive SoCs

10.3% CAGR from 2015 to 2020*

Source: *IC Market Drivers 2017, IC Insights, 2016,

**Trends and Opportunities in Driver Assistance and

Automated Driving, IHS Automotive Sep 2015

0

5

10

15

20

25

30

35

40

2014 2015 2016 2017 2018 2019 2020

Billio

ns (

$)

2014-2020F Automotive IC Market*

Synopsys Confidential Information

Park Assist

Night Vision

Driver Monitoring

Autonomous Park Assist

Adaptive Cruise Control

Collision Warning/ Avoidance

Blind Spot Detection

Lane Departure Warning

Traffic Sign Recognition

Surround-View Systems

0% 5% 10% 15% 20% 25% 30%

Camera-dominant or camera-only applicationsSource: IHS © 2015 IHS

ADAS System Unit Production CAGR 2014 - 2021

ADAS: Fastest Growing Application: 25% CAGR ‘14-21

• Camera-dominant or camera-only applicationsGrowth

Drivers


Defining Artificial Intelligence

Artificial IntelligenceMimics human behavior

Machine LearningUses advanced statistical algorithms to improve AI

Deep LearningLearning based not task-specific algorithms

Convolutional

Neural Networks

Recurrent

Neural Networks

Deep Neural Networks (DNNs)

• Artificial Intelligence mimics

cognitive functions such as

problem solving & learning

• Machine Learning analyzes

large amounts of data to infer

patterns & results

• Deep learning is a

specialized subset of

machine learning using

artificial neural networks



What About a Deep Neural Network?

“Hey Google. How Can

Synopsys IP Help me

With My AI Design?

Google’s LSTM1 Voice

Recognition Model


What About a Deep Neural Network?

Google’s LSTM1 Voice

Recognition Model

• 56 Layers

• 34 million weights

~19 billion operations

per guess…


61

13812

25 45 60

7

2432

0

24

4

44

9 1420 32

3

7

50

55

60

65

70

75

80

85

100 1000 10000

% A

ccura

cy T

op 1

Million Multiplications

AlexNet

VGG16

ResNEt

Inception

MobileNet

DenseNet

MobileNet V2

Deep Learning Algorithm TradeoffsHighest Accuracy Does Not Always Mean Most Efficient

#Millions of weights (coefficients) to be

transferred from DDR memory


ARTIF ICIAL

INTELLIGENCE

Deep Learning SoC Challenges

Specialized Processing

System Connectivity

Security & Functional Safety

Memory Performance

Unique Requirements


Specialized Processor Options

Vision CPU (1/2/4 cores) CNN Engine (scalable)

AXI Interconnect

EV6x Embedded Vision Processor

Shared MemorySync & Debug Streaming Transfer Unit

Libraries

(OpenCV) & API

(OpenVX)

Simulators

(fast NSIM, EV

VDK)

Compilers /

Debuggers (C/C++,

OpenCL C)

MetaWare EV Software

CNN

Mapping

Tool

Core 4

Core 3

Core 2

Core 1

32-bit

scalar

512-bit

vector DSP

VFPU

3520 MAC Engine

1760 MAC Engine

880 MAC Engine

Convolution

Conv. 2D

Classification

Conv. 1D

SFPU

Efficiency of HW w/ full SW programmability

Unlimited design flexibility

Programmable vision cores + CNN Engine

Software works within standard toolchains

EV6x Embedded Vision Processor IP Custom Processor w/ASIP Designer


HPC Kit Enhanced for AI Applications

EV61 + CNN w/o HPC Kit w/ HPC Kit% Difference

Post Route

Frequency Met 500MHz Frequency target

Core Area Same core area

Normalized Power 1.000 0.614 -38.6%

EV61 + CNN w/o HPC Kit w/ HPC Kit% Difference

Post Route

Frequency 760 811 +6.7%

Normalized Power 1.000 0.715 -28.5%

Core Area Same core area


Special Cells introduced to reduce CNN engine’s

power consumption up to 39%

Special Tradeoff tuning enables 7% frequency

boost with 28% lower power


ARTIF ICIAL

INTELLIGENCE


System Connectivity

Security & Functional

Safety

Memory Performance

Unique Requirements



Deep Learning Memory Options

LPDDR4X LPDDR5 DDR4/5 HBM2/2E GDDR5/5X GDDR6

Typical

Interface

Dual 16-bit,

32-bit channel

Quad 16 bit

channels

(64 bits total)

Dual 32+8 bit

channels

(64+16 bits total)

Octal 128 bit

channels

(1024 bits total)

32 bits

Dual 16-bit

channels

(32 bits total)

Max Pin

Bandwidth4.2Gb/s 6.4Gb/s

6.4Gb/s

(DDR5)2.4 → 3.2Gb/s 12Gb/s 18Gb/s

Max interface

Bandwidth34.1GB/s 51GB/s 51GB/s 307 → 409GB/s 48GB/s 72GB/s

Max Capacity 8GB 8GB3DS RDIMM

256GB

8H Stack 8GB

→ 16GB1GB 1GB

Power

(mW/Gb)~2 ~8

Interface

voltage0.6v 0.5V / 0.3V 1.1V (DDR5) 1.2V 1.5V / 1.35V 1.35V / 1.25V



ARTIF ICIAL

INTELLIGENCE


System Connectivity


Safety

Memory Performance

Unique Requirements



PCI Express 5.0 IP for AI DesignsProven in AI Applications with Customers in Silicon

32 Gb/s

Multi-Protocol 32G & PCIe

5.0 TX Eye

Multi-Protocol 32G & PCIe

5.0 RX Eye

• Built on proven

512-bit architecture

• 1GHz timing

closure with 32b

PIPE x16 lanes

• Implements 64-bit

interface supported

by PIPE 5.1.1

• PHY performance:

>36dB @ 16 GHz

Nyquist

• Multi-protocol with

lane independence

• Up to 16-lane hard

macro

• Low latency, high

throughput

• Support for cache

coherency via CCIX

• Prioritized traffic to

intelligently manage

data flow via

multiple VCs &

Traffic Classes

PCIe 5.0 Controllers PCIe 5.0 PHY Key for AI



New CXL ProtocolAllows CPUs and Accelerators to Access Each Other’s Memory

• CXL dynamically multiplexes three protocols

onto a single link

– CXL.io – PCIe repackaged for high bandwidth,

– CXL.cache – an “agent” coherence protocol

– CXL.mem – a memory access protocol

• Intel defines multiple profiles that are

combinations of CXL.io, CXL.cache, CXL.mem

• CXL uses PCIe electricals and connectors, and

PCIe can operate on the same interfaces

• Future Intel CPUs will support PCIe 5.0 & CXL

PCIe Gen5 PHY

Logical PHY

Mux

CXL.io CXL.cache/mem

Accelerator Logic

PIPE 5.X

CXL

Device-Side

Soft IP

IO (PCIe) Cache Memory

Accelerator


Challenges: Supporting Multiple Display StandardsVESA DSC Interface Simplifies Integration

Video Source Device

HDMI Integration

DP Integration

DSI Integration

Display Port 1.4 TX Cntrl. TX

PH

Y

DP

IF

TX P

HY

HDMI 2.1 TX Cntrl.

HD

MI I

F

DSC Integration

DSC Integration

DSC Integration

DSC

IFD

SC IF

DSC

IF

VESA DSC 1.2a

Encoder

VESA DSC 1.2a

Encoder

VESA DSC 1.1

Encoder

So

C L

og

ic

• Synopsys pre-integrates

Display Controllers with

DSC Encoder

• Designers can focus on

integrating common VESA

DSC Interface into their SoC

Logic

Common DSC Interface

Pre-Integrated

MIPI DSI 2.0 Host

Cntrl. TX P

HY

DSI

IF


ARTIF ICIAL

INTELLIGENCE


System Connectivity


Safety

Memory Performance

Unique Requirements



Requirements of Functional Safety in Automotive ICsDriving the Need for Comprehensive Functional Safety Solutions

Meeting quality levels required

for automotive applications

AEC-Q100 qualification of

SoCs (Grade 1, Grade 2)

ASIL Requirements

QM, A, B, C, D

Reliability

Quality

Functional

Safety Design

Procedures

System

Requirements

Documentation

& Organization

Power-On/Off

Self Test

Periodic Test for

Mission Mode

Failure

Escalations

Functional

Safety


How Synopsys Addresses Key Requirements of Functional

Safety Systems

• Safety Manager: ARC EM Safety

Islands manages periodic & mission

mode testing

• Safety Network & Test Interface:

DesignWare SHS drives testing of

logic, interfaces, analog/mixed-signal

and PLLs

• Certification: The Functional Safety

Solution is ASIL-D Ready Certified &

ISO26262 Chapter 5 (HW Dev)

Certified

Safety

Manager

JTAG

TAP

Safety

Network

with

Test

interface

Safety

Network

Safety

Network

Digital

Safety

Network

Memory

Interface IP PHY

Safety Network

Safety Bus


Securing Deep Learning SoCs

• Narrow AI today, room for improvement

– Adversarial Attacks are Threat

• AI Models

– Expensive; Updates required

• AI applications use private data

– Facial Recognition; Biometrics

• Integrity of the model:

– Model corruption by nefarious agents

– Corrupted models behave poorly

• Trusted Execution Environment with DesignWare IP

secures neural network SoCs for AI applications

Secure authentication, data encryption, key management, platform security & content protection


In Closing…

© 2019 Synopsys, Inc. 23© 2019 Synopsys, Inc. 23Synopsys Confidential Information

• ARC & EV Processors,

ASIP Designer, and

Foundation Cores for

Specialized processors

• HBM2, LPDDR, and

Embedded Memories

for optimized memory

performance

• Portfolio of silicon-

proven interface IP for

real-time-data

connectivity

Addressing the Critical Building Blocks of AI

DesignWare IP Portfolio for AI SoCs

Pre & Post Processing& DL Acceleration

High Speed Bandwidth Low pJ/bit

Chip-to-chipbandwidth

CMOS SensorInterface

Complete Scalar, Vector, CNN engines

Low Power DRAM

Chip-to-Chip Cache Coherency

Cloud Connectivity

HBM2 LPDDR

PCI Express

CCIX / CXL

MIPI CSI-2 &

I3C

Ethernet

Foundation

Cores

ARC EV

Processors

Memories and Logic Libraries

ASIP

Designer

ARC EM & HS

Processors

Flexible Deep Learning Math Primitives

Custom Deep Learning Processors

Near Threshold LibrariesMulti-Port Memories


INUIT IVE ADOPTS

DESIGNWARE EMBEDDED

VISION PROCESSOR

Supporting Customers Across AI ApplicationsAccelerating Development of Automotive & AI System-on-Chip Designs

HABANA LABS ACHIEVES

FIRST-PASS SUCCESS

FOR AI SOC

FABU SELECTS

DESIGNWARE IP FOR

INTELLIGENT ADAS SOC

“Our ADAS and autonomous vehicle chip

uses DesignWare IP to help us integrate

intelligent functionality into our SoC and

accelerate the path to achieving system-

level ISO 26262 compliance.”

Hang Nguyen

CTO, R&D Division

“After an extensive evaluation process, we

selected Synopsys' leading 16 GT/s

DesignWare IP for PCI Express 4.0 due to

its established track record in the industry

and advanced features…”

Eitan Medina

Chief Business Officer

“The competitive PPA advantages of the

DesignWare EV62 processor were critical

to achieving the real-time processing

capabilities of our NU4000 3D imaging &

vision processor SoC.”

Dor Zepeniuk

Vice President of R&D


Thank You

IP Powering the Future of AI and Automotive Designs

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