* Microprocessor Systems I/O System Design

*IntroductionI/O devices serve two main purposesTo communicate with outside worldTo store dataI/O controller acts as an interface between the systems bus and I/O deviceRelieves the processor of low-level detailsTakes care of electrical interfaceI/O controllers have three types of registersDataCommandStatus

*Introduction (contd)

*Introduction (contd)To communicate with an I/O device, we needAccess to various registers (data, status,)This access depends on I/O mappingTwo basic waysMemory-mapped I/OIsolated I/OA protocol to communicate (to send data, )Three typesProgrammed I/ODirect memory access (DMA)Interrupt-driven I/O

*Accessing I/O DevicesI/O address mappingMemory-mapped I/OReading and writing are similar to memory read/write Uses same memory read and write signalsMost processors use this I/O mappingIsolated I/OSeparate I/O address spaceSeparate I/O read and write signals are neededPentium supports isolated I/O64 KB address spaceCan be any combination of 8-, 16- and 32-bit I/O portsAlso supports memory-mapped I/OMemoryaddressingspaceI/OaddressingspaceI/OMemory addressingspace00000FFFFF0000FFFF00000FFFFFDirect I/OMemory-mapped I/O

*Accessing I/O Devices (contd)Accessing I/O ports in 80x86Register I/O instructionsin accumulator, port8 ; direct formatUseful to access first 256 portsin accumulator,DX ; indirect formatDX gives the port address

*8086/88 Port Addressing Space Addressing SpaceFFFF000000F800FFAccessed directly byinstructionsAccessed throughDX Accessing directly by instructionsIN AL, 80HIN AX, 6HOUT 3CH, ALOUT 0A0H, AX Accessing through DXIN AL, DXIN AX, DXOUT DX, ALOUT DX, AX

*Input Port Implementation8086/88Data BusAddress busDecoderInputGating deviceOther control signals The outputs of the gating device are high impedance when the processor is not accessing the input port When the processor is accessing the input port, the gating device transfers input data to CPU data bus The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus

*Input Port Implementation Circuit Implementation Assume that the address of the input port is 9CH

*Input Port Implementation

*Output Port Implementation Circuit Implementation Assume that the address of the output port is 9CH

*Output Port Implementation

*A Reconfigurable Port Decoder1Vcc

*An Example I/O DeviceKeyboardKeyboard controller scans and reports Key depressions and releasesSupplies key identity as a scan codeScan code is like a sequence number of the keyKeys scan code depends on its position on the keyboardNo relation to the ASCII value of the keyInterfaced through an 8-bit parallel I/O portOriginally supported by 8255 programmable peripheral interface chip (PPI)

*An Example I/O Device (contd)8255 PPI has three 8-bit registersPort A (PA)Port B (PB)Port C (PC)These ports are mapped as follows8255 register Port addressPA (input port)60HPB (output port)61HPC (input port)62HCommand register63H

*An Example I/O Device (contd)Mapping of 8255 I/O ports

*An Example I/O Device (contd)Mapping I/O ports is similar to mapping memoryPartial mappingFull mappingKeyboard scan code and status can be read from port 60H7-bit scan code is available fromPA0 PA6Key status is available from PA7PA7 = 0 key depressedPA0 = 1 key released

*I/O Data TransferData transfer involves two phasesA data transfer phaseIt can be done either by Programmed I/ODMAAn end-notification phaseProgrammed I/OInterruptThree basic techniquesProgrammed I/ODMAInterrupt-driven I/O

*I/O Data Transfer (contd)Programmed I/ODone by busy-waitingThis process is called pollingExampleReading a key from the keyboard involvesWaiting for PA7 bit to go low Indicates that a key is pressedReading the key scan codeTranslating it to the ASCII valueWaiting until the key is released

*8255 Programmable Peripheral Interface

*8255 Programmable Peripheral Interface

*8255 Programmable Peripheral Interface

*Programming 8255 8255 has three operation modes: mode 0, mode 1, and mode 2

*Programming 8255 Mode 0: Ports A, B, and C can be individually programmed as input or output ports Port C is divided into two 4-bit ports which are independent from each other Mode 1: Ports A and B are programmed as input or output ports Port C is used for handshaking

*Programming 8255 Mode 2: Port A is programmed to be bi-directional Port C is for handshaking Port B can be either input or output in mode 0 or mode 1Can you design a decoder for an 8255 chip such that its base address is 40H?Write the instructions that set 8255 into mode 0, port A as input, port B as output, PC0-PC3 as input, PC4-PC7 as output ?

Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1 Strobed Output Timing diagrams.

*Example: Mode 1 Input

BIT5EQU 20HPORTCEQU22HPORTAEQU20H

READ PROCNEARRead:IN AL, PORTC; read portcTEST AL, BIT5;test IBFJZ Read;if IBF=0IN AL, PORTA;Read DataREAD ENDPkeyboardPA0PA7STBPC4DAV8255

*Example: Mode 1 outputPrinterPB0PB7ACKPC2ACK8255PC4DSData Strobe : to tell the printer to latch the incoming data. Generated Externally

*BIT1EQU2PORTCEQU62HPORTBEQU61HCMDEQU63HPRINTPROCNEAR; check printer ready?IN AL, PORTC ;get OBFTEST AL, BIT1 ;test OBFJZ PRINT ;if OBF=0 buffer is full;send character to printerMOV AL, AH ;get dataOUT PORTB, AL ;print data; send data strobe to printerMOV AL, 8 ;clear DSOUT CMD, ALMOV AL, 9 ;clear DSOUT CMD, AL;rising the data at the positive edge of DSRETPRINT ENDPExample: Mode 1 output

*Keyboard example 1/2

*Keyboard example 2/2

*Bouncing Problem

*Bouncing

*Software Solution

*De-bouncing CircuitryTwo asynchronous flip-flop solutions are given below

The basic idea is that these flip-flops store the values even if the D/D nodes both float

*Another Solution

*ErrorsParity error: Received data has wrong error -- transmission bit flip due to noise. Framing error: Start and stop bits not in their proper places. This usually results if the receiver is receiving data at the incorrect baud rate. Overrun error: Data has overrun the internal receiver FIFO buffer. Software is failing to read the data from the FIFO.