INVENTIVE - cadence.com

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CMP Model Application in RC and Timing Extraction FlowHongmei Liao*, Li Song+, Nickhil Jakadtar+, Taber Smith+

* Qualcomm Inc. San Diego, CA 92121 + Cadence Design Systems, Inc. San Jose, CA 95134

© 2007 Cadence Design Systems, Inc. All rights reserved worldwide.2

Outline

• Problems Due to Thickness/Topography Variation– Physical: Copper Pooling and Yield Issues– Electrical: Timing Failures and Performance Loss Due to

Excessive Guardband

• Modeling Technology & Product Overviews– Model Calibration and Validations– Product (CMP Predictor) & Features

• Problem Mitigation Approaches– Integration Flow with RC Extraction Tool– RC Extraction and Timing Results


Interconnect Thickness Variation

• Significant Variation– Thickness Variation: 10% to 40%– Width Variation: 10% to 40%

• Due to Design Layout– Varying Feature Density– Varying Feature Widths

• Has Impact on Manufacturing– Functional Yield Loss– Parametric Timing Failures

WaferSurface

DishingOxide Loss

IsolatedThin-Lines

IsolatedWide-Lines

Dense ArrayThin-Lines

Dense ArrayWide-Lines

Total Copper LossErosion

ChipSurface


Accounting For Variation in Design Process

SystematicThickness

ManufacturingVariation

Guardband

Systematic &Random

ThicknessManufacturing

VariationGuardband

Actual Thickness

Current “2D” Methodology is Conservative Full Chip Guardbandfor Both Systematic and Random Thickness Variation (+- 20%)

+20%

-20%

RandomThickness

ManufacturingVariation

Guardband

Actual Thickness

Cadence “3D” Methodology Eliminates Systematic GuardbandLeaving Only a Relatively Small Random Thickness Variation (+/- 10%)

+10%

-10%


Cadence CMP Model Calibration

Calibration Step Prediction Step

ECD/CMPVirtual Mfg

Process (VMP) Library

MeasurementData From Test Wafer

Predict New Design

ProductDesign LayoutFile

Data from ECD & CMP

Processing Results

Semi-Physical Model Tailored to Specific Process

Full-ChipPrediction

Tailored to Customer’s

Process & Design

CalibrateModel

GeometryExtraction

GeometryExtraction

Test Wafer Design Layout File

ECD/CMPVirtual Mfg

Process (VMP) Library

Topographical Analysis

FabricateTest Wafer(ECP/CMP)


Supported By Leading Edge Foundries and Many Top Tier IDM’s

• Virtual Manufacturing Process Libraries created for each Foundry Process Node (65nm, 45nm, …)

• VMP’s Calibrated by Foundries/IDM’s• VMP’s provided by foundries/IDM’s to Design Teams• Half node support

Common Platform PartnersSAN JOSE, Calif. and HSINCHU, TAIWAN June 4, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) and Taiwan Semiconductor Manufacturing Company (NYSE: TSM) today announced that Cadence is providing key capabilities to TSMC Reference Flow 8.0. The new reference flow addresses design challenges at 45nm, providing statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies.

Reference Flow 8.0 is the latest generation of TSMC's design methodology that increases yields, lowers risks and improves design margins. The flow provides a reference of qualified design building blocks that give designers a proven path from specification to tape out.

"TSMC and Cadence are continuing an established track record of innovation and collaboration with Reference Flow 8.0," said Eric Filseth, corporate vice president of marketing at Cadence. "The resulting TSMC Reference Flow 8.0 is a complete, integrated and comprehensive solution for 45-nanometer design. The breadth of offerings and easy-to-use flow is the key value that Cadence delivers to our mutual customers."

"We worked closely with Cadence to address the complex issues that face designers at 45 nanometers," said Kuo Wu, deputy director of design service marketing at TSMC. "Through our ongoing collaboration with Cadence, we're able to provide designers with new power management, variation-aware analysis, and design for manufacturing technologies, all tightly integrated into TSMC Reference Flow 8.0 and targeted to TSMC's 45nm process."

The silicon-proven TSMC Reference Flow 8.0 allows designers to accelerate advanced 45nm design with lower power, faster cycle time, higher quality and lower manufacturing risk. The Cadence contribution to TSMC Reference Flow 8.0 is based on several new capabilities in the Cadence® Encounter® digital IC design platform and the Cadence Logic Design Team Solution. The new capabilities are supported by a broad range of Cadence tools, including:

§ Incisive® Design Team Simulator§ Incisive Enterprise Simulator§ Cadence SoC Encounter GXL™ RTL-to-GDS system§ Encounter RTL Compiler§ Encounter Conformal® technologies§ Cadence Encounter Test§ Cadence NanoRoute™ nanometer router§ Cadence Encounter Timing System§ Cadence VoltageStorm® power analysis§ Cadence QRC extraction§ Cadence CMP Predictor§ Cadence Chip Optimizer.

Issued by: Cadence and TSMCIssued on: 2007/06/05

New features address design challenges at 45nm node

Cadence Accelerates 45nm Design with TSMC Reference Flow 8.0

SAN JOSE, Calif. and HSINCHU, TAIWAN June 4, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) and Taiwan Semiconductor Manufacturing Company (NYSE: TSM) today announced that Cadence is providing key capabilities to TSMC Reference Flow 8.0. The new reference flow addresses design challenges at 45nm, providing statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies.

Reference Flow 8.0 is the latest generation of TSMC's design methodology that increases yields, lowers risks and improves design margins. The flow provides a reference of qualified design building blocks that give designers a proven path from specification to tape out.

"TSMC and Cadence are continuing an established track record of innovation and collaboration with Reference Flow 8.0," said Eric Filseth, corporate vice president of marketing at Cadence. "The resulting TSMC Reference Flow 8.0 is a complete, integrated and comprehensive solution for 45-nanometer design. The breadth of offerings and easy-to-use flow is the key value that Cadence delivers to our mutual customers."

"We worked closely with Cadence to address the complex issues that face designers at 45 nanometers," said Kuo Wu, deputy director of design service marketing at TSMC. "Through our ongoing collaboration with Cadence, we're able to provide designers with new power management, variation-aware analysis, and design for manufacturing technologies, all tightly integrated into TSMC Reference Flow 8.0 and targeted to TSMC's 45nm process."

The silicon-proven TSMC Reference Flow 8.0 allows designers to accelerate advanced 45nm design with lower power, faster cycle time, higher quality and lower manufacturing risk. The Cadence contribution to TSMC Reference Flow 8.0 is based on several new capabilities in the Cadence® Encounter® digital IC design platform and the Cadence Logic Design Team Solution. The new capabilities are supported by a broad range of Cadence tools, including:

§ Incisive® Design Team Simulator§ Incisive Enterprise Simulator§ Cadence SoC Encounter GXL™ RTL-to-GDS system§ Encounter RTL Compiler§ Encounter Conformal® technologies§ Cadence Encounter Test§ Cadence NanoRoute™ nanometer router§ Cadence Encounter Timing System§ Cadence VoltageStorm® power analysis§ Cadence QRC extraction§ Cadence CMP Predictor§ Cadence Chip Optimizer.

Issued by: Cadence and TSMCIssued on: 2007/06/05

New features address design challenges at 45nm node

Cadence Accelerates 45nm Design with TSMC Reference Flow 8.0

§ Cadence CMP Predictor


Cadence CMP Predictor Features/Applications

• Full chip interconnect and dielectric thickness prediction

– Multi-level– Long-range effects –

neighboring die and scribe lines• Robust Viewing and Analysis

– Command line or point and click UI

– Surface height, thickness, density,…

– Topography plot and statistics• Manufacturing Hotspot

Checking– Hotspot checking – Foundry

defined or customer defined– EDA methodology for

design/dummy fill modifications• RC Extraction Interfaces

– EDA tools (RC extraction)– Generic thickness export file

InterconnectThicknessPrediction

(CMP Predictor) Tool

ThicknessTable

RCExtraction

Tool

Cu Thickness Ox ThicknessXpos, Ypos

InterconnectThicknessPrediction

(CMP Predictor) Tool

ThicknessTable

RCExtraction

Tool

Cu Thickness Ox ThicknessXpos, Ypos


Virtual Manufacturing

Prediction

Foundry ProcessCharacterization

VMPLibraryVMPLibraryVMPLibrary

Cadence CMP Predictor - Applications

Chip Design

Yield Hot Spots

V

Time (seconds)0.0 20n 40n 60n

-2.0

0.0

2.0

4.0

6.0

Nominal Thickness

Actual Thickness

80n

V

Time (seconds)0.0 20n 40n 60n

-2.0

0.0

2.0

4.0

6.0

Nominal Thickness

Actual Thickness

80n

Critical Net Performance

Dummy FillModification

Hotspot Fix

RCExtraction

ProcessOptimization


Variation Impact on RC- Monte Carlo Simulation

RC Extraction ToolQRC…

Critical NetDesignLayout(GDS

/LEF/DEF) RC,Timing

Info

Manufacturing EffectsW and T Variations

Litho Simulation

/WEE

CMP Simulation

(CCP)

Tech File

0

20

40

60

80

100

120

140

160

0.2 0.205 0.21 0.215 0.22 0.225 0.23 0.235 0.24 0.245 0.25 0.255 0.26 0.265 0.27 0.275 0.28

W (um)

Occ

uran

ce

Cc ~ W, T, HCs ~ W, T, HWidth

f

Monte Carlo Simulation Analytical Approach0.2

0.22

0.24

0.26

0.28

0.3

0.32

0.34

0.36

0.38

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Density (%)

Thic

knes

s (u

m)

Density

T

0

5 0

10 0

15 0

20 0

25 0

0.1

0.4

0.7 1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

3.4

3.7 4

4.3

4.6

4.9

C

f


Thickness Impact on Capacitance

0

50

100

150

200

250

300

350

400

450

500

-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1

0

50

100

150

200

250

300

0.15 0.2 0.25

T (um)

f

0

100

200

300

400

500

600

700

S (um)

Leng

th (u

m)

0

200

400

600

800

1000

1200

0.12 0.22 0.42 1.02

W (um)

Leng

th (u

m)

Close form calculation. Ref: N.D. Arora, L. Song et al. IEEE Tran. Semiconductor Manufacturing, pp. 262-271, Vol. 18, No.2 May 2005

The impact of thickness variation (stdev = 5.6%) on C (stdev = 1.9%) is less compared to R (linear). However, variations as large as +/- 7% are observed and it may cause extraction errors for critical nets


Thickness and Width Variation Impact on Timing

0

5 0

1 0 0

1 5 0

2 0 0

2 5 0

0.1

0.4

0.7 1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

3.4

3.7 4

4.3

4.6

4.9

C

f

0

2 0

4 0

6 0

8 0

1 0 0

1 2 0

1 4 0

1 6 0

1 8 0

0.02

0.08

0.14 0.

2

0.26

0.32

0.38

0.44 0.

5

0.56

0.62

0.68

0.74 0.

8

0.86

0.92

0.98

R

f

-62.42.6922T+W Variation

50.82.8054T Variationb

-112.52.6421W Variationa

02.7546Nominal

RC Difference (ps)RC delay (ns)65/90nma. W = 0.10um, Gaussian, StDev = 10%b. T = 0.25um, Gaussian, StDev = 12%

Both self and coupling capacitance are included in timing calculation

Close form calculation. Ref: N.D. Arora, L. Song et al. IEEE Tran. Semiconductor Manufacturing, pp. 262-271, Vol. 18, No.2 May 2005

C distribution R distribution


Corner Based Methodology

Worst Case analysis (corner) yields 26% higher worst coupling capacitance estimation

Measurement vs. Analysis

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.590.5940.5980.6020.606 0.610.6140.6180.6220.626 0.630.6340.638

Cc

fFr

eque

ncy

Coupling Capacitance

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Cc

f

Monte CarloSensitivity

Monte Carlo: 18.07(3.20)Sensitivity: 18.35(2.86)Corner: Cc (worst) = 33.95

Freq

uenc

y

Coupling Capacitance

N.D. Arora, L. Song and A. FujimuraUS Patent 7089516


CCP And QRC Integration Flow

Cadence CMP

Predictor

Design (GDS)

Layer map

RC Extraction with

Model-basedErosion Data

Erosion Data

Design

Tech File

DSPF

SPEF/SSPEF

Spice

BEGINMETAL LEVEL NX pos, Y pos, Cu Thickness, ,Oxide Thickness etc.I j A A

VMP

No Density Rule Based Erosion Table


Model-Based versus Rule-Based Approach:Comparison to Golden Data

0

10

20

30

40

50

60

70

80

90

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9

Errors Compared to Golden Data (%)

nets

(%)

Erosion Table

CMP Model

0

10

20

30

40

50

60

70

-4 -3 -2 -1 0 1 2 3 4 5

Errors Compared to Golden Data (%)

nets

(%)

Erosion TableCMP Model

Validated byTSMC!


RC Extraction Results – CMP Model vs. Rule

Thickness Variation

CapacitanceVariation

0.96

0.98

1.00

1.02

1.05

1.07

1.09

0.96 0.98 1.00 1.02 1.05 1.07 1.09

Thickness Distribution

0

2000

4000

6000

8000

10000

12000

0 1 2 3 4 5 6 7 8 9 10 11 12

Cap Difference (%)

No.

of N

etsLong range and

multi-level CMP effects are difficult to capture using rules


Timing Results – CMP Model vs. Rule

Timing Difference

0

100

200

300

400

500

600

700

800

900

-0.1 0.5 2.0 3.5 5.0 6.5 8.0 9.5 11.0

Slack (ns)

No.

of P

ath

Model

Rule

OKOKPath4

OKOKPath3

56 ps worseOKPath2

46 ps worseOKPath1

ModelRuleModelRule

Hold Setup

Timing slacks are different using model based approach, possible over/under designs


Summary

• The incorporation of CMP model into RC extraction flow of 65nm designs is demonstrated

• Capacitance values extracted using the model based approach is different than those obtained through a rule based approach

• The distribution of timing slacks is also different, in addition, new setup timing violations were observed using the CMP model

• There are potential over or under designs when using rule based approach, model based approach should yield more accurate results

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