Introduction to VLSI Course Work 2021. 2. 1. · Introduction to VLSI ITI Ismailia Memory (Array)...

Introduction to VLSI ITI Ismailia

Introduction to VLSI Course Work

Dr. Hassan Mostafa

حسن مصطفى. د

[email protected]


Course Work

Presentation 20% (Tuesday March 4, 3-6PM)

Final Examination 40% (March 20, midnight)

Project 40% (March 20, midnight) <by email>


Course Project (40%) Deadline: March 20, midnight

Implement the layout of ONE of the following by using standard cells and also full custom design.

64-bit adder <less 5% marks if selected>

64-bit multiplier

64-bit priority encoder

64-bit comparator

Use any available CMOS technology

Compare in a table the layout area, power, worst case delay, design time, and number of transistors of the VHDL design and the custom design.

You are expected to deliver a report of maximum 4 double column pages following IEEE conference style for your design (one extra page = -4%).


Presentation (20%) Deadline: Tuesday March 4, 3-6PM

Provide a 10 minutes presentation on ONE of the following topics:

Clock and Data Recovery (CDR)

Two MEMS applications of your choice other than Accelerometer and Angular rate sensors

Cognitive Radio

Internet of Things

FINFET Processing flow

Network on Chip (NoC) for SoC design

Embedded software architectures


Introduction to VLSI Dr. Hassan Mostafa

حسن مصطفى. د

[email protected]


Contents

CMOS Processing

Scaling

Memory Design: RAM/ROM

Controller: Finite-State Machines

Data-path: Shifters, Adders, Multipliers

SoC Subsystems

Digital Implementation Strategies: ASIC/FPGA

Layout and Design Rules


References

Textbooks referenced

[Rab96] J. M. Rabaey “Digital Integrated Circuits: A Design Perspective” Prentice Hall, 1996.

Slides used(Modified)

[©Prentice Hall] © Prentice Hall 1995, © UCB 1996 Slides for [Rab96] http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html

http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html


Registers

Used for storing data

Structure

N-bit wide

read/write

Clocked

Static/dynamic implementation

Register files

Multiple read/write ports possible

Example: 32-bit wide by 16-bit deep, dual-port parallel read, single port parallel write register file

Itanium processor has 183 x 132-bit registers

. . .

16 w

ord

s

32 bits

32


Implementing Registers Using Logic Gates

Flip-flops

Simple SR latch:

Flip-flops

- JK, D, T

- Clocked

- Master-slave (edge-triggered)

S

R

Q

Q

Q

Q

S

R

S R Q Q’

1 1 Q Q’

1 0 0 1

0 1 1 0

0 0 x x


f

S

f

R

Implementing Registers in CMOS

Direct gate implementation too costly

A master-slave JK flip-flop uses 38 CMOS transistors

Directly implement in transistors

Example: clocked SR FF latch

Q

Q

Note: carefully size the

S, R and f transistors so that we can write

Q


Implementing Registers in CMOS (cont.)

Another example: D latch (register)

Uses transmission gate

When “WR” asserted, “write” operation will take place

Stack D latch structures to get n-bit register

D

WR

Q Q

WR

WR

WR

Transmission gate


Shift Registers: Idea

Shift registers are used for iteratively shifting data

Used in pipelining, bit-by-bit processing, etc.

D

D1

f

f D1 D2

f

f D2 D3

f

f D3

D1 D2 D3 • Problem?

When clock goes high, the data will traverse all the shift registers chain in one clock cycle!

Solution: use non overlapping clocks f1 and f2. f1 used by odd gates, f2 by even gates (use xmission gates after D1’, D2’, D3’).

Use non-overlapping clocks


Memory (Array) Design

Array of bits

Area very important

Memory takes considerable area in processor chips

Compaction results in fewer memory chip modules, more on-chip cache

Timing and power consumption of memory blocks have significant impact on the system

Different types

RAM (SRAM, DRAM, CAM)

ROM (PROM, EEPROM, FLASH)


Memory Design (cont.)

Static vs. dynamic RAM

Dynamic needs refreshing

- Refreshing: read, then write back to restore charge

- Either periodically or after each read

Static (SRAM)

Data stored as long as supply voltage is applied

Large (6 transistors/cell)

Fast

Dynamic (DRAM)

Periodic refresh required

Small (1-3 transistors/cell)

Slower

Special fabrication process


word select lines

Storage cells

Memory Architecture: the Big Picture

Address: which one of the M words to access

Data: the N bits of the word are read/written

Word 0

Word 1

Word M-2

Word M-1

. . .

N bits

S0

S1

S2

SM-2

SM-1

...

Word 0

Word 1

Word M-2

Word M-1

. . .

N bits

S0

S1

S2

SM-2

SM-1

...

Decoder

...

A0

A1

Ak-1

Address

decoder

k = log2 (M)


Memory Access Timing: the Big Picture

Timing:

Send address on the address lines, wait for the word line to become stable

Read/write data on the data lines

READ

WRITE

DATA

Read Access Read Access

Read Cycle

Data Valid Data Written

Write Access

Write Cycle


Memory Cell: Static RAM (6 transistors)

6-transistor cell

Must adjust inverters for input coming through n-type pass gate

Sense amplifier (read) and Driver (write)

Bus drivers

Must adjust sense-amplifier for input coming through n-type pass gate

Condition for read

Condition for write Rd/WR

Sj (WL)

biti (BL) biti


CMOS SRAM Analysis (Read)

WL

BL

V DD

M 5

M 6

M 4

M 1 V DD V DD V DD

BL

Q = 1 Q = 0

C bit C bit


CMOS SRAM Analysis (Read)

0

0

0.2

0.4

0.6

0.8

1

1.2

0.5 1 1.2 1.5 2

Cell Ratio (CR)

2.5 3

Vo

lta

ge

Ris

e (

V)


CMOS SRAM Analysis (Write)

BL = 1 BL = 0

Q = 0

Q = 1

M 1

M 4

M 5

M 6

V DD

V DD

WL


CMOS SRAM Analysis (Write)


6-Transistor Memory Array

8 words deep RAM, 2 bits wide words

To write to word j:

Set Sj=1, all other S lines to 0

Send data on the global bit0, bit0’, bit1, bit1’

To read word k:

Set Sk=1, all other S lines to 0

Sense data on bit0 and bit1.

Rd/WR

bit1 bit1

Rd/WR

bit0 bit0

S0

S1

S7

bit1 bit1 bit0 bit0


Dynamic RAM 3-Transistor Cell

3-transistor cell

No p-type transistors yield a very compact layout for cell

No Vdd connection

Sense Amplifier must be able to quickly detect dropping voltage

WR

data in data out

Rd – Precharge data_out’ to

generate ‘1’ outputs

precharge


Dynamic RAM 3-Transistor Cell: Timing

Value stored at node X when writing a “1”=VWR-VTn

WR

data in data out

Rd

precharge

X

WR

Rd

X

data in

data out

Vdd-VT

DV

Vdd

Vdd


Dynamic RAM 1-Transistor Cell

1-transistor cell

Storage capacitor is source of cell transistor

Special processing steps to make the storage capacitor large

Charge sharing with bus capacitance

(Ccell << Cbus) why? Extra demand on sense

amplifier to detect small changes

Destructive read (must write immediately)

Si (WL)

Storage

capacitor

Precharge to middle voltage level

Bi


Dynamic RAM 1-Transistor Cell: Timing

Write: Cs is charged/discharged

Read

Voltage swing is small (~250 mV)

Charge sharing: Cs*(Vx)+CBL*(VDD/2) = (Cs+CBL)*Vfinal

Voltage change = Vfinal - VDD/2

WL

X

BL

Vdd/2

V dd

GND

Write "1" Read "1"

sensing

Vdd-VT

Vdd/2

WL

BL

X

Cs

CBL


Dynamic RAM 1-Transistor Cell: Observations

DRAM memory cell is single-ended

Read operation is destructive

Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design

When writing a “1” into a DRAM cell, a threshold voltage is lost

Set WL to a higher value than Vdd

Introduction to VLSI ITI Ismailia EE 5324 - VLSI Design II - © Kia

Bazargan

RAM Cells: Summary

Static

Fastest (no refresh)

Simple design

Right solution for small memory arrays such as register files and cache memories

Dynamic

Densest: 1T is best and is the way to go for large memory arrays

Built-in circuitry to step through cells and refresh (can do more than one word at a time)

Sense amplifier needed for fast read operation


Read Only Memory (ROM) Cells: MOS NOR

To store constants data or invariant code

Popular for control implementation

Store program or state machine

Programmable logic array structure

Can be precharged

Transistor exist 0, No transistor 1

bit1 bit2 bit3

read1

read2

0 1 0

0 0 1

MOS

NOR

ROM


ROM Cell: MOS NOR Layout

Programming of the memory can be delayed to one of last process steps

Metal1 on top of diffusion

Basic cell

10 l x 7 l

GND (diffusion)

Metal1

Polysilicon

WL0

WL1

WL2

WL3


ROM Cell: MOS NAND

All word lines high by default with exception of selected row

WL0

WL1

WL2

WL3

Pullup devices

BL0 BL1 BL2 BL3

Transistor exist 1

No transistor 0


ROM Cell: MOS NAND: Layout

No contact to Vdd or GND necessary drastically reduced cell size

Loss in performance compared to NOR ROM

Why?

Basic cell

5l x 6l

Threshold

implant

Polysilicon

Diffusion

lowering

Introduction to VLSI ITI Ismailia Spring 2006 EE 5324 - VLSI Design II - © Kia

Bazargan

33

ROM Cells: Summary

Mask programmability

Precharged vs. pseudo

NAND cell, NOR cell

Area (NAND wins)

Speed (NOR wins)

Other types: EEPROM, etc.


Non-Volatile Memory Cells

Programmable after fabrication

Keep their configuration even after the supply voltage is disconnected

Basic idea:

Use a floating strip of polysilicon between the substrate and the gate

Put charges on the floating gate

Increase threshold voltage disable the device

Different types based on the erasure method


Floating-Gate Transistor (FAMOS)

Source Drain

Gate Floating gate

t ox

t ox

Substrate

n + n + p

(a) Device cross-section

S

D

G

(b) Schematic symbol


Floating-Gate Transistor: Programming

D S

20 V

20 V

D S

0 V

0 V 10V 5V - 5 V

D S

5 V

5 V - 2.5 V

Avalanche injection.

Removing

programming voltage

leaves charges

trapped

Programming

results in

higher VT

- - - - - - - -

- -

- -


FLOTOX EEPROM

Source Drain

Gate Floating gate

Substrate n+ n+

10 nm

20-30 nm

(a) Flotox transistor

V GD

I

(b) Fowler-Nordheim

I-V characteristics

10 V

-10 V

p

BL

WL

V DD

(c) EEPROM cell during a read operation

Programmed 1

Not programmed 0


FLASH EEPROM

n+ drain n+ source

p-substrate

Control gate

Floating gate

programming

erasure Thin tunneling oxide


Cross-Section of NVM Cells

Courtesy Intel


Characteristics of Some NVM Cells


Emerging Technologies (Non-volatile)

• Why can’t your pc simply turn on like your television?

• MRAM uses magnetism rather than electrical power to store bits of data.

• No refresh is needed to retain the data.

• For users of laptops and other mobile devices, such as MP3 players and cell phones, MRAM is the holy grail of longer battery life.


Giant Magnetoresistance (GMR)

Two thin films of

altering ferromagnetic

materials and a non-

magnetic layer-spacer.

(%)R RR

GMRR R

D 10-80% decrease in electrical

resistance


Tunnel Magnetoresistance (TMR)

Two thin films of

altering ferromagnetic

materials and an

insulating spacer.

Fe/MgO/Fe junctions reach over 200% decrease in

electrical resistance at room temperature


MRAM

One of the two plates is a permanent magnet set to a

particular polarity, the other's field will change to match that

of an external field.


MRAM: Reading process

Transistor is “ON”

Measuring of electrical

resistance of a small

sense current from a

supply line through the

cell to the ground.


MRAM: Writing process

Transistor is “OFF”

When current is

passed through the

write lines,

an induced magnetic

field is created at the

junction, which alters

the polarity of the free

layer.


MRAM: Characteristics

• Non-volatility

• Infinite endurance

(Number of cycles till

failure)

• High speed

performance

• Low cost


Memristor / RRAM

Memristor, HP labs Memristor symbol


History

2008: HP has a working memristor prototype

End of 1990s: Research on resistance switching

1971: The theory of the Memristor

1960s: Resistance switching

t


Applications

Memristor, HP labs

DRAM

Mass storage devices

RRAM, successor to: Memristor


Physics


Reading Material Not included in final examination


0 0 0

0

1

0

0

0

0 1 0 1

0

0 …

Memory Cell Array Interface: Example

Memory parameters:

16-bit wide

1024-word deep

Accessing word 9

Address = 00000010012

16 bits

S0

S1

S2

S1022

S1023

...

Decoder

...

A0

A1

A9

Word 0

Word 1022

Word 1023

. . .

.

.

.

Word 9

Word 1

Word 2

SenseAmp /

Drivers

16 bits

S9 A2

A3


Memory Cell Array Layout

Memory performance (speed)

Storage cell speed (read, write)

Data bus capacitance

Periphery: address decoders, sense amplifiers, buffers

Memory area

Cell array layout

How to layout the cells array?

Linear is bad:

- Long data busses

- A lot of cells connected to data bus

- Decoder will have a lot of logic levels N bits

S0

S1

S2

SM-2

SM-1

...

Decoder

...

A0

A1

Ak-1

Word 0

Word M-2

Word M-1

. . .

Word 1

Word 2

SenseAmp /

Drivers

N bits


Memory Cell Array Layout (cont.)

Group the M words into M/L rows, each containing L words

Benefits?

N bits

S0..L-1

SL..2L-1 Row

Decoder

...

Alog L

Alog L+1

Ak-1

Word 0

SAmp/Drv

S2L..3L-1

Word 1 . . . Word L-1

Word L Word L+1 . . . Word 2L-1

Word 2L Word 2L+1 . . . Word 3L-1

Word M-L . . . . . . Word M-1

. . . . . . . . . . . .

SM-L..M-1

N bits N bits . . .

SAmp/Drv SAmp/Drv . . .

N bits N bits N bits . . .

Column Decoder + MUX

N bits

A0

Alog L-1

. . .

address:

L bits

k-L bits


Memory Cell Array Access Example

word=16-bit wide(N), row=8 words(L), address=10 bits (k)

Accessing word 9= 00000010012

16 bits

S0..7

S8..15 Row

Decoder

...

A3

A4

A9

Word 0

SAmp/Drv

S16..23

Word 1 . . . Word 7

Word 8 Word 9 . . . Word 15

Word 16 Word 17 . . . Word 23

Word 1016 . . . . . . Word 1023

. . . . . . . . . . . .

S1016-1023

16 bits 16 bits . . .

SAmp/Drv SAmp/Drv . . .

16 bits 16 bits 16 bits . . .

Column Decoder + MUX

16 bits

A0

A2

L=8 words

M/L =

1024/8=

128 rows

A1

1

0 0

0

…

1

0 0


Hierarchical Memory Structure

Taking the idea one step further

Shorter wires within each block

Enable only one block addr decoder power savings

Blk EN Blk EN

Blk EN Blk EN

Row

Address

Column

Address

Block

Address

Global Bus

SAmp/

Drv Global drivers/

sense amplifiers


Row Decoder Implementation

WL3

WL2

WL1

WL0

GND GND

Precharge

devices

Vdd f A0 A0 A1 A1

Dynamic 2-to-4 NOR

Decoder

f A0 A0 A1 A1

WL3

WL1

WL0

WL2

2-to-4 MOS Dynamic

NAND Decoder


Row Decoder Implementation (cont.)

WL1

WL0

A2A3 A2A3 A2A3 A2A3 A0A1 A0A1 A0A1 A0A1

A2 A3 A3 A2 A0 A1 A1 A0

Introduction to VLSI Course Work 2021. 2. 1. · Introduction to VLSI ITI Ismailia Memory (Array)...

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