EET 3350EET 3350Digital Systems DesignDigital Systems Design

Dan SolarekDan SolarekDan SolarekDan Solarek

Introduction to VHDLIntroduction to VHDLAn OverviewAn Overview

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What is VHDL?What is VHDL?

VHDL = VHDL = VVHSIC HSIC HHardware ardware DDescription escription LLanguageanguage

where VHSIC = where VHSIC = Very High Speed Integrated CircuitVery High Speed Integrated Circuit

A technology independent, standard language for: A technology independent, standard language for: hardware description hardware description

simulation simulation

synthesissynthesis

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What is VHDL?What is VHDL?

VHDL is a programming language that has been VHDL is a programming language that has been designed and optimized for describing the behavior of designed and optimized for describing the behavior of digital systems. digital systems.

Syntax is similar to C (actually, more like Ada)Syntax is similar to C (actually, more like Ada)

It is highly typed – It is highly typed – includes a rich set of data typesincludes a rich set of data types

Allows concurrent processingAllows concurrent processing

Not a general purpose programming languageNot a general purpose programming language

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History of VHDL DevelopmentHistory of VHDL Development

Outgrowth of the DARPA VHSIC ProgramOutgrowth of the DARPA VHSIC ProgramVendors designing large chips needed to exchange Vendors designing large chips needed to exchange data describing their designsdata describing their designsIBM, Texas Instruments, and Intermetrics got the IBM, Texas Instruments, and Intermetrics got the contract in 1983 and released VHDL 7.2 in 1985contract in 1983 and released VHDL 7.2 in 1985Released to the IEEE for standardization in 1986Released to the IEEE for standardization in 1986Became IEEE Std 1076-1987Became IEEE Std 1076-1987Reballoted/upgraded to IEEE Std 1076-1993Reballoted/upgraded to IEEE Std 1076-1993Released IEEE Std 1164-1993, STD_LOGIC_1164 Released IEEE Std 1164-1993, STD_LOGIC_1164

9-valued logic definition, math functions for std_logic9-valued logic definition, math functions for std_logic

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Why VHDL?Why VHDL?

It is a Standard It is a Standard Data Exchange medium between VendorsData Exchange medium between VendorsCommunications medium between CAD ToolsCommunications medium between CAD ToolsNot Proprietary Not Proprietary Promotes interoperability and design re-usePromotes interoperability and design re-use

Not technology-specificNot technology-specificHuman-ReadableHuman-ReadableCan be used to describe the behavior of a design, or to Can be used to describe the behavior of a design, or to synthesize the design itselfsynthesize the design itselfSupports a wide range of abstraction levels Supports a wide range of abstraction levels

Can model a system, board, chip, register-transfer-level (RTL), or Can model a system, board, chip, register-transfer-level (RTL), or gate level designsgate level designs

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VHDL FeaturesVHDL FeaturesSupports HierarchySupports Hierarchy

Flexible design methodology: Top-down, bottom-up, or bothFlexible design methodology: Top-down, bottom-up, or both

Has elements to make large-scale design easierHas elements to make large-scale design easiere.g., components, functions, procedures, packages, configuratione.g., components, functions, procedures, packages, configuration

Supports three types of Supports three types of modeling styles:BehavioralBehavioral (sequential statement model [like a program]) (sequential statement model [like a program])DataflowDataflow (concurrent statement modeling) (concurrent statement modeling)StructuralStructural (for connecting components) (for connecting components)

Test Benches can be written in the same languageTest Benches can be written in the same languagecircuits can be verified by simulation before synthesiscircuits can be verified by simulation before synthesis

Propagation delays, min-max delays, setup and hold timing, Propagation delays, min-max delays, setup and hold timing, timing constraints, etc. can all be described naturallytiming constraints, etc. can all be described naturally

or mixedor mixed

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Basic Hardware Design Flow

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Steps in VHDL-based design flow

Block diagram

CodingComp-ilation

Simu-lation

Syn-thesis

FittingTiming /

verification

Front-endsteps

Back-endsteps

Very painful

Painful, but not uncommon

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VHDL Design FlowVHDL Design Flow

1. Hierarchical / block diagram Figuring out the basic approach and building blocks at the block-diagram level.

Large logic designs are usually hierarchical, and VHDL gives you a good framework for defining modules and their interfaces and filling in the details later.

2. Coding Actual writing of VHDL code for modules, their interfaces, and their internal details.

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Design FlowDesign Flow

3. Compilation Analyses your code for syntax errors and checks it for compatibility with other modules on which it relies. Compilation also creates the internal information that is needed for simulation.

4. Simulation A VHDL simulator allows you to define and apply inputs to your design, and to observe its outputs. Simulation is part of a larger step called verification. A functional verification is performed to verify that the circuit’s logical operation works as desired independent of timing considerations and gate delays.

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Design FlowDesign Flow

5. Synthesis Converting the VHDL description into a set of primitives or components that can be assembled in the target technology. For example, with PLDs or CPLDs, the synthesis tool may generate two-level sum-of products equations. With ASICs, it may generate a netlist that specifies how the gates should be interconnected.

6. Fitting / Placement & Routing Maps the synthesized components onto physical devices.

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Design FlowDesign Flow

7. Timing verification At this stage, the actual circuit delays due to wire lengths, electrical loading, and other factors are known, so precise timing simulation can be performed. Study the circuit’s operation including estimated delays, and verify that the setup, hold, and other timing requirements for sequential devices (like flip-flops) are met.