Introduction to Semiconductor Memory Dr. Lynn Fuller to Semiconductor Memory Page 11 Rochester...
Transcript of Introduction to Semiconductor Memory Dr. Lynn Fuller to Semiconductor Memory Page 11 Rochester...
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
Page 1
Rochester Institute of Technology
Microelectronic Engineering
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
Introduction to Semiconductor Memory
Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee
Microelectronic Engineering Rochester Institute of Technology
82 Lomb Memorial Drive Rochester, NY 14623-5604
Tel (585) 475-2035 Email: [email protected]
Department webpage: http://www.microe.rit.edu
11-13-2015 SemiconductorMemoryIntro.ppt
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
Page 2
Rochester Institute of Technology
Microelectronic Engineering
ADOBE PRESENTER
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© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
OUTLINE
Introduction Types of Memory Memory Organization Decoders Sense Amplifiers Timing Circuits References Homework
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
INTRODUCTION
This document will discuss various types of semiconductor memory. We will look at layout of memory arrays. We will describe circuits common to all memory such as row and column decoders, readout electronics, and sense amplifiers.
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
TYPES OF MEMORY
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
TYPES OF MEMORY
Read-Only Memories (ROMs) - These are used to store information that will not change during the life of the system. They are permanently programmed during manufacture. Nonvolatile read-write Memories (EPROM, EEPROM) - These devices retain the information stored in them when the power is turned off. They can be erased but usually much slower than they can be written. The number of erase/write cycles may be limited. Dynamic Random Access Memories (DRAMs) - Information is stored as charge on a capacitor. The stored charge will eventually leak away so DRAMs must be periodically refreshed. Typically DRAMs are refreshed every 5-50 milli seconds. One transistor one capacitor per cell. Static Random Access Memories (SRAM) - These devices store information in two cross-coupled inverters. Such a memory does not need to be refreshed. CMOS SRAM is low power. The SRAM cell requires six transistors making it fewer bits per chip than DRAM.
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
TYPES OF MEMORY
We will focus on SRAM, DRAM and NVM.
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
MEMORY ORGANIZATION
sense amplifiers/drivers
Column decoder
Row
deco
der
Word Line
Storage Cell
Bit Line
Input/output
Column
Address bits
Row
Address
Bits
A0
.
AJ
20
2J
Word
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
MEMORY ORGANIZATION
The peripheral circuits include multiplexers, decoders, sense amplifiers, column precharge, data buffers, Read-write circuits, level shifting, amplification and more. These circuits have to work for Millions or Billions of storage locations.
Read/Write Write Enable
Sense Enable
Read/Write Column Decoder
Precharge Electronics
Column MUX
Sense Amplifiers
Decoder R/W Control
Word line
Bit
Lin
e
Word line
Word line
Bit
Lin
e
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
DECODER
Q0
Q1
Q2
Q3
A
B
A decoder will activate (high) one row (only) from a binary input.
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
DECODER
Row
deco
der
Row
Address
Bits
A0
.
AJ
20
2J
A decoder will activate (high) one row (only) from a binary input. For example a 16 bit address will be able to address 2n rows or 216 = 65536 rows, 232 = 4.29Billion rows and 264 = 18.4Quintillion rows. We need more NOR gates…..each NOR is n-inputs.
Q0
Q1
Q2
Q3
A
B
A 2 bit address can activate
one of 2n = 22 = 4 rows
Word Lines
Word Lines
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
AND AND NOR N=2 DECODERS
A0 A1
0 0
0 1
1 0
1 1
A1 A0
A0 A1
1
2
3
4
= OUT
B
A A
A
B B
NEGATED INPUT NOR IS EQUAL TO AND
Inputs
1 2 3 4
Outputs
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1
2
3
4
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
N=3 AND DECODER
A2 A0 A1
A2 A1 A0 0 1 2 3 4 5 6 7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1
0
1
2
3
4
5
6
7
outputs
Input address
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
N=6 TWO LEVEL DECODER STAGE
One of the 64 6-input
AND gates needed to
decode a 6-bit address
Two level decoder reduces the fan-in and
the intermediate values from the
predecoder (1st Level) can be reused with
other final decoders. (see next page)
= or
Final Decoder
Final Decoder
1st Level Decoder 1st Level
Decoder
Intermediate Values
Intermediate Values
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
N=6 TWO LEVEL DECODER
n=6
2n = 64
A2 A0
A1 A3 A5
A4
1 2 3 4 ….. 62 63 64
Output to rows
Input Address [A0, A1, A2, A3, A4, A5]
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
6 TRANSISTOR SRAM CELL
VDD Wordline-1
Q
Bit
lin
e-1
Bit
line-
2
Bit
line-
2
Bit
line-
1
Wordline-2
Q
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
DIFFERENTIAL VOLTAGE SENSE AMPLIFIER
VDD
Bit
line-
1
Bit
line-
1
Output
Bias
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
DRAM 1 TRANSISTOR 1 CAPACITOR CELL
•A DRAM memory cell is formed with one transistor and one capacitor. Referred to as a 1T1C cell. •Storing a logic ONE requires a voltage of +Vdd/2 across C1. •Storing a logic ZERO requires a voltage of -Vdd/2 across C1. •Various leakage paths cause the capacitor to slowly deplete charge. •The capacitor needs to be refreshed periodically, which makes the DRAM dynamic rather than static. •Typical refresh rates are every 5-50 msec •Voltage at node x=Vdd for logic one and ground for logic zero
Digit Line
C0
WL0
Vdd/2
D0
X
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
DRAM SENSE AMPLIFER
Digit Line Reference
Digit Line
C0
Vdd/2
Vdd
Vdd/2
fs
fs
fp
Q9 Q8
Q5
Q6
Q2 Q1
Q3 Q4
Q7 is turned on with signal fp precharging the two digit lines to Vdd/2
Q7
Note: the memory is organized into two arrays so that one can be used as the reference for the other. (with basically identical digit line capacitance)
WL0
Vdd/2
D0 D0*
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
SENSE AMPLIFIER DETAILS
Fs goes high and the data in the selected memory cell is sensed. The word line WL0 goes high and the charge on selected capacitor C0 is shared with the capacitance of the digit line D0. If a “1” was stored in C0 the voltage on D0 will initially be a little higher than Vdd/2. The voltage on the reference digit line will initially be Vdd/2. The crosscoupled inverters amplify these starting voltage and bring the digit line D0 to Vdd and D0* to zero volts. The capacitor C0 is recharged (refreshed) at the same time it is read. If a “0” was stored in C0 the voltage on D0 will initially be a little lower than Vdd/2. The crosscoupled inverters bring D0 to zero volts, refreshing C0 and providing a one for an output on D0*.
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
CIRCUIT TIMING
Clock
Pre Charge
Address
Data
Word Line
Bitline B and B
Q
Q Bar
Column
Sense
Output
Read/Write Write Enable
Sense Enable R/W
Control
Column Decoder
Precharge Electronics
Column MUX
Sense Amplifiers
Decoder
Word line
Bit
Lin
e
Bit
Lin
e
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
Page 22
Rochester Institute of Technology
Microelectronic Engineering
SRAM CIRCUIT TIMING
Precharge
Bitline Bar
data
Read enable
Write enable
Q
Some of the various input and output voltages during write
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
Page 23
Rochester Institute of Technology
Microelectronic Engineering
SUMMARY
The electrical engineer will be involved with the design, testing or application of semiconductor memory at some point in his/her career. An understanding of the different types of semiconductor memory and the peripheral circuits is important.
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
Page 24
Rochester Institute of Technology
Microelectronic Engineering
REFERNCES
1. Hodges Jackson and Saleh, Analysis and Design of Digital Integrated Circuits, Chapter 4.
2. Sedra and Smith, Microelectronic Circuits, Sixth Edition, Chapter 13.
3. Dr. Fuller’s Lecture Notes, http://people.rit.edu/lffeee
© November 13, 2015 Dr. Lynn Fuller
Intro to Semiconductor Memory
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Rochester Institute of Technology
Microelectronic Engineering
HOMEWORK – SEMICONDUCTOR MEMORY
1. For the n=6 two level decoder shown on page 15 show how to connect the gates for the output for row 2, 3, 4, 62, 63,64
2. Write a paragraph on how the SRAM cell and differential voltage sense amplifier work. See page 16 and 17.