Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

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Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University
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Transcript of Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Page 1: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Introduction to Layout

Jack Ou, Ph.D.CES 522 V

VLSI DesignSonoma State University

Page 2: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Flow Chart

Page 3: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Cross Sectional of an Inverter

Page 4: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Mask SetD D

S S

Page 5: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Basic Ingriedents

• n-well (N_WELL)• Polysilicon (POLY)• n+ diffusion• p+ diffusion• contact• metal

Page 6: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Manufacturing the n-well• Grow a protectiveLayer of oxide.• Remove oxidein selected region• Ion Implantation

Page 7: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

• Poly silicon(doped to makegood conductor,Block n+ diffusion)• n-diffusion

Page 8: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

p-diffusion, contacts and metal

Thick metal oxide provides insulationp+ diffusion is made selectively using silicon dioxide and photo resist

Page 9: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

λ

• λ is half of the smallest feature size– In 0.18 um, λ is 0.09 um

• λ based design rules makes it easy to migrate from one process to process.

• Industrial design rules are usually specified in microns, which makes it difficult to migrate to a more advanced process.

Page 10: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Simplified λ based design rules

Page 11: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Example from tsmc 0.18 um process

POLY has a width of 2 λContacts are 2 λ x 2 λ

Page 12: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Design Rules

Page 13: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Schematic/Layout of an Inverter

p+ diffision

n+ diffision

Ground

VDD

Page 14: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Schematic/Layout of a NAND2

p+ diffision

n+ diffision

Ground

VDD

Page 15: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Substrate Contact

Page 16: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

P_WELL

Page 17: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

P_WELL+P_PLUS_SELECT

Page 18: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

P_WELL+P_PLUS_SELECT+Active(43)

Page 19: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

P_WELL+P_PLUS_SELECT+Active(43)+Contact to Active

Page 20: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

P_WELL+P_PLUS_SELECT+Active(43)+Contact to Active+Metal1

Page 21: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Nwell Contact

Page 22: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

NWELL

Page 23: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

NWELL+N_Plus_Select+

Page 24: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

NWELL+N_Plus_Select+Active Layer

Page 25: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

NWELL+N_Plus_Select+Active Layer+Contact to Active Layer

Page 26: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

NWELL+N_Plus_Select+Active Layer+Contact to Active Layer+Metal 1

Page 27: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

DRC

Page 28: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

DRC

Check: to run DRCFirst: to see the first DRC violationNext: to step through the DRC errors

Page 29: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

DRC Results

DRC violation

Page 30: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Use the Rule Deck to Repair the Layout

Page 31: Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University.

Repaired Layout

Enlarged N Plus Select

Reduced Result Count