Introduction to Freescale Radar Microcontroller...

External Use

TM

Introduction to Freescale

Radar Microcontroller Solutions

FTF-AUT-F0077

A P R . 2 0 1 4

Andrew Robertson | ADAS Senior Applications Engineer

TM

External Use 1

Agenda

• ADAS trends and need for radar systems

• Radar fundamentals

• MPC5775K microcontroller

• Radar Processing

• Chirp Generation

• Range & Doppler FFT

• Algorithm Flow

• Summary and conclusions

TM

External Use 2

Overview

• ADAS trends and need for radar

systems






• Algorithm Flow


TM

External Use 3

Market Trends

• There is a global trend in the increasing numbers of road fatalities.

In 2010, 1.24 million people were killed on the world’s roads, the

eighth leading cause of death globally (World Health Organization).

• Within the developed regions, passive car safety systems, seat

belts, airbags, and crumple zones have proven essential in

decreasing fatalities and serious injuries to the occupants of cars

and pedestrians.

• The automotive industry is under pressure to provide new and

improved vehicle safety systems, from basic airbag-deployment

systems to complex advanced driver assistance systems (ADAS)

with accident prediction and avoidance capabilities.

TM

External Use 4

• Camera and Radar @>15kmh

• Cognition Algorithms to extract

features / classify objects

• No display necessary

• F. Safety applied to longitudinal

motion (braking / Steering)

e.g.

• Lane Keep

Assist

• Adaptive cruise

control

• Emergency

braking

• Pedestrian

protection

• Rear/Side Camera, sat. Radar,

Usonic @<15kmh

• 3D image techniques and data

fusion

• 2.5D and 3D with high quality

• Park assist

• Self parking with safety

e.g.

• Park Assist

• 3D Surround

View

• Cross traffic

Alert

• Blind Spot det.

• Object Data @ >15kmh

• 3D Enviornmental Modeling

oallowing self navigation

• No Display

• Hard safety – Longditudinal and

Lateral motion

• Integration of Feature extraction

e.g.

• Self-driving

Auto

• Sensor

Fusion

Advanced Driver Assistance Systems

TM

External Use 5

Accident Free Driving is Within Our Sight

Source – Frank Gruson, Continental AG Source – Frank Gruson, Continental AG

TM

External Use 6

Applications for Automotive Radar Are Growing

AEBS Advanced Emergency Braking System

FCW Forward Collision Warning

LDW Lane Departure Warning

BUA Back up Aid

BSD Blind Spot Detection

TM

External Use 7

Expected ADAS Regulations and NCAP Ratings

AEBS Advanced Emergency Braking System

FCW Forward Collision Warning

LDW Lane Departure Warning

BUA Back up Aid

BSD Blind Spot Detection

Source: Interpretation of Continental / Freescale Segment

FCW/LDW Availability if performances are

met (Source NHTSA)

FCW/LDW NCAP Tests

AEBS Mandatory for all

new cars

AEBS / LDW Mandatory for new trucks > 3.5t

FCW/AEBS/LDW/BSD Part of NCAP Star Rating

AEBS / LDW Mandatory for new trucks > 3.5t

BUA Mandatory for SUVs and Van’s

2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Expected

Under Discussions

Decided

TM

External Use 8

Overview


systems






• Algorithm Flow


TM

External Use 9

RaDAR (Radio Detection And Ranging)

RADAR

relative velocity

vR ≠ 0

RADAR

relative velocity

vR = 0

Distance R

Dt

Dt = 2 R / c0 Doppler Shift

TM

External Use 10

FMCW (Frequency Modulated Continuous Wave)

• FMCW operation is independent of the speed or direction of travel of the target high precision

• FMCW is less complex, safer and lower cost (compared to pulse systems)

• FMCW gives low false alarm rates

• FMCW sees a higher percentage of valid targets

TM

External Use 11

Overview


systems






• Algorithm Flow


TM

External Use 12

RADAR Processing

Re-

ceiver

Signal

analysis

Detec-

tion

Signal

condi-

tioning

Tracking

ADC/DSP/FPGA

MPC5775K

• Antenna

• Mixer

• LNA

• HP/LPF

• AAF

• ADC

• Gain

• Window

• FFT

• Filter

• Power

• CFAR

• Clustering

• Kalman Filter

0 20 40 60 80 100 1200

1000

2000

3000

4000

5000

6000

7000

8000

MMIC MR2001

Obj1=(d1, vr1,al1)

Obj2=(d2, vr2, al2)

TM

External Use 13

Benefits of Integration

MPC5675K

System

MPC5775K

System

Performance– MPC5775K offers top-performance for intense computational tasks with key integrated digital accelerators

Safe –Built on proven safe technology it delivers a scalable, well documented, process compliant safe architecture and safe Software

Integration & Cost – Right balance of memory, large number of Analogue IP designed for Radar, FFT accelerator. Drive Miniaturization and BOM saving

Flexible – can be used in all applications and with all Front End Radar sensor technology and types.

TM

External Use 14

Overview


systems






• Algorithm Flow


TM

External Use 15

Qorivva MPC5775K MCU Overview CPU Platform

• 266 MHz Power ISA Dual Issue core multi core system

• Two z4 Cores in permanent delayed Lockstep for high safety integrity level

• Two z7 cores for application execution

• I-cache – 16 KB (2 ways) / D-Cache 16 KB (2 ways)

• Core Local D-memory (64kB at each core) with local MPU

• Vector Floating Point Unit & SIMD (z7)

• 64 bit BIU with E2E ECC

Radar Processing Platform

• Signal Processing Toolbox (SPT) FFT accelerator, SDMA, PDMA

•8x Integrated ΣΔ-ADC with 5 MHz bandwidth and internal sampling clock of

320 MHz.

•12-bit resolution DAC with maximum of 2Msps

•Low jitter 320Mhz PLL for RADAR

Memory

• Up to 4 MBytes byte Flash with EE Emulation and ECC

• Up to 1.5 MBytes SRAM with ECC

• Safe Crossbar (E2E ECC) with system MPU

Vehicle & ECU communication

• 4 x FlexCAN (64 message buffers)

• 1 x FlexRay (Dual Channel 128 msg. buffers)

• 1 x Ethernet Controller (ENET)

• 4 x LINFlex (SCI) & 3x IIC

• 4 x dSPI (4cs std / 8cs in larger v package version only)

• 3 x eTimer

• 2 x FlexPWM (2x 12 channel) & 2x CTU

• Octal A/D (10 M samples/sec) SD Radar I/F – 5MHz BW + 4x SAR

• 2 x SENT

System

• Highly stable Oscillator for Radar ASIC to A/D synchronization

• SIPI (~300MBaud) for interprocessor or mc to ASIC communication

• Safe DMA Engines • Autonomous Fault Collection and Control Unit • CRC computing unit

• Junction temperature sensor

• Nexus Class 3+ debug interface (Aurora extension)

TM

External Use 16

RADAR System Integration

• High-speed multi-master bus connects modules: 64-bit @ 133MHz

• Multi-ported SRAM and Flash support concurrent transfers

TM

External Use 17

Overview


systems






• Algorithm Flow


TM

External Use 18

RADAR Timing Generation

CTE

WGM

ADC ADC

ADC

DAC

SPT

A

C

Q

SRAM

CS

0 2 105

4 105

6 105

8 105

1 104

0.001

0.002

0.003

0.004

t

DA

Cou

t(t)

G

P

I

O

acquisition

window events

chirp[N]

chirp[N+1]

•

•

•

Timing Table[N]

Timing Table[N+1]

fast

DMA

eDMA

eDMA Waveform[N]

Waveform[N+1]

run, hold, reset

ctep

Input signal from MR2001

Control signal to MR2001

Output signal to MR2001

A new best-in-class 12-bit

resolution DAC which

has maximum of 2Msps

Sample received RADAR

echoes

10MSps/12-bit

8x ΣΔ-ADC with 5 MHz

bandwidth and an

internal sampling clock of

320 MHz – 69dB SNR

TM

External Use 19

Chirp Sequence RADAR Timing

• 1 frame comprises up to 512 chirps and the processing algorithm

− ~20 frames per second possible dep. on complexity of processing

• Range FFT performed on-the fly

• Doppler FFT and post-processing run in gaps (transmit idle) between chirps

TM

External Use 20

Overview


systems






• Algorithm Flow


TM

External Use 21

SPT Operation Principle

Configures and

controls SPT

Runs specialized

signal processing

tasks on SPE

Sample received RADAR

echoes

10MSps/12-bit

RADAR Timing

Generation

Command list for

signal processing

Buffered ADC

samples

FFT data

Peak lists

Timing definition

TM

External Use 22

Range Processing

• Range FFT processing

− Windowing

− 2x real by complex FFT

− Data transfer between system RAM and SPT RAM

TM

External Use 23

Signal Analysis – Range FFT

• Range FFTs

− real to complex transform, provide SNR gain

TM

External Use 24

Signal Analysis – Doppler FFT

• Doppler FFTs

− Complex to complex

− Provide SNR gain

− Determine the relative speed

(Doppler gates)

TM

External Use 25

Fast Chirp Sequence Range FFT

Range

FFT

Chirps f(t)

t

Range Gate (Distance)

Dopple

r (S

peed)

ADC

1.N

Range

FFT

SDMA

Min

Max

Sum

Offset Comp.

Pi Comp

COPY

TRANSPOSE

TM

External Use 26

Fast Chirp Sequence Doppler FFT

Range Gate (Distance)

Dopple

r (S

peed)

Doppler

FFT

PD

MA

SRAM

Peak List

Detection

Algorithm

Z7_0 Core

Tracking

Algorithm

Z7_1 Core

SRAM

Car

Comms

Z4_1 Core

TM

External Use 27

Overview


systems






• Algorithm Flow


TM

External Use 28

Radar Algorithm Mapping

TM

External Use 29

FFT Accelerator Architecture

• Operand RAM

− divided into slices for simultaneous access to 8 complex operands

• Twiddle RAM

− stores window coefficients and twiddles

− Divided into 8 slices for simultaneous access

• Quadrature extension

− saves twiddle storage

− Exploits /8 symmetry

• Radix 4 kernel

− 1x Radix4

− 2x Radix2

− 2x real split

− Window only

TM

External Use 30

Operation Principle

TM

External Use 31

FFT Accelerator Advantages

Supports round

commands Can perform large

number of FFTs without

involvement of CPU cores

On-the-fly data

reordering Enables high speed,

back to back Radix kernel

computation

Quadrature Extension Reduced twiddle storage

and fast switch between

window coeff./twiddles

Supports 2x real by 1x

complex FFT w/ splitting Boost real FFT by ~2x

Supports source/dest.

address increments Can work with

interleaved vectors for

multi-D FFTs

Supports auto-repetition

for many small size

FFTs Minimizes scheduling

overhead

DIT+WinMul

Implementation can do time domain

windowing without penalty

Kernel configurable for

Radix4/2/split performs 2^N FFTs with

real/complex values and

time/freq. windows

SPT - FFT

Accelerator

TM

External Use 32

Integer FFT Performance (SPT)

• Up to 24/24-bit complex integer

• Scaling & Time Domain Window included

Operation length cpl/real

round

count

number

cycles time [us]

FFT128, complex 128 C 4 128 2.56

FFT128, real 128 R 5 80 1.6

FFT256, complex 256 C 4 192 3.84

FFT256, real 256 R 5 120 2.4

FFT512, complex 512 C 5 400 8

FFT512, real 512 R 6 240 4.8

FFT1k, complex 1024 C 5 720 14.4

FFT1k, real 1024 R 6 432 8.64

FFT2k, complex 2048 C 6 1632 32.64

FFT2k, real 2048 R 7 952 19.04

FFT16, complex 16 C 2 36 0.72

16xFFT16 (clubbed) 256 C 2 96 1.92

TM

External Use 33

Achieved Performance

• 200Mhz timing closure of SPT

sam

ple

s

C/R

rou

nd

cou

nt

nu

mb

er

cycl

es time

[us] chan

nel

s

chir

ps

ran

ges

# ops

total

time

[ms]

Range FFT 256 R 5 120 0.60 6 512 - 3072 1.84

Doppler FFT 512 C 5 400 2.00 6 - 128 768 1.54

Beamforming FFTs 16 C 2 36 0.18 - 512 128 65536 6.56

single execution one RADAR scan

Operation

cycles

Win

cycles

FFT time[us] #ops time [ms]

FFT256 complex 704 13234 52.40 3072 160.97

FFT256 real 704 8172 33.37 3072 102.51

FFT512 complex 1392 31060 122.00 768 93.70

operation

SPE implementation, libdsp values, 266MHz

Includes

windowing

Performance need:

~10x acceleration for

range FFT

~20x for Doppler

TM

External Use 34

SPT Features

• Acquisition Block (SDMA) ‒ Channel muxing—Sample re-ordering to

simplify PCB routing

‒ Sample DMA—Merging ADC samples into

memory words, arranging the data into

packets, and distributing to memory

locations

• Programmable DMA (PDMA) ‒ Transfers data between the system

RAM/Flash/TCM to operand RAM or

twiddle RAM (SPT internal RAMs) and

vice-versa

‒ Performs special packing and unpacking

schemes on the fly, for reduced storage

• Memory ‒ Operand RAM stores the operands for

operations like FFTs

‒ Twiddle RAM stores constants like

coefficients used in FFT operations

‒ Work registers store single values for

calculation (such as coefficients)

• Hardware Accelerator ‒ FFT

Radix4 and Radix2 butterfly and twiddle

multiplication

Windowing for pre- and post-multiplication with

coefficients

‒ COPY

Primarily moves data from one location to

another

Can transpose and pack complex data and

manipulate real/imaginary parts

‒ Command Sequencer

The command sequencer reads and interprets

instructions in the command queue and

triggers the operation specific scheduler

depending on the instruction

• CPU interaction

• Debug Support

TM

External Use 35

The Benefits

• Built on proven PowerPC based MCU architecture

− Provides the necessary infrastructure, esp. for safety applications (up to

ASIL-D for forward looking sensors)

− Z7 cores and SIMD units used to keep algorithms flexible

− Special features to increase bus/memory throughput

• High-performance computation addressed by SPT

− Operations scheduled autonomously by command sequence

− Enables very high speed FFT implementation

− Decouples FFT load/store bandwidth from system memory

TM

External Use 36

Safety Features

• As part of the Freescale SafeAssure program, the MCP5775K MCU has been

designed with two high-performance Power Architecture®e200z7 cores for signal

processing and can help car manufacturers achieve a minimum ISO 26262

Automotive Safety Integrity Level-B (ASIL-B).

• In addition to supporting the requirements of automotive functional safety

applications, there are two e200z4 cores in a lockstep configuration specifically

designed for decision-making and safety-critical requirements, helping to achieve

ISO 26262 ASIL-D certification.

• Some additional key safety features include online logic built-in self-test (LBIST)

and memory built-in self-test (MBIST), End-to-End error-correcting code (ECC),

clock and power generation supervisor, and a failure-handling module—which also

enable customers to obtain ASIL-D certification.

TM

External Use 37

Summary and Conclusions

Radar is a critical element in ADAS solutions for future

automobiles

Most advanced Radar MCU available with integrated

SDADC and FFT acclerator.

The MPC5775K microprocessor was specifically

designed to interface with the MR2001 chipset to

form a complete scalable radar system (Tx and Rx)

and MCU with few additional components.

TM

External Use 38

Questions?

TM

© 2014 Freescale Semiconductor, Inc. | External Use

www.Freescale.com

http://www.freescale.com/

https://twitter.com/Freescale

https://twitter.com/Freescale

https://www.facebook.com/freescale

https://www.facebook.com/freescale

Introduction to Freescale Radar Microcontroller...

Documents

Transcript of Introduction to Freescale Radar Microcontroller...