Introduction to Control using Digital Signal Processors · PDF fileIntroduction to Control...

Introduction to Control using Digital Signal Processors

Richard Poley DSP Field Applications

Contents Introduction ................................................................................................................................................2 1. Review of Fundamental Concepts...........................................................................................................4

Differential Equations.............................................................................................................................4 Difference Equations ..............................................................................................................................4 The Laplace Transform ..........................................................................................................................5 Continuous Time Systems ......................................................................................................................6 The Impulse Function.............................................................................................................................6 Convolution ............................................................................................................................................7 Significance of s-Plane Pole Locations ..................................................................................................8

2. Discrete Time Control Systems .............................................................................................................11 Data Converters ....................................................................................................................................12 Sampled Data Systems .........................................................................................................................13 The z-Transform...................................................................................................................................15 Stability of Discrete Systems................................................................................................................18 Z-Plane Mapping ..................................................................................................................................19 Zero Order Hold ...................................................................................................................................22

3. Digital Controller Design .....................................................................................................................26 Numerical Integration Techniques........................................................................................................26 Pole-Zero Matching..............................................................................................................................36 Invariance Methods ..............................................................................................................................38 Comparison of Emulation Design Methods..........................................................................................39 Discrete Conversion in Matlab .............................................................................................................39 Digital Controller Design .....................................................................................................................41

4. Implementation .....................................................................................................................................46 Simulation Diagrams ............................................................................................................................46 Sample Rate Selection ..........................................................................................................................47 Control Loop Delay ..............................................................................................................................51 Choosing a Control Processor ..............................................................................................................55

Summary ...................................................................................................................................................64 Appendix A................................................................................................................................................65 Appendix B................................................................................................................................................66 Appendix C................................................................................................................................................67 Appendix D ...............................................................................................................................................68 Notes .........................................................................................................................................................70

Introduction

Introduction The development of embedded digital computers in recent years has brought about a rapid increase in their use in real-time control applications. Examples are multi-phase inverters, electric motors, power supplies, and hydraulic actuators. In many of these applications, the role of the embedded computer has previously been restricted to non-time critical functions such as communications and supervisory tasks. Increasingly however, the availability of modern high performance embedded processors is enabling them to act as sophisticated real-time controllers, and this has led to widespread interest in the subject of digital control among engineers whose principal experience is in analogue rather than digital control techniques.

The use of a digital processor for control of a real-time system brings several benefits to the designer. Among these are:

• Immunity from environmental effects • Ability to implement advanced control strategies not possible using analogue techniques • Immunity from component errors including temporal and thermal drift • Improved noise immunity • Ability to modify and store control parameters on-line • Ability to implement digital communications • System fault monitoring and diagnosis • Data logging capability • Ability to perform automated calibration

For those unfamiliar with digital control, design using digital processor poses several new challenges. Among the most common of these are the need to:

• Determine a suitable sample rate • Account for quantization effects arising from A/D and D/A conversions • Acquire programming skills • Select a suitable processor • Understand numerical issues due to finite resolution of processor and data converters

Unfortunately, many of the available training courses tend to focus on the specifics of the control processor or on programming topics rather than the underlying theory of digital control, and it can be difficult for a practising engineer to acquire a firm grasp of the basics of this subject. For many, this problem is compounded by the mathematical nature of the subject, and there is clearly a need for introductory material which presents digital control theory in a way accessible to analogue engineers.

This document will attempt to remove the major obstacles encountered by control engineers and designers embarking on design using embedded processors for the first time, and to de-mystify a subject which is more susceptible than most to over-complication by technical jargon. The principal objective is to provide a clear and straightforward explanation of the important design techniques in such a way as to dispel many commonly held fears and to encourage further reading of this fascinating subject.

2 Introduction to Control using DSP

Introduction

Scope Control theory is a very extensive subject, and it is obviously unrealistic to attempt rigorous coverage in an introductory document such as this. With this in mind, we will consider only linear systems which have a convenient transfer function description. In particular, state space and non-linear systems are not covered. Although this may seem limiting at first, the techniques provide a good basis for understanding and investigating the properties of a wide range of controllers and compensators.

The document is organised into four sections.

1. A brief review of fundamental concepts

2. An introduction to sampled data systems and the z-transform

3. Techniques for designing digital controllers

4. Considerations when implementing a controller on an embedded processor

The content should be easily accessible to readers with a background in basic analogue design. Familiarity with the Laplace transform and root locus techniques is useful, but not essential as both are described in the first section.

The task of designing digital systems is greatly simplified by the use of computer design software. Throughout this document, extensive use is made of Matlab and Simulink to illustrate concepts and prove results. A detailed description of these tools is beyond the scope of this document, but readers are encouraged to investigate for themselves the benefits of using them.

Notation Notation varies considerably across the literature and this can sometimes lead to confusion. In this document a convention consistent with the majority of texts is adopted, in which the controller input is an error signal denoted by e(t) and the generated output denoted by u(t).

It will be necessary to represent signals which occur only at discrete intervals of time. The notation u(tk) and u(tk+1) indicates the value of the signal u(t) at the kth and (k+1)th sample instant respectively. The simpler, equivalent notation u(k) and u(k+1) will also be used.

A list of recommended texts is given in Appendix B. Where necessary, reference to a specific text is indicated using square brackets.

Introduction to Digital Control 3

1. Review of Fundamental Concepts

1. Review of Fundamental Concepts Before turning to the subject of discrete systems, it may be helpful to review briefly some basic mathematical results which will be needed later.

Differential Equations The ordinary differential equation

)(... 011

1

1 tuyadtdya

dtyda

dtyda n

n

nn

n

n =++++ −

−

−

where a0, a1 … an are constants is an example of a linear nth order constant-coefficient differential equation. If none of the coefficients depend explicitly on time, the equation is termed time invariant. Linear Time Invariant (LTI) equations are an important class of differential equations which can be used to describe many real systems.

dtdD =The “D-operator” is defined as , and allows the above equation to be written

uyaDaDaD nn

n =++++ −− )...( 01

11

A characteristic equation has the form: 0... 011

1 =++++ −− aDaDaD n

nn

A fundamental law of algebra states that this equation has exactly n solutions (roots), which are not necessarily distinct.

Difference Equations Just as differential equations may be used to describe continuous time systems, so difference equations describe discrete time, or sampled data systems. Difference equations relate the evolution of variables from one discrete instant of time to another. For example, the equation

)2()1()()2()( 321 −+−++−= keckeckeckuku

is a second order linear difference equation relating the input e to the output u at discrete instants of time. In the context of digital control, the time interval between samples is always fixed, and the notation denotes the input signal n sample intervals in the past. We will see later that difference equations such as this can be implemented quite easily on a digital computer.

)( nke −



The Laplace Transform The Laplace transform provides a useful method of finding the solution of differential equations. For those unfamiliar with the technique, it may be helpful to view it in a way analogous to the use of logarithms to simplify basic mathematical operations such as multiplication, division, and raising numbers to powers. Expressions may be converted from one form to another, where mathematical manipulation is simpler, then transformed back to the original form once the answer is known.

A differential equation in terms of time (representing a signal or a system) may be converted using a Laplace transform into a different function in terms of a complex variable, s, known as the Laplace operator. After transformation, a solution of the differential equation may be obtained by simple algebraic manipulations, yielding a different equation also in terms of s. To obtain a solution in terms of time, an inverse Laplace transform is carried out. As with logarithms, tables exist to help transform equations from one domain to the other.

For example, to determine the output of a system when subjected to a given input signal in the time domain, it would be necessary to perform a convolution of the input signal and the impulse response of the system. Providing both input and system can be transformed into the Laplace domain, the same result can be obtained by multiplication of their transforms.

The Laplace transform of a signal f(t) is given by the formula

∫∞

−=0

)()( dtetfsF st

The form of the Laplace transform suggests we should think of the signal f(t) as being composed of an infinite series of terms of the form est, where s is a complex variable ( ωα j+ ) known as the ‘complex frequency’. Such terms give rise not only to sine and cosine components, but also growing and decaying exponentials. The only constraint on s is that its real part must be sufficiently large to ensure that the integral converges.

Tables of Laplace transforms for common functions are widely available, and therefore in most cases the need to compute the above integral is avoided. The inverse transform is normally performed by arranging results into a form which allows the same tables to be used in reverse. A sample table of Laplace transforms is shown in Appendix A.



Continuous Time Systems In general, a linear time-invariant system may be described by the equation

ubdt

udbyadt

ydadt

ydnn

n

nn

n

n

n

++=+++ −

−

−

−

...... 1

1

11

1

1

This is an ordinary differential equation in which a0, a1 … an, and b0, b1 … bn, are constants, y(t) and u(t) are dependent variables, and t is the independent variable, time. The system may be characterised by two polynomials in the Laplace operator s:

nnnnn asasasassA +++++= −−−

12

21

1 ...)(

nnnn bsbsbsbsB ++++= −−−

12

21

1 ...)(

The roots of A(s) are called the poles of the system, while the roots of B(s) are called the zeros of the system.

)()(

sAsB

The rational function is called the transfer function of the system. The behaviour of the

system in the time domain can be determined from the inverse Laplace transform of the transfer function, which yields the impulse response function of the system – it’s theoretical response when subjected to an impulse function.

The Impulse Function The impulse is a important mathematical function which has infinite amplitude at time t = 0, and zero amplitude elsewhere.

⎩⎨⎧

≠=∞

=0:00:

)(tt

tδ

It also has the property that the area under the pulse is exactly equal to 1.

1)( =∫∞

∞−

dttδ

If we multiply the impulse function by a constant a, the amplitude stays the same but the area strength becomes a. The impulse response of a system is defined as its response when subjected such an input.



Convolution We can calculate the output of a linear system in the time domain based on it’s impulse response function using a technique known as convolution. For a system with the impulse response function g(t) subjected to an input e(t), the output u(t) can be found from

∫∞

−=0

)()()( τττ detgtu

)(τe )( τ−tgby the time reversed impulse response In words: we multiply the input signal at every value of τ , then integrate the product from 0 to ∞ . This is known as a convolution integral.



Significance of s-Plane Pole Locations The position of each pole plotted on a complex plane yields valuable information about it’s influence on the step response of the system. In the diagram below, each graph represents the step response of a system described by a single pole or complex pole pair at the s-plane locations shown [1]. All graphs have the same horizontal (time) axis for easy comparison.

Re

Im

-ve +ve

-veFaster decay rate

Mor

e os

cilla

tory

X

X

X

X

X

X

X

X X

XX

X

X

X

XX

4

1

0.25

Unstable

-4 -1 -0.25 0.25

Figure 1-1 – Effect of s-plane pole position on step response

Poles located anywhere in the right half of the plane give rise to motions which increase without bound, indicating an unstable system. Poles in the left half plane produce motion which decays more quickly the further to the left they are positioned. Complex poles induce an oscillatory motion, which becomes more pronounced the larger the imaginary component of the pole. Oscillation is constrained within a decay envelope determined by the distance of the pole from the imaginary axis, so complex poles close to the imaginary axis have oscillations which take longer to die out than poles positioned further to the left.

Experienced design engineers can predict the behaviour of a design directly from knowledge of its poles, and to make intelligent choices about control loop compensation without the need to carry out simulation. We will see later how the relationship between pole positions and step responses is affected by transformation into the digital domain.



Root locus plots A single-input, single-output (SISO) system can be described by the transfer function

)()(1)()(

sHsGsGsT

+=

where G(s) and H(s) are transfer functions representing the forward and return components of the loop respectively. The denominator of this expression is in general a quotient of polynomials in s:

)()()()(1

sasbKsHsG =+

A root locus plot is a plot of G(s)H(s) as some variable K is varied from 0 to ∞ . As K changes, the position of the roots this equation trace out a set of loci in the complex plane, called root loci, and these can be used to investigate closed loop performance. The roots are found from

0)()(1 =+ sHsG

1)()( −=sHsG

πnsHsG =∠ )()(1)()( =sHsGTherefore any point in the s-plane which satisfies both , and , is a point on the root locus. Figure 1-2 shows an example root locus plot for a simple third order system.

Figure 1-2 – Example root locus plot



There is an extensive set of rules which determine the paths taken by the individual loci and their effect on the time response of the system. Some of these rules are listed below.

1. Complex conjugate poles lead to a step response which is under-damped

2. If all system poles are real, the step response is over-damped

3. Closed loop zeros may induce overshoot even in an over-damped system

4. The response is dominated by s-plane poles closest to the origin

5. The further left the dominant system poles are: a) the faster the response

b) the greater the bandwidth c) the more expensive it is to implement

6. When a pole and zero nearly cancel each other, the pole has little effect on the overall response

7. Time domain and frequency domain specifications are loosely related: a) rise time and bandwidth are inversely proportional b) larger PM, GM and lower Mp improve damping

8. Adding a pole to the forward path pushes the root loci towards the right

9. Adding a LHP zero generally moves & bends the root loci towards the left

Note: Many of these rules were summarised in an important paper by W.R. Evans in 1948, and for this reason are known as the Evans rules. Matlab on-line help refers to the root locus design method as the “Evans root locus method”.

We shall see later that many of these statements can be made about root locus diagrams constructed for discrete systems in the z-plane.


2. Discrete Time Control Systems


e(t)r(t) c(t)Gp(s)

+Gc(s)

Controller

Sensor

Processu(t)

H(s)

Figure 2-1 – Continuous control system block diagram

Figure 2-1 shows a block diagram of a typical single-input, single-output (SISO) continuous control system. The controller Gc(s) and process to be controlled Gp(s) are both analogue in nature, and their dynamics are often described using either Laplace transform or state space representation. We will assume that we wish to implement the controller using a digital computer which receives samples of the error signal e(t) and generates a corrective output u(t) at discrete intervals of time. The continuous controller Gc(s) will be replaced by a discrete controller Gc(z) having the form shown below.

e(kt)e(t) ADC DAC

Gc(z)

Controlleru(kt)

u(t)

Figure 2-2 – Discrete controller block diagram

Continuous signals must be converted into discrete form before they can be used by the digital controller using an analogue-to-digital converter (ADC). The controller calculates a correction based on the error input, and this must also be converted back into continuous form using a digital-to-analogue converter (DAC) before it can be applied to the actuator or process. The discrete time input and output signals are denoted e(kT) and u(kT) respectively.



Data Converters Data converters form the interface between the analogue and digital parts of our system, and are a convenient place to begin our investigation of discrete time systems. In simple terms they may be thought of as consisting of three components: a sampler, a hold unit, and a quantizer.

• A sampler is a device which captures the input signal, whether continuous or discrete, at regular intervals of time. Mathematically, the action of the sampler leads to the derivation of the z-transform, which plays a role in discrete system design analogous to that of the Laplace transform in continuous design. Time domain signals may be transformed into the z-domain, where mathematical manipulation is simpler. Once the result in terms of the complex variable z is known, expressions may be converted back into the time domain using an inverse z-transform.

• Data converters also include a hold unit which reconstructs the signal between the sample points. The most common type of hold is the zero-order hold (ZOH), which maintains the output constant between samples. The output from such a device therefore consists of a series of steps, rather than a continuously varying signal from which it was sampled. The action of the ZOH introduces dynamic effects which can have significant influence on the performance of the system.

• The process of converting a continuously variable input signal into a form which can be processed by a digital computer involves quantization of the signal. The signal is approximated by a binary number which can only take on a finite number of values. An n-bit quantizer approximates the signal by one of 2n discrete values, and this introduces a random “quantization” error into the measurement. Calculations based upon digitized values will include a quantization errors, which can quickly accumulate leading to instability or limit cycles.

The action of all these components influences the behaviour of the overall system and must be taken into account at the design stage.



Sampled Data Systems There are several ways to introduce the concept of sampling a continuous time signal. One intuitive way allows us to use our knowledge of the impulse function and of convolution to determine how a continuous signal will be affected by sampling.

)(tδ

)(te )(tu

Consider a constant input e(t) which is sampled by an ideal switch closing once for an infinitesimally short amount of time. Such a device is known as an “impulse modulator”, and its’ action may be represented mathematically by an impulse function. The output signal u(t) will be the convolution of impulse response of the input signal and the delta function, however we know e(t) at the switching instant is constant, call it e, so the convolution integral will be

∫∞

−=0

)()( ττδ dtetu

Since the area under the impulse function is always equal to 1, the integral will also be 1. Therefore at the switching instant the output will equal the input u = e, and elsewhere the output will be zero.



∑∞

=

−=0

)()(n

nTtt δδ

)(tTδ

time tT 4T2T 5T3T

time t

u(t)

T 4T2T 5T3T

u(3T)

T

time t

u*(t)

T 4T2T 5T3T

)()()(* tuttu δ=

1

Figure 2-3 – The sampled data process

Figure 2-3 shows one way to visualise the sampling process [1]. The upper graph represents the action of a “sampler”: an idealised device represented by a sequence of impulses, each applied at the instants we wish to sample the input signal. As previously described, each impulse has zero width, infinite amplitude, and unit area. The diagram represents such a signal as a series of vertical arrows with unit amplitude, where the height of each arrow represents the strength of each impulse.

The fixed time between consecutive pulses is determined by the sample rate we decide to use, and is denoted by the symbol T. Mathematically the sampler is represented by:

∑∞

=

−=0

)()(n

nTtt δδ

By convention, the notation implies a unit pulse at time . nTt − nT

The middle graph shows the continuous time signal representing the output of the system we wish to control. The value of the signal at the kth sampling instant is denoted by u(kT).

The lower graph shows the combination of signal and sampling pulses, and from the point of view of the controller, represents the total information available about the process. The interaction between the sampler and signal in the time domain can be determined using the convolution integral. Mathematical analysis of this process leads to the introduction of the z-transform: a technique which extends the transfer function model into the realms of discrete data systems.



The z-Transform Convolution is commonly represented the “*” operator, so our sampled signal may be written

)()()(* tuttu δ=

)(tδ with the summation given above leads to Replacing

∑∞

=

−=0

)()()(*n

nTttutu δ

Information about the value of the input signal is only available at the sampling instants, so the convolution can be represented by a single summation without any loss of information

∑∞

=

−=0

)()()(*n

nTtnTutu δ

Expanding the series and taking Laplace transforms leads to:

[ ] [ ]...)2()2()()()(0)(* +−+−+== TtTuTtTut)u(u*(t)sU δδδLL

We know the Laplace transform of the delta function is 1, and we can now apply the shifting theorem, a unique property of the Laplace transform, to yield an infinite series in terms of the Laplace variable, s

...)2()()0()(* 2 +++= −− TsTs eTueTuusU

∑∞

=

−=0

)()(*n

nTsenTusU

This equation represents the Laplace transform of any arbitrary continuous time signal after sampling. It can be simplified by making the substitution which leads to sTez =

∑∞

=

−=0

)()(n

nznTuzU

{ })(tuZThis is known as the “z-transform” of u(t), and is written as . Just as with Laplace transforms, it is not normally necessary to evaluate the infinite sum because tables exist of z-transforms for common functions (see Appendix A).

It is important to appreciate that the choice of for the complex variable makes any operation carried out in the z-domain dependent on the sampling period (T) of the system. The sample rate is chosen at an early stage in the discrete design process, and any subsequent change will affect the results of all calculations based on z.

sTe



Z-transform of a step function To illustrate how a z-transform may be derived, we will consider a step function with amplitude K, represented by the equation Ktf =)( for . The sampled output picks up no samples before t = 0, and thereafter the output at each sample instant is always K. Therefore,

0≥t

KnTf =)(

…for n = 0, 1, 2…

This forms an infinite series ∑∞

=

−=0

)()(n

nznTfzF

nKzzF −=)(

...)1()( 321 ++++= −−− zzzKzF

This is the binomial expansion of , which leads to the final equation for the z-transform of a step function of amplitude K.

11)1( −−− z

1)(

−=

zKzzF

Z-transform theorems The z-transform possesses several theorems and properties which are useful in design. Five of the most important are shown below.

)()()]()([ 22112211 zFazFakTfakTfa ±=±Za) Linearity

b) Convolution of time sequences )()()()( 2121 zFzFlkflfl

=⎭⎬⎫

⎩⎨⎧

−∑∞

∞=

Z

{ } )()( zFznkf n=+Zc) Time shift

{ } )()( rzFkfr k =−Zd) Frequency scaling

)()1(lim)(lim1

zFzkfzk

−=→∞→

e) Final value theorem

The final value theorem is particularly useful in determining the steady state response of a dynamic system represented by a z-transform.



The inverse z-transform To obtain the time response of a process where F(z) is known, we need to carry out an inverse z-transformation. The most direct methods are either a partial fraction or a power series approach. The partial fraction method involves expansion of z-1F(z) such that each term multiplied by z is recognisable from z-transform tables in a manner analogous to that used to find inverse Laplace transforms.

However, in many cases, information in the form of a z-transform can be converted directly into useable time domain form by making use of the time shift property of the z-transform. We will explore this next.

Relationship between z-transforms and difference equations Having obtained a z-transform representation of our controller, we need to convert it to a form which can be implemented on a digital computer. To do this, we make use of the “time shift” property of the z-transform

{ } )()( zFznkf n=+Z

The technique is to re-arrange the transfer function onto a single line, and divide through by the highest power of z before applying the above property. For example, suppose we have a controller Gc(z) represented by the transfer function

)()(

)1()( 2 zE

zUz

KzzGc =−

=

Re-arranging to bring everything onto the same line yields

)()()(2)(2 zKzEzUzzUzUz =+−

We now divide through by z2 and re-arrange as follows

)()()(2)( 121 zEKzzUzzUzzU −−− +−=

Repeated application of the time shift property brings this into difference equation form.

)1()2()1(2)( −+−−−= kKekukuku

Notice that the practice of dividing through by the highest power of z means that the output is expressed in terms of time delayed sequences of previous inputs and outputs. This type of expression is easy to implement using a computer program, and the techniques for doing this will be discussed later.



Stability of Discrete Systems The discrete-time transfer function is the ratio of the output / input of the system in the z-domain.

)()()(

zDzNzP =

Here, N(z) and D(z) are polynomials in z. Let m be the order of D(z), and n be the order of N(z). For the system to be physically realizable, we have the condition . mn ≥

Recall that a continuous system containing a single pole p, may be expressed in Laplace form as

pssG

−=

1)(

The inverse Laplace transform with zero initial conditions is: . Now for stability we

want to decay with time, and hence the pole at s = p must have a negative real part. This leads to the well-known stability condition for all continuous systems: all system poles must lie in the

ptetg =)(pte

left half of the s-plane.

There is an equivalent stability condition for discrete systems. Consider the single pole system represented by the transfer function

pzzG

−=

1)(

The inverse z-transform with zero initial conditions is

npnTg =)(

A system is said to be stable if any bounded input signal leads to a bounded output signal. A bounded signal is one which is absolutely summable:

∞∑∞

=

p0

)(n

nu

The exponential is summable for np 1≤p p, so in order to ensure stability must be less than 1 (or else the infinite series will grow without bound), and we have the necessary condition for stability which applies to all discrete systems that all system poles must lie within a unit circle in the z-plane.



Z-Plane Mapping As we have seen, z-transformation is carried out by making the substitution , where sTez =

s

Tωπ2

= is the sampling interval. It is useful to see what happens to the complex variable z when

s takes on certain values. For example, if s is purely imaginary, then ωjs = and

TjTez sT ωω sincos +==

2sω

ωThe locus of z will trace out a circle of unit radius as is varied from 0 to .

ωα js +=In general, for any point in the s-plane

)sin(cos TjTeeeez TTjTsT ωωαωα +===

Each point in the z-plane is represented by a vector of length which makes an angle Teα Tω radians with the positive real axis. This process is known as “mapping” between planes. The diagram below shows the mapping of five arbitrary points between the z and s-planes [7].

2φ

ωj

Tωφ =1

Re

Im

-ve

+ve

+ve

-ve

A

CD

E

BRe

Im

-ve

+ve

+ve

-ve

A

C

DE

B

Z DomainLaplace Domain

1φ

σ−

'ωj

σ

r1

r3

r2

Ter σ−=1

T'2 ωφ =Ter σ=2Ter γ−=3

γ−

2φ

ωj

Tωφ =1

Re

Im

-ve

+ve

+ve

-ve

A

CD

E

BRe

Im

-ve

+ve

+ve

-ve

A

C

DE

B

Z DomainLaplace Domain

1φ

σ−

'ωj

σ

r1

r3

r2

Ter σ−=1

T'2 ωφ =Ter σ=2Ter γ−=3

γ−

Figure2-4 – Mapping of typical points in the s-plane



Mapping the region of stability Just as the Laplace transform is the basic tool for controller design in the continuous domain, so the z-transform provides the designer with tools for analysis and design of sampled-data systems. Study of the pole-zero configuration is one design approach, and it is helpful to appreciate how the s-plane region of stability is transformed by sampling.

2sω−

Re

Im

-ve

+ve

+ve

-ve

AF

C

DE

B

Re

Im

-ve

+ve

+ve

-ve

AF

CDE

B Re

Im

-ve

+ve

+ve

-ve

AF

CDE

B

2sω

Region of stability shown cross-hatched

Z Domain Laplace Domain

Figure 2-5 – Comparison of Laplace and z-domains

The region of stability in the s-plane shown above is referred to as the “primary strip”. It contains all the stable poles of the continuous system which will map to unique poles in the z-plane. Any roots which lie in this region will be “reflected” an infinite number of times into similar horizontal strips (known as complementary strips) above and below the primary strip. This is a consequence of the sampling theorem more familiarly known as “aliasing”.

With this substitution, the region of stability in the s-plane is mapped onto the unit circle in the z-plane, as described earlier. Note that in mapping the region in this way, the entire length of the line BC, from 0=ωj to , is mapped onto the z-plane from z = (-1,0) to (0,0). Obviously a great deal of distortion takes place during the mapping process!

∞

The important point is that roots lying within the unit circle give rise to decaying motions, while those lying outside give rise to motions which increase exponentially without bound.



Response of pole locations in the z-plane It is helpful to be able to visualise the time domain behaviour of single poles in the z-plane. Just as with continuous systems, experienced digital designers can use this information to help make important design choices. Figure 2-6 shows the step responses associated with a small number of z-plane pole locations. Compare this with the diagram of s-plane responses shown earlier.

Im

XX X X X

X

X

X

X

X

X

Re

Figure 2-6 – Effect of z-plane pole positions on step response

Any root lying on the boundary of the unit circle produces a continuous oscillation, representing a condition of marginal stability, while a root lying outside the unit circle produces an unstable motion, the magnitude of which increases exponentially with time. Stable roots lying on the real axis to the right of the origin correspond to LHP s-plane roots lying on the negative real axis, and consequently induce no oscillatory behaviour in the time response. As poles move towards the origin, their response decays at a faster rate. This is equivalent to a pole on the real axis of the s-plane moving to the left. Zeroes may be located anywhere in the z-plane, however as they move from the origin towards z = 1 they increase the overshoot of the sys-tem. If zeroes are located outside the unit circle the system is called a “non-minimum phase” sys-tem. The significance of this is that there is no longer a linear relationship between the magnitude and phase of the system frequency response. The above unit step responses were prepared using Matlab using a sampling rate of 0.1 seconds. It should be remembered that unlike the s-plane, mapping in the z-plane is not unique: it is de-pendent on the sampling rate used for discretization. A key result of sampling is that calculations are only valid for the chosen sample rate. A different sampling rate gives rise to a completely dif-ferent mapping in the z-plane.



Zero Order Hold The reconstruction of a continuous signal from discrete samples is almost always performed using a zero-order hold (ZOH) device. Such a device maintains a constant output between sampling points, and produces a series of flat-topped pulses of width T.

TsTs

Ts/2Ts/2

time (t)

u(t)

Figure 2-7 – Zero Order Hold

Mathematically, the Laplace transform of the ZOH function can be derived by applying the transform separately to each flat-topped pulse. Recall the definition of the Laplace transform for the arbitrary function . )(tf

dtetfsF st−∞

∫=0

)()(

Therefore, for a sampler and zero order hold applied to the signal )(tf

...)(...)()0()(2

0

* ++++= −+

−− ∫∫∫ dtenTfdteTfdteftf stTnT

nT

stT

T

stT

The ZOH function in each interval can be represented as the difference between two step functions: . Taking the Laplace transform of this yields )(1)(1)( Ttttf ZOH −−=

see

sssF

sTsT

ZOH

−− −

=−=111)(

∑∞

=

−−−

=0

* )(1)(n

sTsT

enTfsesF



The summation in this equation is simply the z-transform of , and )(tf

)(1)(* zFsesF

sT−−=

sesF

sT

ZOH

−−=

1)(Therefore the output of the ZOH is the z-transform of f(t) modified by . The

frequency response of the ZOH can be evaluated by making the substitution ωjs =

ωω

ω

jejF

Tj

ZOH

−−=

1)(

ωω

ωωω

jj

jeeejF

TjTjTj

ZOH2

2)(

222

⎪⎩

⎪⎨

⎧

⎪⎭

⎪⎬

⎫−

=−

−

⎟⎠⎞

⎜⎝⎛

2sin Tω

The term in brackets is simply and we have

2/)2/sin(

)( 2/

TT

TejF TjZOH ω

ωω ω−=

2/T/2)sinc()( TjZOH eTjF ωωω −=

This is a complex number expressed in exponential (polar) form, where the magnitude is given by

2/)2/sin(

TTTFZOH ω

ω=

πω nT=

2This will be zero whenever , which occurs at integer multiples of the sampling

frequency (i.e. ). snff =

The phase is given by

2)( TjFZOH

ωω −=∠

This tells us that a zero order hold contributes a phase lag proportional to half the sampling period: i.e. the lower the sampling frequency, the more phase lag is added. In most control systems, phase lag erodes phase margin and contributes to instability, so the presence of a sampler tends to degrade the robustness of a control system.



)1(1)(+

=ss

sGTo illustrate this effect, let’s examine the frequency response of the system after

discretization at three different sample rates.

-100

-50

0

50M

agni

tude

(dB)

10-2

10-1

100

101

102

-270

-225

-180

-135

-90

Phas

e (d

eg)

Bode Diagram

Frequency (rad/sec)

cont0.2 sec1 sec2 sec

Figure 2-8 – Frequency response comparison of different sample rates

The response of the continuous system is shown in blue for comparison. Notice that the magnitude curves are not greatly affected by sampling, however the phase curves depart from the continuous case by a significant amount. Notice also that as we increase the sample rate the discrete response curves approach the curve for the continuous case. This is a general rule in digital design: performance can usually be made arbitrarily close to that of a continuous system at the expense of an increase in sample rate.

In fact, for frequencies below the cross-over frequency (i.e. magnitude = 0dB), a reasonable approximation is to take the additional phase lag from sampling as

2T

lagωφ =

2TωFigure 2-9 shows the amount by which each of the phase curves diverges from an reference

line.



0 0.5 1 1.5 2 2.5 3 3.50

10

20

30

40

50

60

70

80

90

Normalized frequency (wT)

Pha

se e

rror (

deg)

Phase error introduced by sampling

0.2 sec1 sec2 secwT/2

Figure 2-9 – Phase error introduced by sampling

As can be seen, this approximation works quite well for systems in which the cross-over frequency is below ¼ the sample rate, and this will provide us with a useful reference point when we later come to make a choice of sample rate for our system. The Matlab script used to generate these curves is shown in Appendix D.


3. Digital Controller Design

3. Digital Controller Design Now that we understand the basic concepts of sampled data systems we can turn our attention to design. An interesting and useful approach is to design the controller design using analogue techniques, then to apply a mathematical conversion to arrive at an equivalent digital form. This is sometimes known as “analogue prototyping” or “design by emulation”, and is popular because it allows existing, proven controller designs to be re-used. Several discrete conversion methods are available, each of which has its’ own benefits and drawbacks depending on nature of the expected input signal and the performance objectives.

We will explore three common conversion methods:

1) Methods based on numerical integration

2) Pole-zero matching techniques

3) Invariant, or hold equivalent methods

Numerical Integration Techniques The concept of discrete conversion using numerical integration is to represent a given transfer function as a differential equation, then derive a difference equation whose solution is an ap-proximation to that of the original differential equation. For example, let’s assume we have a simple analogue filter described by the transfer function

asa

sEsUsH

+==

)()()(

We wish to design a discrete filter with equivalent behaviour. The transfer function represents a system defined by the first order differential equation

)()()( taetautu =+& We can solve this by evaluating the integral

∫ −=t

dueatu0

))()(()( τττ

To perform the integration on a signal defined only at discrete intervals, we need find a way of estimating the value between the sample points. There are many ways to approach this problem, but to illustrate the process we will look at two simple methods: forward approximation and trapezoidal approximation.



Forward approximation method

t t

a(e(t)-u(t))

kT+T

a(e(t)-u(t))

kT kT+TkT Figure 3-1 – Discrete integration using forward approximation

To determine the integral, we need to find the area of the shaded region in the above left diagram. To begin, assume the value of the integral at time t = kT is already known, and we wish to find the value at t = kT + T. The integration can be broken into two parts

∫∫+

−+−=+TkT

kT

kT

dttuteadttuteaTkTu ))()(())()(()(0

The first term on the right hand side is simply , so we need to find a way of performing the second integral. One way which might come to mind is to assume the value of remains constant over the entire interval. This corresponds to the shaded area in the right hand diagram and is known as the forward approximation rule (or sometimes as “Euler’s method”), because the value remains the same looking forward from the current point.

)(kTu)( uea −

))()(( kTukTeaT −The area of the rectangle is simply , and the integration becomes

)()()()( kTaTukTaTekTuTkTu −+=+

)()()1()( kTaTekTuaTTkTu +−=+

We can convert this to a z-transform representation making use of the time shift property

)()()1()( 11 zEaTzzUzaTzU −− +−=

[ ] )()1(1)( 11 zEaTzzaTzU −− =−+

1

1

)1(1)()()( −

−

−+==

zaTaTz

zEzUzH

aT

zazH

+⎟⎠⎞

⎜⎝⎛ −

=1

)(



Comparing this with the original Laplace transform equation, we see that the z-domain equivalent could have been obtained simply by making the substitution

Tzs 1−

←

This is the basis of the forward approximation rule. To determine the z-transform, we simply sub-

stitute each instance of ‘s’ in our original Laplace transform with T

z 1− . Let’s examine how we

apply the forward approximation rule to convert a simple s-domain transfer function into an

equivalent z-domain form. For the simple integrator s

sH 1)( = , we apply the above substitution

to find

1)()()(

−==

zT

zEzUzH

Thus we see that a continuous transfer function with a single pole at s = 0 has been transformed into a z-plane transfer function with a single pole at z = 1. Both systems are stable, and their re-sponse to an input sinusoid is shown below for a sample period of 1 second.

Figure 3-2 – Integrator Response to Sinusoidal Input

assH

+=

1)(Now let’s consider a single pole filter with the continuous function . Applying the

forward rule substitution yields

aT

zzH+−

= 11)(

aTzTzH+−

=1

)(



Choosing T = 1 second, and a = 4, we find

31)(+

=z

zH

4−=sA continuous system with a single pole at , is transformed into a discrete system with a

pole at . Recall that the condition for stability in a discrete system is that all poles should have magnitude less than 1, and we should therefore suspect that this system is unstable. Again we can verify this using a simple Simulink model with sinusoidal input. The result is shown be-low.

3−=z

Figure 3-3 – Filter Response to Sinusoidal Input Clearly the forward approximation method has the undesirable ability to map stable continuous poles into unstable discrete ones. The reason for this is easy to understand if we consider the ef-fect the transformation has on the s-plane region of stability.



Re

Im

-ve

+ve

+ve

-ve


Re

Im

-ve

+ve

+ve

-ve

[1,0]

Figure 3-4 – s-plane mapping using forward approximation method The figure on the right shows the region of stability of the s-plane, while the left figure shows the same region after transformation by the forward rule. The transformation maps a pole at position p according to

)1(1−← p

Tp

In other words, points are scaled by a factor inversely proportional to the sampling period (T), and shifted right by 1. The origin of the s-plane correctly transforms to the position z = [1,0] in the z-plane, but is the only point which is not distorted by the forward rule. The discrete region of sta-bility (indicated by the dotted circle in the left diagram) is merely a subset of the transformed continuous stability region. This is why some stable continuous poles become unstable after con-version using forward approximation. If a faster sample rate is selected we ought to be able to move the pole inside the unit circle. T = 0.1 seconds produces a transfer function of

6.01.0)(

−=

zzH

The sinusoidal response shown below confirms that the system is indeed stable. Transformation using this method clearly leaves much to be desired and it is rarely used.



Figure 3-5 – Filter Response to Sinusoidal Input

Trapezoidal approximation method Another discrete integration method we might use is the trapezoid rule. This approach approxi-mates the numerical integration by taking a straight line between sampling points.

kT-T

u(t)

t

kT

t

u(t)

kT-T kT

Figure 3-6 - Numerical integration using trapezoidal rule The area of the shaded trapezoid can be calculated from

[ ])()()()(2

)()( kTaukTaeTkTauTkTaeTTkTukTu −+−−−+−=

By a similar approach to that used for forward approximation, we obtain the transfer function

azzT

azH+⎟

⎠⎞

⎜⎝⎛

−+

=

11

2

)(

This implies that the conversion could be achieved using the substitution



11

2 +−

←zzTs

This is known as “Tustin’s method”, or occasionally the “bi-linear” transformation because of the form of the substitution.

Note: Professor Arnold Tustin (1899-1994) is best known for the bilinear transformation that bears his name. His many other achievements through his work in feedback control include the use of the 'Metadyne' constant-current DC generator for gun control, an approach to frequency-response servo design, a version of the describing function approach to non-linearity’s, and the invention of a 'signal flow graph' representation of feedback loops. In addition, he made significant contributions to mainstream electrical engineering and was the author of many published papers on electrical machines.

Application of Tustin’s method maps the entire LHP of the Laplace domain into a unit circle in the z-domain. Regions of stability of stability on each domain are therefore congruent, which means stable poles in one domain remain stable after transformation, as shown below.

Re

Im

-ve

+ve

+ve

-ve


Re

Im

-ve

+ve

+ve

-ve Figure 3-7 – s-plane mapping using Tustin’s method

Example Tustin’s method applied to an ideal PID controller To illustrate the application of Tustin’s method we will use it to convert a simple continuous controller into discrete form. A common type of PID controller is known as the parallel or “ideal” form, and is represented by the equation



∫ ++=dt

tdeKdtteKteKtu DIP)()()()(

Here, e(t) is the error input to the controller and u(t) is the output signal to the actuator or process. Taking the Laplace transform with zero initial conditions yields

)()()()( 1 ssEKsEsKsEKsU DIP ++= −

{ }sKsKKsEsU DIP ++= −1)()(

112

+−

←zz

Ts We now apply Tustin’s method by making the substitution for s as follows:

⎭⎬⎫

⎩⎨⎧

+−

+−+

+=112

11

2)()(

zz

TK

zzTKKzEzU DIP

⎭⎬⎫

⎩⎨⎧ −++++−=+− 22 )1(2)1(

2)1)(1()1)(1( z

TKzTKzzKEzzU DIP

⎭⎬⎫

⎩⎨⎧ +−++++−=− )12(2)12(

2)1()1( 2222 zz

TKzzTKzKEzU DIP

⎭⎬⎫

⎩⎨⎧ ++−+

⎭⎬⎫

⎩⎨⎧ −+

⎭⎬⎫

⎩⎨⎧ ++=−

TKTKKE

TKTKzE

TKTKKEzUUz DIPDIDIP

22

422

22

⎭⎬⎫

⎩⎨⎧ ++−+

⎭⎬⎫

⎩⎨⎧ −+

⎭⎬⎫

⎩⎨⎧ +++= −−−

TKTKKEz

TKTKEz

TKTKKEUzU DIPDIDIP

22

422

212

The terms inside the brackets will be constant for any given choice of controller parameters and sample rate, and we can simplify by making the substitutions

TKTKKc DIP

221 ++=

TKTKc DI

42 −=

TKTKKc DIP

223 ++−=

This leaves the simpler equation

)()()()()( 23

121

2 zEzczEzczEczUzzU −−− +++=



The z-operator only appears in negative powers, so we can use the time shift property to transform this into a difference equation relating the current output sample to current and previous input samples.

)2()1()()2()( 321 −+−++−= keckeckeckuku

Here, e(k) represents the present value of sampled error input, e(k - 1) the input one sample period earlier, and e(k - 2) the input two sample periods earlier. Similar notation is used for the output samples. This is the final difference equation representing the equivalent discrete PID controller which will be programmed into the control computer. In principle, the same technique can be used to convert any continuous time controller represented by Laplace transform into an equivalent discrete form. We will return to this equation later when we consider controller implementation.

In practice the use of computer design tools means it is never necessary to compute the discrete difference equation by hand in this way. We will see shortly how to use Matlab to perform the conversion for us directly.

Tustin’s Method with Pre-Warping The simplicity of Tustin’s method comes at a price. Although the stable region of the s-plane is indeed mapped onto the stable region of the z-plane, it is not mapped in quite the same way as we were hoping for.

∞j

Re

Im

-ve

+ve

+ve

-ve

∞− j

1ω

1ω

2sω−

Re

Im

-ve

+ve

+ve

-ve

2sω

Laplace Domain

Z Domain

Figure 3-8 – s-plane distortion introduced by Tustin’s method

Figure 3-8 shows the mapping achieved by Tustin’s method. Note that the entire LHP of the s-plane is mapped onto the unit disk – not just the primary strip. Effectively, the whole imaginary axis from 0 to is wrapped around the circumference of the circle. The corollary of this is that ∞±



even though we are assured that a stable continuous root will map into a stable discrete root, it’s position in the z-plane may well induce completely different dynamic behaviour from that expected. The Tustin method maps low analogue frequencies into approximately the same discrete frequencies, but produces a highly non-linear mapping for high frequencies.

There is a technique which allows us to compensate for the distortion induced by Tustin’s method. It involves applying a deliberate distortion to the root locations in the s-plane prior to mapping, such that the mapping will place the roots in the correct position in the z-plane. This technique is called pre-warping, and is quite straightforward to carry out. Here are the steps:

⎟⎟⎠

⎞⎜⎜⎝

⎛

1ωsG 1ω1. Re-write the desired characteristic equation in the form , where is the critical

frequency we wish to preserve.

2tan2 1T

Ta ω=1ω2. Replace by , such that a

112

+−

←zz

Ts3. Apply the substitution

As a simple example, let’s examine how the following simple second order system is mapped using Tustin’s method with and without pre-warping.

1579116.3015791)( 2 ++

=ss

sG

This corresponds to a system with unity gain, damping ratio 0.12, and natural frequency 125.6 rad/s. We would expect z-transformation using Tustin’s method to distort the frequency scale, moving the critical nω frequency. If the transfer function were to represent a low-pass filter for example, this might be a serious concern. Pre-warping at nω would preserve this frequency at it’s correct value as shown in figure 3-9.

Notice how Tustin’s method has shifted the natural frequency denoted by the peak magnitude and the -90o phase points to a lower frequency. Both are restored to their original frequency after pre-warping.

In this way, any given s-plane root can be mapped across to a position in the z-plane corresponding to equivalent time domain frequency. However, this process can only be applied to one root (or equivalently, a complex conjugate root pair) at a time. Complex systems with many roots will still suffer from frequency distortion and a compromise will have to be found.



-60

-40

-20

0

20

Mag

nitu

de (d

B)

102

-180

-135

-90

-45

0

Phas

e (d

eg)

Bode Diagram

Frequency (rad/sec)

ContinuousTustinPre-w arped

Figure 3-9 – Tustin’s method with frequency pre-warping

Pole-Zero Matching The idea behind the pole-zero matching method is that, subject to certain rules, s-plane poles and zeros might reasonably be mapped (subject to certain constraints) using the substitution . sTez =

The method consists of a set of steps which are outlined below.

1. Transform the poles of the transfer function according to z = esT

2 Transform the zeros of the transfer function according to z = esT

3 Map any infinite zeros of the continuous system to z = -1

4 Match the gain of the transformed system at s = 0

For example, suppose we wish to use this technique to obtain the discrete equivalent of a system described by the transfer function

2110)(

++

=s

ssG



Using a sample period of 0.2 seconds. The system has a simple zero at and a simple pole at . The discrete transfer function will therefore be of the form

1.0=s2−=s

2

2)(pzzzzG

−−

=

Substitution using gives sTez =

6703.0

9802.0)2.0)(2(

2

)2.0)(1.0(2

==

==−

−

ep

ez

0=s is 0.5, but the discrete system gain at is 0=zThe gain of the continuous system at

0601.06703.09802.0

1=−−

=zzz

325.80601.0

5.0=Therefore we need to apply a fixed gain to the discrete system of and the final

discrete transfer function becomes

6703.016.8325.8)(

−−

=z

zzG

The frequency response plots for there continuous and discrete equivalent systems are shown below.

-10

-5

0

5

10

15

20

Mag

nitu

de (d

B)

10-3

10-2

10-1

100

101

102

0

30

60

90

Phas

e (d

eg)

Bode Diagram

Frequency (rad/sec)

Figure 3-10 – Frequency response plots for matched pole-zero example



Invariance Methods The philosophy of invariance methods is that with knowledge of the input to a given continuous system, it ought to be possible to construct an equivalent discrete system which produces exactly the same response as the original for the same input. To proceed with the method we need to know what form the input will take.

Step Invariance Method The step invariance method bases the conversion on the continuous system response to a step function input. For this reason the method is sometimes called the “zero order hold equivalent” method. In this case, we assume the continuous system will be subjected to an input unit step

function ssGsC )()( =

ssU 1)( = . Therefore the output will be of the form

U(s) C(s)G(s)

To determine the time response we take the inverse Laplace transform, and then find the z-transform.

⎥⎦

⎤⎢⎣

⎡

⎭⎬⎫

⎩⎨⎧= −

ssGzC )()( 1LZ

This is the output response for a discrete input given by the z-transform of the unit step function

, or 1

)(−

=z

zzU)()( ttu 1= . Therefore the equivalent discrete system would be given by

⎥⎦

⎤⎢⎣

⎡

⎭⎬⎫

⎩⎨⎧−= −−

ssGzzG )()1()( 11 LZ

Ramp Invariance Method The ramp invariance method (or “first order hold equivalent” method) follows exactly the same procedure as that of the step invariance method. The only difference is that the reference input is

taken as a ramp function 2)1()(

−=

zTzzU2

1)(s

sU = . This has the z-transform , and the discrete

system producing an equivalent output would be given by

⎥⎦

⎤⎢⎣

⎡

⎭⎬⎫

⎩⎨⎧−

= −2

12 )()1()(

ssG

TzzzG LZ



Comparison of Emulation Design Methods The impulse invariant method matches the impulse response of the discretized version with that of the continuous system. This is a good technique if only the impulse response is of interest, but can cause difficulties if working in the frequency domain because aliasing effects are introduced.

The step invariant method (ZOH equivalent) works well in cases where the input is held constant between samples, as it would be if it came from a computer, but introduces significant phase errors for continuously varying input signals.

The ramp invariant method (FOH equivalent) probably gives the best all-round performance with continuous input signals.

Tustin’s method is easiest for hand calculation but introduces significant z-domain distortion resulting in incorrect sampled poles. This can be eliminated using pre-warping, but only at a single frequency. For frequency responses defined by more than one frequency (e.g. band-pass or notch filters), this method is not suitable.

Discrete Conversion in Matlab Matlab contains a useful function to convert continuous-time transfer function into discrete form. The function “c2d” can be invoked with an argument to implement any of the conversion meth-ods described earlier. The syntax is: sysd = c2d(sys,Ts,method) Here, “sys” is the continuous-time system representation, “Ts” the sampling interval, and “method” the conversion method chosen from the following list:

'zoh‘ = Zero-order hold (step invariant method)

‘foh‘ = First-order hold (ramp invariant method)

'imp‘ = Impulse-invariant discretization (matches impulse responses)

'matched‘ = Matched pole-zero method

‘forward‘ = Forward integral approximation

'tustin‘ = Bi-linear (Tustin) approximation

'prewarp‘ = Tustin approximation with frequency pre-warping.

The Tustin method with pre-warping can be applied using a slightly different syntax with the critical frequency “Wc” (in rad/s) specified as a fourth input. The syntax is: sysd = c2d(sys,Ts,’prewarp’,Wc) There is more documentation on the c2d function in the Matlab on-line help by typing “doc c2d”.



541)( 2 ++

−=

ssssHFor example, in Matlab the system can be represented and discretized with

sampling period 0.1 s using the ZOH equivalent method as follows. % create transfer function H = tf([1 -1], [1 4 5], 'inputdelay', 0.35) % discretize using ZOH equivalent method with Ts = 0.1s Hd = c2d(H, 0.1, 'zoh') % plot step function of both systems step(H, '-', Hd, '--') The first line creates a transfer function representation of the continuous-time system. The next line performs the discretization, and the last line constructs the continuous and discrete step re-sponses shown below.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15Step Response

Time (sec)

Ampl

itude

Figure 3-11 – Step response comparison of example system

As a second example, let’s return to the PID controller we discussed earlier. We already know how to transform this into discrete form “long-hand”, using the Tustin method. The following lines of Matlab script would have achieved the same thing (and avoided the algebra!) Gc1 = Kp + tf(Ki, [1 0]) + tf([Kd 0], 1) Gcz = c2d(Gc, Ts, 'tustin')

Where Kp, Ki, and Kd are the continuous PID controller settings, and Ts the chosen sample period.



Digital Controller Design The main disadvantage of basing a digital controller design on an analogue prototype is that the result is at best only an approximation to the original. The analogue prototype represents an upper bound on the effectiveness of the digital controller.

An alternative is to conduct the entire design in the digital domain, however to do this we must first have available a z-domain description of the process we wish to control. If the process can be described in transfer function form, we can apply one of the discrete conversion techniques of the previous section. This approach has benefits in terms of performance compared with emulation techniques because the effect of the ZOH is included in the model from the outset.

Root Locus Method The root locus is a plot in the s-plane or z-plane of closed loop root positions as some parameter is varied, usually from 0 to ∞ . A root locus plot for a system can be readily obtained from Matlab using control gain as the chosen variable. For systems with one input and one output, the “SISOTOOL” utility allows us to visualise the root loci, and manipulate controller poles and zeros to optimise against given performance targets. The same approach can be applied to either continuous or discrete systems.

)110(1)(+

=ss

sGFor example, suppose we have a plant described by the transfer function for

which we wish to design a digital controller with sample rate of 1 Hz such that the step response of the system has an overshoot of less than 16%, and a settling time to within 1% of final value in less than 10 seconds.

We begin by using Matlab to convert the plant transfer function into discrete form using the ZOH equivalent (step invariance) method described earlier. sys = tf(1, [1 0]) * tf(1, [10 1]) sysd = c2d(sys, 1, 'zoh') Next, we invoke the SISOTOOL utility to design our discretized system as follows: sisotool(sysd)

This utility enables us to visualize how the placement of controller poles affects the behaviour of our systems, and to use this information to design a suitable discrete compensator.

For this second order system, the peak magnification ratio (Mp) is given by the formula

211 ζ

πζ

+

−

+= eM p . We can transpose to find the damping ratio required to meet the overshoot

specification: 504.0≥ζ .

The settling time constraint can be determined directly from the time response of a second order system to a unit step input:



)sin(1

1)(2

ϕωζ

ζω

+−

−=−

tetc d

tn

95.0≈nωFrom which we obtain the required natural frequency: rad/s. These specifications for ζ nω & will define a region of the z-plane in which the system roots must lie in order to meet the design constraints. SISOTOOL allows design constraints to be applied to the root locus diagram such that unsuitable regions of the complex plane are shaded. This is shown in the diagram below, from which it can be seen that no value of controller gain can position the roots inside the desired region. Some form of compensation is clearly required.

Figure 3-12 – Root locus plot & z-plane constraints

We can modify the controller by adding real or complex poles and zeros and inspecting the new loci. In this way, many design candidates can be evaluated to determine the best control solution. In this case, we may be tempted to try a real zero positioned at near z = 0.5. The resulting design would indeed produce an acceptable closed loop response, but to be realizable, the controller transfer function must have at least as many poles as zeros. Therefore, let’s examine the effect of adding a lead compensator. A lead compensator consists of a real zero and a real pole, with the pole at higher frequency than the zero. It aims to introduce low frequency phase lead so that phase margin can be improved without significantly affecting



steady-state error. Correctly applied, it can improve both rise time and settling time, as well as increase damping. The presence of a lower frequency zero than pole tends to pull the system loci towards the left of the complex plane. Using SISOTOOL, the pole-zero combination may be positioned by hand to achieve acceptable performance. One choice results in the controller

2725.09193.03106.0)(

−−

×=zzzGC

The modified root locus is shown below.

Figure 3-13 – Root locus plot with compensator

The addition of a lead compensator with one real zero and one real pole has allowed us to position the open loop roots inside the desired region. The step response of the closed-loop system for a controller gain of 0.3106 is shown below from which it can be seen that both design constraints are now comfortably met.



Step Response

Time (sec)

Ampl

itude

0 10 20 30 40 50 600

0.2

0.4

0.6

0.8

1

1.2

1.4

Figure 3-14 – Step response after compensation

We now need to determine the control difference equation corresponding to this compensator. This can be done by application of the shifting theorem to the z-domain transfer function, as before.

)9193.0)((3106.0)2725.0)(( −×=− zzEzzU

)(0286.0)(3106.0)(2725.0)( 11 zEzzEzUzzU −− −+=

)1(0286.0)(3106.0)1(2615.0)( −−+−= kekekuku

This is the difference equation representing our controller and can easily be coded on a digital computer. We now see the benefit of using a digital processor in a control system: there is no need to synthesize circuits using discrete electrical components. Any compensators required to stabilize and tune the loop dynamics may be implemented in software, which leads to configurable and highly stable compensator designs.



Frequency Response Method

Bode plots are a valuable tool for designing continuous systems, and with care they can be used to carry out design in the digital domain, providing certain limitations are clearly understood. One such limitation is the use of the Bode relations, which (for minimum-phase continuous-time systems) describe a relationship between the magnitude and phase curves.

The approach to design using frequency response is broadly similar to that for root locus method, except that we base our design choices on the Bode rather than root locus plot. The steps to carry out discrete controller design in digital domain are as follows.

1. Convert G(s) to G(z) using step invariant method

2. Construct magnitude and phase plots

3. Evaluate gain and phase margins

4. Add compensators to achieve required performance

5. Re-test and adjust compensation as necessary

For comparison, the Bode plot obtained from SISOTOOL for the previous example is shown below.

Figure 3-15 – SISOTOOL Bode plot example


4. Implementation

4. Implementation

Simulation Diagrams Simulation diagrams are a useful way of visualising the structure of discrete control algorithms based on their describing difference equations. They enable graphical simulation of the system and easy representation of software algorithms. For example, suppose that a discrete system can be represented in the following form

)2()1()()()1()2( 21001 ++++=++++ kebkebkebkuakuaku

Here, e(k+n) represents the input series and u(k+n) the output series. First, rearrange the expression in terms of the highest order of the output

)2()1()()()1()2( 21001 +++++−+−=+ kebkebkebkuakuaku

Now making use of the shift operator z-1 to represent a unit delay element

)()()()()()( 212

02

02

11 kebkebzkebzkuazkuazku +++−−= −−−−

The expression can now be arranged into a nested sequence of delayed terms as follows

{ }{ })()()()()()( 001

111

2 kuakebzkuakebzkebku −+−+= −−

This equation can be built up in graphical form using a series of blocks representing the operations of unit delay, multiply, and add as shown below.

z-1

b0

a0

z-1

b1

a1

b2

u(k)

e(k)

Figure 4-1 – Simulation diagram of 2P2Z controller

In the diagram above, triangles represent multiplication by a constant coefficient, circles are additions, and square blocks represents storage elements which delay the value at that point by one sample period. This is an implementation of a 2-pole, 2-zero (2P2Z) controller, an example of which is the discrete PID controller we derived earlier using the Tustin method.


4. Implementation

Sample Rate Selection Selection of the sample rate must be made at an early stage when designing a digital control system, and the decision can have a profound effect on the overall performance. Too slow a rate will induce excessive phase lag and can easily lead to instability and loss of control (see section on zero-order hold). A practical lower limit is imposed by the well-known sampling theorem, which dictates that our sampling frequency BωSω should be at least twice the system bandwidth

2≥B

S

ωω

We know that the faster we sample a system, the closer our discrete approximation will be to the original continuous-time signal, so we may be tempted to select an arbitrarily fast sample rate. However, sampling at an unnecessarily fast rate places an increased computational burden on the processor, and means that both it and the data converters will be over-specified, resulting in increased system cost.

The optimum choice of sample rate depends on the nature of the process being controlled, and one approach is to base the selection on the rise time of the process. Rise time is based on the step response of the process, and is defined as the time taken for the output to rise from 10% to 90% of its final value.

A guideline which usually produces acceptable performance is to select a sample period of between 4 and 10 times the process rise time, however it should be emphasized that the suitability of the selected sample rate should always be confirmed by simulation before proceeding further with the design.

Rise Time Determination For first order systems, rise time is directly calculable from the dynamic equation

τt

etc−

−= 1)(

))(1ln( tct −−= τ

τ2.2≈rtSubstituting 0.1 & 0.9 for c(t) and subtracting leads to the widely used approximation

For a second order system, the unit step response is governed by the equation

)sin(1

1)(2

ϕωζ

ζω

+−

−=−

tetc d

tn

ζ nωWhere and are the damping ratio an un-damped natural frequency respectively. The

damped natural frequency is given by 21 ζωω −= nd , and the phase by . ζϕ 1cos−=


4. Implementation

ζ nωSince we have two independent variables, and , we cannot obtain a simple analytic formula for rise time as we did for the first order case. However we can arrive at an approximation by plotting rntω ζ ζ against and fitting a straight line or curve over the range 0 < < 1. The result is shown below.

Figure 4-2 – Rise time determination of second order system

The curve typically exhibits a “knee” point at around ζ = 0.7, where critical damping occurs. As the damping ratio is increased, one real root tends to dominate the rise time and we have an approximation similar to the first order case. At low damping, a reasonable approximation is given by the formula [6]

nrt ω

ζ5.28.0 +≈

For damping ratios above about 0.8, the curve can be approximated by:

nrt

ωζ56.1 +−

≈

Example To illustrate the techniques we’ve just covered, let’s look at how we might design and implement a simple PID controller on a digital processor. In this example, the plant we wish to control and the measuring transducer are described by the transfer function

( )( )1841)( 2 +++

=sss

sG


4. Implementation

Assume an analogue PID controller already exists and is known to give acceptable performance with controller settings: KD = 8, KI = 11, KD = 2.5. Our task is to design a discrete controller with the same performance.

We will begin by selecting a suitable sample rate based on the rise time of the plant. The transfer function poles are at: 1,22 −±−= is , and we might expect the response to be dominated by the real pole at which is confirmed by step response simulation in Matlab. 1−=s

0 0.5 1 1.5 2 2.5 3 3.5 40

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Figure 4-3 – Step response of example plant

The normalised step response is shown above and the Matlab script to model this and determine rise time is shown below.

% set up time vector Tfinal = 4; dt = 0.01; t = 0:dt:Tfinal; % create plot figure colormap('Autumn'); hold al l grid on % construct model of plant G1 = tf(1, [1 4 8]); G2 = tf(1, [1 1]); Gp = G1 * G2 * 8; y = step(Gp,t); plot(t,y) % calculate rise time k = find(y > 0.0999); t1 = k(1); k = find(y > 0.8999); t2 = k(1); tr = (t2 - t1) * dt;


4. Implementation

The script calculates the rise time of this plant as 2.21 seconds. If we had estimated the rise time using the formula for the dominant pole we would have obtained a similar result. This is quite a slow system and processor bandwidth is unlikely to be an issue, so let’s select a conservative 20 times faster sample rate, say 0.1 seconds.

We can now use Tustin’s method as previously described to determine an equivalent difference equation for the PID controller. The constants can be easily calculated from the controller settings and desired sample time to yield the control equation

)2(55.42)1(9.98)(55.58)2()( −+−−+−= kekekekuku

We can simulate this quite easily in Matlab, using an OCF representation of the controller. Step responses of the system controlled by continuous and discrete PID controllers can be compared as shown below.

0 1 2 3 4 5 6 7 8 9 100

0.2

0.4

0.6

0.8

1

1.2

1.4Servo Response Plot

Time (s)

Dis

plac

emen

t (m

m)

continuousdiscrete

Figure 4-4 - Step response comparison of continuous & discrete PID controllers

Perhaps not surprisingly, the responses are slightly different. This is because of the distortion of the frequency domain introduced by the Tustin method.


4. Implementation

Control Loop Delay

A critical feature of any control loop is the amount of delay present in the controller. In digital systems, delays arise in the action of the data converters and because of finite computation time of the controller. Since the controller will be positioned inside the control loop, these delays introduce a phase lag which erodes phase margin and contributes to instability.

0 5 1 0 1 5 2 0 2 50

0 . 1

0 . 2

0 . 3

0 . 4

0 . 5

0 . 6

0 . 7

0 . 8S e rvo R e s p o n s e P lo t

T im e (s )

Dis

plac

emen

t (m

m)

0 . 10 .1 5 0 . 20 .2 5 0 . 30 .3 5 0 . 40 .4 5 0 . 50 .5 5 0 . 60 .6 5 0 . 70 .7 5 0 . 80 .8 5 0 . 9

Figure 4-5 – Effect of servo delay on stability

Figure 4-5 shows a simulation of the step response of a second order system in a closed loop, over a range of different input delays. The transfer function used is

501.17947.01)( 2 ++

=ss

sG

This system has a natural frequency of about 1.225 rad/s, and even with negligible delay the step response exhibits some oscillation. Using the sample rate guidelines described earlier, N = 4 gives the sampling period Ts = 0.2144 s. Increasing the input delay to 0.9 seconds results in significantly larger and more prolonged oscillations.

Introduction of any digital processor into the control loop brings with it a certain amount of unavoidable delay: data converters have a small conversion time associated with them, and computation of the control algorithm takes a finite number of CPU clock cycles. Additionally, the controller will be triggered by an interrupt which runs asynchronously with other processor tasks. Each time the interrupt is triggered, there will be a further short delay as the processor switches execution to the ISR. Therefore it is critical to minimise the processor interrupt latency.

In order to appreciate the nature of such delays, we will examine a typical controller timeline from the instant an input signal is sampled.


4. Implementation

Controller timeline Each input sample is converted by an integrated ADC, and an interrupt is triggered when the result is available. The CPU now executes an interrupt service routine (ISR) – a short sub-routine which reads the new sample, runs the control algorithm, and sends the new output to the actuator. The critical time is the interval between the instant at which the input is sampled, and the instant at which the new control output is written. This causes a control loop delay which degrades the performance of the system and it is essential for the designer to be able to predict and minimize any delay.

time

Sam

ple

poin

tS

ampl

e po

int

Con

vers

ion

star

tsC

onve

rsio

n st

arts

Con

vers

ion

com

plet

eC

onve

rsio

n co

mpl

ete

1 S/H acquisition time (settling time, pre-filter)1 S/H acquisition time (settling time, pre-filter)

ADC conversion time2 ADC conversion time2

3 Recognition delay (interrupt blocking code, OS jitter issues)3 Recognition delay (interrupt blocking code, OS jitter issues)

4 Hardware interrupt latency4 Hardware interrupt latency

5 Computational delay (controller algorithm)5 Computational delay (controller algorithm)

6 Interrupt body (remaining ISR code)6 Interrupt body (remaining ISR code)

7 ISR context restore & exit7 ISR context restore & exit

8 CPU bandwidth8 CPU bandwidth

Writ

e ne

w s

et p

oint

Writ

e ne

w s

et p

oint

Inte

rrupt

trig

gere

dIn

terru

pt tr

igge

red

ISR

beg

ins

ISR

beg

ins

ISR

end

sIS

R e

nds

Ret

urn

Ret

urn

Nex

t sam

ple

poin

tN

ext s

ampl

e po

int

Fixed by hardware

User configurable

Software dependent

Control loop delayControl loop delay

Figure 4-6 – Sample control loop timeline

Figure 4-6 shows the sequence of events which take place one each sample trigger on the C28x DSP. This processor is designed to automatically trigger sampling using a programmable timer. This ensures that sample points occur at regular intervals of time and avoids any “jitter” which might be induced by an interrupt initiated sample trigger.

The timeline diagram differentiates between unavoidable delays introduced by the hardware, and delays which are user configurable or software dependent and can therefore be influenced by the designer. The dominant contribution to servo delay usually comes from the control algorithm and it is important to make careful choices about both the algorithm structure and the processor on which it runs.


4. Implementation

Control Algorithm Structure Computational delay can sometimes be reduced by re-structuring the control algorithm. To illustrate this, let’s return to the example of the discrete PID controller derived earlier. We saw that this controller could be represented by the difference equation

)2()1()()2()( 321 −+−++−= keckeckeckuku

If we examine this calculation carefully, we see that to implement it on a computer we need to perform three multiplications and four additions. The immediate reaction is to perform all the operations in sequence each time a new value of e(n) is available, starting at the left and working through to the right. The sequence of operations performed by the controller is:

1. Read e(k)

2. Compute new u(k)

3. Update u(k)

The problem with this approach is that the entire computation occurs between the read and the write operations. This is the critical part of the algorithm because it delays the update and adds directly to the loop delay.

We can improve matters (sometimes greatly) by pre-computing those parts of the control law which are already known before the new value of e(n) becomes available. The part of the control law which can be pre-computed is given by

)2()1()2( 32 −+−+−= keckeckuv

This part of the law contains only previous values of e and u which are already known, and the fixed constants c2 & c3. If this value is already available at the time e(n) is read, the only remaining part of the control law which needs to be computed is

vkecku += )()( 1

This contains one multiplication and one addition, so in this simple example we have reduced the number of operations in the critical path from seven down to two. The new sequence to be performed by the controller is:

1. Read e(k)

2. Compute new u(k)

3. Update u(k)

4. Pre-compute v

The modified controller ISR timeline is shown below.


4. Implementation

time

Sam

ple

poin

tS

ampl

e po

int

ISR

beg

ins

ISR

beg

ins

ISR

end

sIS

R e

nds

Sam

ple

poin

tSa

mpl

e po

int

ISR

CONTEXTSAVE

READADC

COMPUTENEW

CONTROLUPDATE

CONTROLLER

PRE-COMPUTENEXT CONTROL

VALUEACKNOWLEDGE

INTERRUPT

CONTEXTRESTORE

Need to determine the cycle count of this!

CONTROLLERADCCS CRPRE-COMP ACKDAC

Figure 4-7 – Determination of controller latency

Now that we have defined what we require our controller to perform, we need to make a choice of processor on which to implement it.


4. Implementation

Choosing a Control Processor It is very important to understand that digital processors are not all the same! There are considerable differences in architecture and performance which can have a significant effect in a control application. Unfortunately this is a poorly understood subject, even among some processor vendors, and can lead to serious problems for the unwary user. Incorrect processor choice can lead to far greater expense and development effort, and in some cases an application may not work at all.

Before discussing how we choose a processor for a control application, it’s useful to review our requirements in the light of what we have just learned. There are many factors which engineers scrutinise when choosing a processor, but we now know that whichever processor we select, two critical requirements have to be met:

1. The processor must be capable of sampling the system at the chosen rate. At first sight, this requirement might seem to apply only to the data converters, but in fact it sets an important constraint on the performance of the processor. In each sample interval, the processor must read the input, compute the controller algorithm, and write a corrective output to the actuator before the next input sample arrives. Therefore the processor must be capable of executing the control algorithm quickly enough to keep pace with the sample rate, and this sets a lower limit on processing “power” required. The amount of processing power available is sometimes (confusingly) referred to as the bandwidth of the processor.

2. Any loop delay introduced by the processor must be minimised. This is a completely different constraint from that described above. It might well be possible for a processor to execute our control algorithm much faster than the sample interval, yet still introduce an unacceptable delay at each output. In order to assess the effect of servo delay, it must be possible to determine how much delay is contributed by the processor. This is a function not only of the efficiency with which the control algorithm is executed, but also the design of the processor and peripherals.

Some low bandwidth applications make only modest demands on the control processor which a micro-controller or micro-processor might easily be capable of meeting. However in cases where relatively high sample rates are required, a DSP (Digital Signal Processor) provides much better real-time performance. DSPs have an architecture which is optimised for handling real-time signals, and are commonly used in high-speed servo systems such as variable speed servo-motors and switching power supplies.

Classifying Processor Architectures Real-time processing applications tend to fall into two classes: those which collect and process blocks of data (block processing), and those in which each individual input sample needs to be processed separately (single sample processing). Time critical control applications invariably need single sample processing.

Consider first a block processing application, such as speech processing. Data would be sampled at a fixed rate by an external A/D converter and fed to the digital processor using a serial communications link. The processor would typically use an automatic Direct Memory Access (DMA) channel to move incoming data from the serial port into a pre-allocated memory buffer.


4. Implementation

When the input buffer is full, an interrupt service routine is triggered which re-directs incoming data to a separate storage buffer, and starts an algorithm to process the data and store the results in an output buffer. When the output buffer is full, a second DMA channel feeds it sequentially to an output port. This common approach to block processing is called “ping-pong” buffering, and is illustrated below.

u

RxBuf1

RxBuf2

Process

TxBuf1

TxBuf2c

Latency dependent on buffer size Latency dependent on buffer size Process latency fixed

1 2 3

DMA ch0 DMA ch1

Figure 4-8 – Block Processing

An important factor to consider is the latency inherent in this approach. In addition to the A/D conversion time and serial transmission delay, each incoming data sample has to wait in memory until the input buffer is filled before processing begins, then wait again in the output buffer until another DMA channel sends it to the output port. Clearly the approach is not optimised for low sample latency, and while this may be acceptable in a speech processing application it could easily de-stabilize a control loop.

In contrast, processors optimised for real-time control minimise the control loop latency by processing each input sample as soon as it becomes available. This is illustrated in Figure 4-9.

u

Process

Outputc

Timer

Result

Interrupt

S/HADC DAC


4. Implementation

Figure 4-9 – Single sample processing

In this case, the input signal is automatically sampled at a fixed rate determined by an internal programmable timer. Sampling is automatic, and the internal A/D converter avoids transmission and DMA delays. As soon as a new sample is available in the ADC result register, an interrupt is triggered and the controller algorithm is executed. The controller writes a new output correction to the D/A converter where it immediately takes effect.

Features such as DMA and cache memory, which work well in streaming applications, tend to degrade digital control performance and should be used with care. Furthermore, processors optimised for digital control tend to have important peripherals already integrated. Examples include A/D and D/A converters, specific serial communications ports, modules designed to interface with specific types of sensor. These can significantly reduce the overall cost of manufacture as well as simplify the hardware design.

CPU Bandwidth When selecting a suitable processor, one of the first criteria to apply is to determine whether it has sufficient performance to meet the real-time demands of the system. Having determined the sample rate we wish to use, we can easily calculate how many CPU cycles are available to the processor between samples based on its operating clock frequency.

available cycles = CPU clock frequency in Hz / sample rate in Hz

To determine CPU bandwidth we need to know something about how efficiently the processor will execute our control algorithm. Processors vary so much in their design and efficiency that often the only way to determine this is to obtain a sample device, write and run a representative controller algorithm, and measure the performance. This is known as “benchmarking”. Once the number of cycles required to run the controller is known, the CPU overhead can be calculated as shown below.

time

Sam

ple

poin

tS

ampl

e po

int

ISR

beg

ins

ISR

beg

ins

ISR

end

sIS

R e

nds

Sam

ple

poin

tS

ampl

e po

int

A CB

CPU overhead = Cycles in ISR

Cycles between sample points=

A + B + C

B ISR code

Other code

ISR


4. Implementation

Figure 4-10 – CPU bandwidth determination

Manufacturers often provide execution benchmarks for common algorithms, but there are no standards defining how these should be performed and the user should always treat such information with caution. Vendors are experts at performing their tests in the specific set of conditions in which their product performs best, and the results may not be representative of what the user will see if the device is applied in his own application. Possibly the only reliable way of assessing processor performance is for the user to write representative code and actually try it!

Quantization The quantization of data – an inherent property of all digital systems – is an important consideration for the designer.

Quantization arises from the conversion of an analogue signal into discrete form because of finite resolution of the data converter. An N-bit converter is capable of resolving to an accuracy of 2-N

of the input range, and this means all computations based on samples of input data will contain a random quantization error of +/- ½ a bit. Figure 4-11 shows the quantization error q resulting from the truncation and rounding of input data, where q = 2-N.

A detailed analysis of quantization leads to a complex non-linear model which is very difficult to analyze [3]. In this discussion we restrict ourselves to numeric issues faced by the programmer.

q

Truncation

q

n

x

x

e

Rounding

2q

±

q

n

x

x

e

Figure 4-11 – Quantization of input data


4. Implementation

Many digital processors have a “fixed-point” architecture, in which numbers are represented as a binary sequence of finite length. The range and resolution of representable numbers is limited by the number of bits available and this is defined by the “word length” of the chosen processor. In general the larger the word length, the greater the range of values which can be represented, but this is not the whole story.

Fixed-point numbers are represented in ‘Q’-format, which defines the position of a notional binary point in a number sequence, and hence the compromise between range and resolution available.

“Q” bit quotient1 bit sign

fffffffffffffffffffffffiiiiiiiis031 Q (Q-1)

“I”-1 bit integer

Figure 4-12 – Q-format binary representation

Figure 4-12 shows the 32-bit binary representation of a number in Q-format. The ‘Q’ denotes the number of bits to the right of the binary point, and therefore sets a limit on the available resolution. If we subtract this number from the word length, in this case 32, we know the number of bits to the left of the binary point, and therefore the available numeric range. Numbers larger or smaller than these cannot be represented in this Q-format [8].

Most fixed-point arithmetic is carried out in “two’s complement” form, in which the most significant bit (MSB) is used to denote the sign of the number. An MSB of 0 denotes a positive number and vice versa.

For example, a Q24 number has 24-bits of resolution, 7 bits of range, and one sign bit. By moving the position of the binary point, format can be adjusted to increase range at the expense of resolution, and vice-versa. Unsuitable choice of format can easily lead to the result of some computations being too small or large to be correctly represented, usually with serious consequences. Therefore it is important for the designer to predict numeric requirements of the application and to understand how to control format when writing code.

Both Matlab and Simulink contain tools for simulating the effects of fixed-point arithmetic, yet ultimately it is the responsibility of the programmer to detect and correct numeric issues in the code. In the past this was a laborious process of assembly programming, but today many processors have optimised fixed-point libraries available which allow the user to control numeric format using C code.

A good example of this is the C28x DSP from Texas Instruments. This processor has a 32-bit fixed-point architecture which immediately gives far greater range and resolution possibilities compared with 16-bit alternatives. Fixed-point arithmetic is supported on this processor through a software library known as “IQ Math”, which allows the user to control the position of the binary point (and hence the range/resolution trade-off) when coding in C [9]. This makes it easier to isolate areas of the program where numeric issues occur and to locally allocate a suitable Q-format.


4. Implementation

Instruction Set The most significant difference between a micro-controller and a DSP is evident in their instruction sets. Micro-controllers and micro-processors have a relatively small number of machine instructions available to them. In contrast, Digital Signal Processors have an rich instruction set which facilitates execution of control algorithms such as the 2-pole 2-zero controller.

The code shown in Appendix C implements such a controller on a C28x DSP. This is taken from a standard library of control functions for the C28x processor and while it may seem confusing at first, the code could be hand written with little effort by a moderately experienced programmer. The algorithm runs in 26 CPU cycles and maintains 32-bits of precision.

A feature of the DSP architecture is that single instructions combine more than one operation in a single CPU cycle. For example, the following line performs a signed 32-bit x 32-bit signed multiplication, shifts the previous result by a pre-determined number of bits and adds it to an internal register, and increments a pointer to the next data value.

QMPYAL P,XT,*XAR7++

This ability to perform multiple operations in parallel in a single machine cycle is a characteristic feature of DSP machine code and permits highly efficient implementation of the delay line and coefficient buffer required for computation of the control law.

Interrupt Latency Many processors are poor at responding to interrupts. As we have seen, in a control application it is imperative to respond quickly to control interrupts in order to minimise control loop latency, and processors truly optimised for control applications will have low interrupt latency.

The interrupt mechanism on the C28x DSP is a good example. Interrupt vectors are immediately loaded into the program counter to avoid the need to determine the interrupt source and calculate an ISR address. The core includes hardware to perform an automatic register context save when an interrupt occurs. This reduces the amount of code which needs to be executed by the ISR before it begins it’s real task and reduces the total latency.

LatencyLatency

Recognition Recognition delay (3) and delay (3) and SP alignment SP alignment

(1)(1)

44Recognition Recognition

delay (3) and delay (3) and SP alignment SP alignment

(1)(1)

44Get vector Get vector

(3 reg. (3 reg. pairs pairs

saved)saved)

33Get vector Get vector

(3 reg. (3 reg. pairs pairs

saved)saved)

33PF1/PF2/D1 PF1/PF2/D1

of ISR of ISR instruction instruction

(3 reg. pairs (3 reg. pairs saved)saved)

33PF1/PF2/D1 PF1/PF2/D1

of ISR of ISR instruction instruction

(3 reg. pairs (3 reg. pairs saved)saved)

33Save Save return return

addressaddress

11Save Save return return

addressaddress

11D2/R1/R2 of D2/R1/R2 of

ISR ISR instructioninstruction

33D2/R1/R2 of D2/R1/R2 of

ISR ISR instructioninstruction

33Sync ext. Sync ext.

signalsignal(ext. (ext.

interrupt interrupt only)only)

22Sync ext. Sync ext.

signalsignal(ext. (ext.

interrupt interrupt only)only)

22cycles

Assumes ISR in Assumes ISR in internal RAMinternal RAM

Internal Internal interrupt interrupt occurs occurs herehere

ext. ext. interrupt interrupt occurs occurs herehere

ISR ISR instruction instruction executed executed on next on next cyclecycle

Figure 4-13 – C28x interrupt latency


4. Implementation

The resulting cycle allocation is shown in the diagram above. Interrupt latency, measured as the number of cycles between the interrupt event and the execution of the first user instruction in the ISR, is a total of 14 or 16 cycles (depending on whether the source is internal or external) including a minimal context save. At 150 MHz this corresponds to less than 100 ns of interrupt latency.

Debugging Real-Time Systems

An important consideration which is often overlooked when selecting a control processor is how easily problems can be tracked down during development. In many conventional embedded applications, code is de-bugged by stopping the processor at an arbitrary point in the program, then stepping through the code one line at a time, examining internal memory and registers to verify the program behaves as intended. Unfortunately, embedded control systems pose particular difficulties when it comes to debugging code which mean this technique cannot always be used.

In a digital control system, the processor is an integral component of the control loop (see Figure 2-1). The loop is closed by the action of the control law being executed, so any attempt to stop the program will immediately open the loop and the process will be un-controlled. In some cases this can be catastrophic.

For example, consider a digital motor controller, in which the processor computes the duty cycle of multiple PWM signals in a switching inverter. The inverter generates voltage waveform which are fed to the stator windings to drive the motor, and the processor calculates the next output based on feedback of stator current and the reference input. In this type of system the processor is an integral and key component in the control loop: stop it from executing and the control loop is immediately broken. Turning motor shafts can accumulate considerable kinetic energy, so if the control loop is broken for any reason the results can be catastrophic. Our problem, then, is to debug our control algorithm without stopping it.

The C28x DSP has a feature which allows the user to debug code even in challenging situations such as this. On this processor, the user has the ability to differentiate between critical and non-critical interrupts, allowing critical events such as control loop interrupts to continue being serviced while non-critical code is halted for de-bugging. Without such a feature, tuning and debugging control code can be a much more lengthy and difficult task.

The non-intrusive nature of real-time mode allows target memory content to be streamed to the host without disrupting operation of the control processor. For example, a memory buffer containing a historical log of an important signal can be displayed, and it’s changes visualised in real-time. The effect is a little like being able to connect an oscilloscope to a software variable of interest and can be very useful when working with real-time signals.


4. Implementation

Processor architecture To conclude, we will examine two processors which typify architectures optimised for block processing and control applications. A good example of a the former is the Texas Instruments C64x DSP.

C64x+Megamodule

C64x+CPU

Data Path 1 Data Path 2M2xxxx

D2 S2 L2

A Register File B Register File

Instruction DecodeInstruction Dispatch

Instruction Fetch

Interrupt& ExceptionController

S1L1M1xxxx

D1

L2 Controller

L1D Controller

32

64

Memory Protection

Bandwidth Mgmt.

Megamodule Interface

DMA Slave I/F

IDM

A

128

256 256

SPLOOP Buffer

L1P Controller

Memory ProtectionBandwidth Mgmt.

Bandwidth Mgmt.

Memory Protection256

128

256

Master Port

(CPU/ cache req.)

128

Advanced Event

Triggering

Program & DataTrace

PowerControl

256

256

L1D Cache/SRAM

L1P Cache/SRAM

L2 Cache/SR

AM

128

256

• Program memory cache

• Dual data paths

• Multiple execution units

• Internal DMA

• Cache controller

• Twelve stage pipeline

• Data memory cache

• Register based architecture

• Level 2 memory cache

Figure 4-14 – C64x architecture block diagram

This processor has several features which lend themselves particularly well to processing blocks of data. Notice the presence of multiple DMA controllers, and a 2-level cache memory architecture. The core has two ‘data paths’, each consisting of four independent working units and an extensive set of registers. This allows the CPU to execute several instructions in parallel, speeding up the algorithm execution time.

However, as we saw with the simulation diagrams, control code is essentially sequential with each computation relying on the result from a previous one, so the benefits of a parallel core architecture are largely lost. Pipeline depth also has a bearing on latency as each program discontinuity, such as a branch or interrupt, must wait for the pipeline to be emptied before it can be taken.

By way of comparison, let’s look at the architecture of a processor designed for real-time control. The C28x processor, also from Texas Instruments, is an excellent example of a new class of processors known as “Digital Signal Controllers” (DSCs), which combine a DSP instruction set with integrated peripherals optimised for control applications.


4. Implementation

ARAU

XAR0-7 DP(16)

DataMemory

Data bus (32)

Program bus (32)

ACC

XT

P

ALU

MPY(32)

R/L(16)

R/L(16)R/L(16)

ProgramMemory

PC

Decoder

ADC

McBSP

CAN

SPI

SCI

CAP

QEP

PWMI/O MUX

XINTF

CPU TIMERS

REAL-TIMEDEBUG

INTERRUPTMANAGER

WATCHDOG

CPUData

AddressGenerator

Figure 4-15 – C28x architecture block diagram

The CPU core is identified by the red dashed line. Notice this design has three main registers – the accumulator (ACC), temporary register (XT), and product register (P). The XP & P registers are associated with the multiplier, while the accumulator is the main working register of the core and is independent of the multiplier. As the simulation diagrams suggested, a processor capable of performing a series multiplications of data and control coefficients, and of accumulating (adding) the results, should be efficient at executing a typical control algorithm

Notice also the presence of an integrated A/D converter, which avoids the communication delay which would be present if an external converter were used. An important feature is represented by the line between the PWM block and the ADC. This processor has the ability to synchronise the sampling instant with a programmable internal timer. As we have seen, it is vital to be able to control accurately the sampling period, and to avoid any uncertainty, or ‘jitter’. The ability to sample and initiate an A/D conversion without any software intervention is a critical requirement in a processor optimised for digital control.

The C28x has several other integrated features useful for digital control, such as multiple PWM pattern generators, and a real-time debug unit which was explained earlier.

It’s also interesting to see which features are not present. Comparing with the diagram of the C64x processor shown earlier, we see there is no cache memory controller. The C28x uses a flat memory space to avoid the cache load delay each time a cache miss takes place. We also notice the absence of DMA – unnecessary in a single sample processing approach.


Summary

Summary This document has sought to provide an introduction to the subject of control design using digital processors. In spite of the limited scope and inherently mathematical nature of the material, an attempt has been made to describe the subject in a way accessible to the analogue design engineer with little or no digital experience.

We have reviewed some fundamental concepts in control theory, and introduced the subject of sampled data systems by applying an impulse modulation function at fixed time intervals to an arbitrary continuous time signal. The result was seen to be a class of complex functions involving the sample period, T. The z-transform was introduced as a means of simplifying the representation and manipulation of such signals. The dependence of sampled data representations on sampling period has been encountered many times, as has the frequency dependent phase lag introduced by the zero-order hold.

Turning to the subject of digital controller design, we explained how continuous time controllers can be converted into equivalent discrete forms using various transformation techniques. We also saw how to construct designs based on a discretized model of the plant, using pole placement and frequency response techniques in conjunction with the SISOTOOL software suite.

Finally, we examined some issues pertinent to the implementation of discrete controllers on a digital processor. The necessity to meet sample rate and servo lag specifications from the design result in an architecture which differs in several respects from general-purpose micro-controllers and DSPs. Although much can be gained by careful examination of processor architecture, it is very difficult to predict how any device will perform in a control application, and the user is well advised to conduct representative benchmark tests before deciding on a specific part.

As the range of control applications served by embedded processors continues to expand, the need for engineers skilled in digital controller design, and for processors capable of meeting their stringent real-time requirements, must only be expected to increase.


Appendix A

Appendix A Table of Laplace & z-transforms for basic time functions

Laplace Transform F(s) Time Function f(t) z-transform F(z)

)(tδ1 1

nz1nTe− )( nTt −δ

1−zz

s1 )(1 t

2)1( −zTz

21s

t

3

2

)1(2)1(

−+

zzzT

31s

25.0 t

aTezz−−as +

1 ate−

2)( aT

aT

ezTze

−

−

−2)(1as +

atte−

1cos2sin

2 +− tzztzω

ω22 ω

ω+s

tωsin

1cos2cos

2

2

+−−

tzztzz

ωω

22 ω+ss tωcos

22)( ωω++ as

te at ωsin−

aTaT

aT

etzeztze

22 cos2sin

−−

−

+− ωω

aTaT

aT

etzeztzez

22

2

cos2cos

−−

−

+−−

ωω

22)( ω+++

asas

te at ωcos−


Appendix B

Appendix B

References

1. J.Schwarzenbach & K.F.Gill, System Modelling & Control, Edward Arnold, 1992

2. Gene F. Franklin, J. David Powell & Michael L. Workman, Digital Control of Dynamic Systems, Addison-Wesley, 1998

3. K.J.Astrom & B.Wittenmark, Computer Controlled Systems, Prentice Hall, 1997

4. J.J.DiStefano, A.R.Stubberud & I.J.Williams, Schaum’s Outline of Feedback & Control Systems, McGraw-Hill, 1995

5. William L. Brogan, Modern Control Theory, Prentice-Hall, 1991 6. Benjamin C. Kuo, Automatic Control Systems, Wiley, 1995 7. Paul A. Lynn, An Introduction to the Analysis and Processing of Signals,

MacMillan, 1990 8. Control System compensation and Implementation with the TMS32010, Texas

Instruments, SPRA009 9. IQ Math Library, Texas Instruments, SPRC086


Appendix C

Appendix C

C28x assembly code implementation of 2-pole 2-zero controller ; e(n)=Vref-Vout MOVU ACC,@Vref SUBU ACC,*XAR2++ LSL ACC,#8 ; ACC=e(n) (Q24) MOVL @VCNTL_DBUFF+4,ACC ZAPA ; Voltage control law

MOVL XT,@VCNTL_DBUFF+8 ; XT=e(n-2) QMPYAL P,XT,*XAR7++ ; b2*e(n-2) MOVDL XT,@VCNTL_DBUFF+6 ; XT=e(n-1), e(n-2)=e(n-1)

QMPYAL P,XT,*XAR7++ ; ACC=b2*e(n-2) P=b1*e(n-1) MOVDL XT,@VCNTL_DBUFF+4 QMPYAL P,XT,*XAR7++ MOVL XT,@VCNTL_DBUFF+2 ; XT=u(n-2) QMPYAL P,XT,*XAR7++ ; P=a2*u(n-2)

MOVDL XT,@VCNTL_DBUFF ; XT=u(n-1), u(n-2)=u(n-1) QMPYAL P,XT,*XAR7++ ; ACC=a2*u(n-2) ADDL ACC,P ; ACC=a2*u(n-2)+ a1*u(n-1) LSL ACC,#(23-VCNTL_QF+8) ; (Q23) ADDL ACC,ACC ; (Q24) MOVL @VCNTL_DBUFF,ACC ; ACC=u(n) ; Saturate the result [min,max] MINL ACC,*XAR7++ MAXL ACC,*XAR7++ ; Duty Cycle Modulation MOVL XT,ACC QMPYL P,XT,*XAR7++ ;(Q0) MOV *XAR3++,P


Appendix D

Appendix D

Frequency Response Demonstration of Sampled Systems % script to demonstrate frequency response of sampled systems % 1 % Gp(s) = ------- % s(s + 1) % % ZOH approximation used % sample rates: 0.2, 1, 2 seconds % examination of phase lag introduced by sampling Gp = tf(1, [1 0]) * tf(1, [1 1]); % construct TF % set sample times in seconds Ts1 = 0.2; Ts2 = 1; Ts3 = 2; % discrete conversions Gpz1 = c2d(Gp, Ts1, 'zoh'); % Ts = 0.2 sec Gpz2 = c2d(Gp, Ts2, 'zoh'); % Ts = 1 sec Gpz3 = c2d(Gp, Ts3, 'zoh'); % Ts = 2 sec % collect frequency data [Mc, Phc, wc] = bode(Gp); [Mz1, Phz1, wz1] = bode(Gpz1); [Mz2, Phz2, wz2] = bode(Gpz2); [Mz3, Phz3, wz3] = bode(Gpz3); % get length of frequency scales ac = size(Phc); a1 = size(Phz1); a2 = size(Phz2); a3 = size(Phz3); % create phase arrays nc = (1:1:ac(3))'; n1 = (1:1:a1(3))'; n2 = (1:1:a2(3))'; n3 = (1:1:a3(3))'; % load phase arrays for k = 1:ac(3) nc(k) = Phc(k); end for k = 1:a1(3) n1(k) = Phz1(k); end for k = 1:a2(3) n2(k) = Phz2(k); end for k = 1:a3(3) n3(k) = Phz3(k); end % normalize frequency scales wz1_norm = wz1 * Ts1; wz2_norm = wz2 * Ts2; wz3_norm = wz3 * Ts3; rad_deg_k = 360 / (2 * pi); % calc phase error for Ts1 for k = 1:a1(3)


Appendix D

H(k) = freqresp(Gp, wz1(k)); % get system response at discrete frequency PH(k) = angle(H(k)) * rad_deg_k; % get phase angle at discrete fre-quency delta_ph1(k) = PH(k) - n1(k); % calc phase error end % calc phase error for Ts2 for k = 1:a2(3) H(k) = freqresp(Gp, wz2(k)); % get system response at discrete frequency PH(k) = angle(H(k)) * rad_deg_k; % get phase angle at discrete fre-quency delta_ph2(k) = PH(k) - n2(k); % calc phase error end % calc phase error for Ts3 for k = 1:a3(3) H(k) = freqresp(Gp, wz3(k)); % get system response at discrete frequency PH(k) = angle(H(k)) * rad_deg_k; % get phase angle at discrete fre-quency delta_ph3(k) = PH(k) - n3(k); % calc phase error end % plot graphs figure; % plot(wc, nc); hold all; plot(wz1_norm, delta_ph1); plot(wz2_norm, delta_ph2); plot(wz3_norm, delta_ph3); grid on; % calc w/2 line zoh_phase = wz1_norm * rad_deg_k / 2; plot(wz1_norm, zoh_phase); % add legends xlabel('Normalized frequency (wT)'); ylabel('Phase error (deg)'); legend('0.2 sec','1 sec','2 sec','wT/2'); title('Phase error introduced by sampling'); % end


Notes

Notes


Notes


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