Introduction to Computer Engineering { EECS...
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Introduction to Computer Engineering – EECS 203 http://ziyang.eecs.northwestern.edu/ ∼ dickrp/eecs203/ Instructor: Robert Dick Office: L477 Tech Email: [email protected] Phone: 847–467–2298 TA: Neal Oza Office: Tech. Inst. L375 Phone: 847-467-0033 Email: [email protected] TT: David Bild Office: Tech. Inst. L470 Phone: 847-491-2083 Email: [email protected]
Transcript of Introduction to Computer Engineering { EECS...
Introduction to Computer Engineering – EECS 203http://ziyang.eecs.northwestern.edu/∼dickrp/eecs203/
Instructor: Robert DickOffice: L477 TechEmail: [email protected]: 847–467–2298
TA: Neal OzaOffice: Tech. Inst. L375Phone: 847-467-0033Email: [email protected]
TT: David BildOffice: Tech. Inst. L470Phone: 847-491-2083Email: [email protected]
Transmission gatesTwo-level logic
KmapsHomework
Outline
1. Transmission gates
2. Two-level logic
3. Kmaps
4. Homework
2 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
CMOS transmission gate (TG)
C
A
C
B
C = 1
C = 0
3 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
CMOS transmission gate (TG)
C
A
C
B
C = 1
C = 0
3 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
CMOS transmission gate (TG)
C
A
C
B
C = 1
C = 0
B = A
3 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
CMOS transmission gate (TG)
C
A
C
B
3 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
CMOS transmission gate (TG)
C
A
C
B
C = 0
C = 1
3 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
CMOS transmission gate (TG)
C
A
C
B
C = 0
C = 1
blocked
blocked
3 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
CMOS transmission gate (TG)
C
A
C
B
C = 0
C = 1
blocked
blocked
B =High-Z
3 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
CMOS transmission gate (TG)
C
A
C
B
3 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Other TG diagram
4 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
TG example
a a b b
0
1
f
5 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Impact of control on input
=
TG’s resistance
0
1
0
6 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Impact of control on input
=
TG’s resistance
1
a
0
0
1
0
6 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Impact of control on input
=
TG’s resistance
1
a
0
=
a’s internal resistance
TG’s resistance
0
1
0
6 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Outline
1. Transmission gates
2. Two-level logic
3. Kmaps
4. Homework
7 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Practice w/ Boolean Minimization
Simplify this expression so that it has the minimal possible literalcount: (
a + b)
(a b + cd)
8 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-Level Logic and Canonical Forms
The previous example illustrated one standard representation(product of sums).
These standard forms are known collectively as two-level logic:
Product of Sums (POS) e.g.
f =(a + b
)(a + b)
Sum of Products (SOP) e.g.
f = a b + ab
Can you see why these two are equivalent?
Why is this known as two-level logic?
9 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Canonical forms - SOP
For Sum of Products (SOP) the canonical form is constructed out ofminterms.
Product term in which all variables appear in complemented oruncomplemented forms once
For an n-input function corresponds to one of of 2n possibleinput combinations
Use binary representation to enumerate minterms
10 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Canonical forms – SOP
x y z term symbol m0 m1 m2 m3 m4 m5 m6 m7
0 0 0 x y z m0 1 0 0 0 0 0 0 00 0 1 x y z m1 0 1 0 0 0 0 0 00 1 0 x yz m2 0 0 1 0 0 0 0 00 1 1 x yz m3 0 0 0 1 0 0 0 01 0 0 xy z m4 0 0 0 0 1 0 0 01 0 1 xy z m5 0 0 0 0 0 1 0 01 1 0 xyz m6 0 0 0 0 0 0 1 01 1 1 xyz m7 0 0 0 0 0 0 0 1
11 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Using Canonical Sum of Products Representation
Convenient representation uses∑
operator and minterms:
f (x1, . . . , xn) =∑
mi
For given function f, list all minterms for which the function is true:
f (a, b, c) = ab + a c
= (m6 + m7) + (m0 + m2)
=∑
m (0, 2, 6, 7)
12 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Using Canonical Sum of Products Representation
Convenient representation uses∑
operator and minterms:
f (x1, . . . , xn) =∑
mi
For given function f, list all minterms for which the function is true:
f (a, b, c) = ab + a c
= (m6 + m7) + (m0 + m2)
=∑
m (0, 2, 6, 7)
12 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Using Canonical Sum of Products Representation
Convenient representation uses∑
operator and minterms:
f (x1, . . . , xn) =∑
mi
For given function f, list all minterms for which the function is true:
f (a, b, c) = ab + a c
= (m6 + m7) + (m0 + m2)
=∑
m (0, 2, 6, 7)
12 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Using Canonical Sum of Products Representation
Convenient representation uses∑
operator and minterms:
f (x1, . . . , xn) =∑
mi
For given function f, list all minterms for which the function is true:
f (a, b, c) = ab + a c
= (m6 + m7) + (m0 + m2)
=∑
m (0, 2, 6, 7)
12 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Canonical forms – POS
For Products of Sums (POS) the canonical form is constructed out ofmaxterms.
Sum term in which all variables appear in complemented oruncomplemented forms once
Use binary representation to enumerate maxterms (note:function is not true for maxterms)
13 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Canonical forms – POS
x y z term symbol M0 M1 M2 M3 M4 M5 M6 M7
0 0 0 x + y + z M0 0 1 1 1 1 1 1 10 0 1 x + y + z M1 1 0 1 1 1 1 1 10 1 0 x + y + z M2 1 1 0 1 1 1 1 10 1 1 x + y + z M3 1 1 1 0 1 1 1 11 0 0 x + y + z M4 1 1 1 1 0 1 1 11 0 1 x + y + z M5 1 1 1 1 1 0 1 11 1 0 x + y + z M6 1 1 1 1 1 1 0 11 1 1 x + y + z M7 1 1 1 1 1 1 1 0
14 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Using Canonical Products of Sums Representation
Convenient representation uses∏
operator and minterms:
f (x1, . . . , xn) =∏
Mi
For given function f, list all maxterms for which the function is false:
f (a, b, c) = (a + c ) (a + b)
= M1 ·M3 ·M4 ·M5
=∏
M (1, 3, 4, 5)
15 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Using Canonical Products of Sums Representation
Convenient representation uses∏
operator and minterms:
f (x1, . . . , xn) =∏
Mi
For given function f, list all maxterms for which the function is false:
f (a, b, c) = (a + c ) (a + b)
= M1 ·M3 ·M4 ·M5
=∏
M (1, 3, 4, 5)
15 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Using Canonical Products of Sums Representation
Convenient representation uses∏
operator and minterms:
f (x1, . . . , xn) =∏
Mi
For given function f, list all maxterms for which the function is false:
f (a, b, c) = (a + c ) (a + b)
= M1 ·M3 ·M4 ·M5
=∏
M (1, 3, 4, 5)
15 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Using Canonical Products of Sums Representation
Convenient representation uses∏
operator and minterms:
f (x1, . . . , xn) =∏
Mi
For given function f, list all maxterms for which the function is false:
f (a, b, c) = (a + c ) (a + b)
= M1 ·M3 ·M4 ·M5
=∏
M (1, 3, 4, 5)
15 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
More examples of two-level logic
f (a, b, c , d) =∑
m(1, 4, 8, 10, 13, 15)
f (w , x , y , z) =∏
M(5, 13, 14)
f (u, v) = u + u v
16 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Logic minimization motivation
Want to reduce area, power consumption, delay of circuits
Hard to exactly predict circuit area from equations
Can approximate area with SOP cubes
Minimize number of cubes and literals in each cube
Algebraic simplification difficult
Hard to guarantee optimality
17 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Logic minimization motivation
K-maps work well for small problems
Too error-prone for large problemsDon’t ensure optimal prime implicant selection
Quine-McCluskey optimal and can be run by a computer
Too slow on large problems
Some advanced heuristics usually get good results fast on largeproblems
Want to learn how these work and how to use them?
Take Advanced Digital Logic Design
18 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Boolean function minimization
Algebraic simplification
Not systematicHow do you know when optimal solution has been reached?
Optimal algorithm, e.g., Quine-McCluskey
Only fast enough for small problemsUnderstanding these is foundation for understanding moreadvanced methods
Not necessarily optimal heuristics
Fast enough to handle large problems
19 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Outline
1. Transmission gates
2. Two-level logic
3. Kmaps
4. Homework
20 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Karnaugh maps (K-maps)
Fundamental attribute is adjacency
Useful for logic synthesis
Helps logic function visualization
General Idea: Circle groups of output values (typically 1’s)
Result: Circled terms correspond to minimized product terms
21 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Karnaugh maps
0 1a
a
0 1
b
a
00 01
10 11
0
1
1
a
b0
22 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Karnaugh maps
0 1a
a
0 1
b
a
00 01
10 11
0
1
1
a
b0
bc
0
1a
c
a
b
10110100
22 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Karnaugh maps
0 1a
a
0 1
b
a
00 01
10 11
0
1
1
a
b0
bc
0
1a
c
a
b
10110100
ab
10110100
00
01
11
10
cd
a
b
c
d
22 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Sum of products (SOP) - Truth table
a b f
0 0 10 1 01 0 01 1 1
f =(a b)
+ (ab)
23 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Sum of products (SOP) - KMap
Equivalent way of expressing the same function:
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
(a b)
+ (ab)
24 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Sum of products (SOP) - KMap
Equivalent way of expressing the same function:
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
(a b)
+
(ab)
24 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Sum of products (SOP) - KMap
Equivalent way of expressing the same function:
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
(a b)
+ (ab)
24 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Some definitions
implicant - a product term (or sum term) which covers/includesone or more minterms (or maxterms)
prime implicant - implicant that cannot be covered by a moregeneral implicant (i.e. one with fewer literals)
essential prime implicants - cover an output of the function thatno other prime implicant (or sum thereof) is able to cover
25 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Some definitions
implicant - a product term (or sum term) which covers/includesone or more minterms (or maxterms)
prime implicant - implicant that cannot be covered by a moregeneral implicant (i.e. one with fewer literals)
essential prime implicants - cover an output of the function thatno other prime implicant (or sum thereof) is able to cover
25 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Some definitions
implicant - a product term (or sum term) which covers/includesone or more minterms (or maxterms)
prime implicant - implicant that cannot be covered by a moregeneral implicant (i.e. one with fewer literals)
essential prime implicants - cover an output of the function thatno other prime implicant (or sum thereof) is able to cover
25 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Some definitions
implicant - a product term (or sum term) which covers/includesone or more minterms (or maxterms)
prime implicant - implicant that cannot be covered by a moregeneral implicant (i.e. one with fewer literals)
essential prime implicants - cover an output of the function thatno other prime implicant (or sum thereof) is able to cover
25 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Implicants
For now, treat × as a “wildcard”
implicant
0
1
00
10
1 1 1 1
1
01 11 10f(a,b,c)
a
bc
26 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Implicants
For now, treat × as a “wildcard”
implicant
0
1
00
10
1 1 1 1
1
01 11 10f(a,b,c)
a
bc
26 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Implicants
For now, treat × as a “wildcard”
implicant
0
1
00
10
1 1 1 1
1
01 11 10f(a,b,c)
a
bc
26 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Implicants
For now, treat × as a “wildcard”
prime implicant
0
1
00
10
1 1 1 1
1
01 11 10f(a,b,c)
a
bc
26 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Implicants
For now, treat × as a “wildcard”
essential prime implicant
0
1
00
10
1 1 1 1
1
01 11 10f(a,b,c)
a
bc
Prime implicants are not covered by other implicants
26 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Implicants
For now, treat × as a “wildcard”
0
1
00
10
1 1 1 1
1
01 11 10f(a,b,c)
a
bc
Essential prime implicants uniquely cover minterms
26 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Implicants
For now, treat × as a “wildcard”
0
1
00
10
1 1 1 1
1
01 11 10f(a,b,c)
a
bc
26 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
K-map example
Minimize f (a, b, c , d) =∑
(1, 3, 8, 9, 10, 11, 13)
f(a, b, c, d) = ab + b d + ac d
27 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
K-map example
Minimize f (a, b, c , d) =∑
(1, 3, 8, 9, 10, 11, 13)
f(a, b, c, d) = ab + b d + ac d
27 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
K-map simplification technique
For all minterms
Find maximal groupings of 1’s and X’s adjacent to that minterm.
Remember to consider top/bottom row, left/right column, andcorner adjacencies.
These are the prime implicants.
28 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
K-map simplification technique
Revisit the 1’s elements in the K-map.
If covered by single prime implicant, the prime is essential, andparticipates in final cover.
The 1’s it covers do not need to be revisited.
29 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
K-map simplification technique
If there remain 1’s not covered by essential prime implicants,
Then select the smallest number of prime implicants that coverthe remaining 1’s.
This can be difficult for complicated functions.
Will present an algorithm for this in a future lecture.
30 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Product of sums (POS)
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
(a + b)
·(a + b
)
31 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Product of sums (POS)
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
(a + b) ·
(a + b
)31 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Product of sums (POS)
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
(a + b)
·
(a + b
)31 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Product of sums (POS)
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
0 1
10
1 10
0
(a + b) ·(a + b
)31 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
POS K-map techniques
Direct reading by covering zeros and inverting variables
Or
Invert function
Do SOP
Invert again
Apply De Morgan’s laws
32 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
POS K-map example
Minimize f (a, b, c) =∏
(2, 4, 5, 6)
f (a, b, c) = (b + c)(a + b)
33 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
POS K-map example
Minimize f (a, b, c) =∏
(2, 4, 5, 6)
f (a, b, c) = (b + c)(a + b)
33 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
b c
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
b d
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
abd
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
ac d
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
abc
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
acd
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
b c + b d + ac d + abc
34 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Six-variable K-map example
z(a, b, c , d , e, f ) =∑
(2, 8, 10, 18, 24, 26, 34, 37, 42, 45, 50, 53, 58, 61)
35 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Six-variable K-map example
CD
EF
CD
EF
AB =00
AB =01
00 01 11 10
00
01
11
10
00 01 11 10
00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
16 20 28 24
17 21 29 25
19 23 31 27
18 22 30 26
CD
EF
AB =11
00 01 11 10
00
01
11
10
48 52 60 56
49 53 61 57
51 55 63 59
50 54 62 58
CD
EF
AB =10
00 01 11 10
00
01
11
10
32 36 44 40
33 37 45 41
35 39 47 43
34 38 46 42
CD
EF
CD
EF
AB =00
AB =01
00 01 11 10
00
01
11
10
00 01 11 10
00
01
11
10
CD
EF
AB =11
00 01 11 10
00
01
11
10
CD
EF
AB =10
00 01 11 10
00
01
11
10
1
1 1
1
1 1
1 1
1 1
1 1
1 1
36 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Six-variable K-map example
z(a, b, c , d , e, f ) = d ef + ade f + a Cd f
37 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Don’t Care logic
All specified Boolean values are 0 or 1
However, during design some values may be unspecified
Don’t care values (×)
×s allow circuit optimization, i.e.,
Incompletely specified functions allow optimization
38 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Don’t Care values
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
39 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Don’t Care values
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
Can let the undefined values be zero
Correct. . . however, complicated(a b)
+ (ab)
39 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Don’t Care values
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
Can let the undefined values be zero
Correct. . . however, complicated(a b)
+ (ab)
39 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Don’t Care values
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
Instead, leave these values undefined (×)
Also called Don’t Care values
Allows any function implementing the specified values to be used
E.g., could use(a b)
+ (ab)
However, best to use simpler 1
39 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Don’t Care values
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
0 1
10
1 1
39 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Satisfiability Don’t Cares
0
0 1
10
1 1wheelsensor
brakesensor
output
0 0
10
1
1
decision
8
32
apply brake
pulse brake
invalid output
release brake
0
1
Input can never occur
This can happen within a circuit
Some modules will not be capable of producing certain outputs
40 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Observability Don’t Cares
<
0 1
1
0 1
10
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
Output will be ignored for certain inputs
41 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Observability Don’t Cares
<
0 1
1
0 1
10
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
Output will be ignored for certain inputs
41 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Observability Don’t Cares
<
0 1
1
0 1
10
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
Output will be ignored for certain inputs
41 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Observability Don’t Cares
<
0 1
1
0 1
10
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
Output will be ignored for certain inputs
41 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Observability Don’t Cares
<
0 1
1
0 1
10
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
<
0 1
1
0 1
10
1
0 1
1
0
0
0 0
1
0 1
1
0 0
1
Output will be ignored for certain inputs
41 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Don’t care K-map example
Minimize f (w , x , y , z) =∑
(1, 3, 8, 9, 10, 11, 13) + d(5, 7, 15)
f (w , x , y , z) = wx + z
42 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Don’t care K-map example
Minimize f (w , x , y , z) =∑
(1, 3, 8, 9, 10, 11, 13) + d(5, 7, 15)
f (w , x , y , z) = wx + z
42 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level logic is necessary
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
Some Boolean functions can not be represented with one logic level(a b)
+ (ab)
43 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level logic is necessary
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
Some Boolean functions can not be represented with one logic level(a b)
+ (ab)
43 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level logic is necessary
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
Some Boolean functions can not be represented with one logic level(a b)
+ (ab)
43 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level logic is necessary
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
Some Boolean functions can not be represented with one logic level(a b)
+ (ab)
43 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level logic is necessary
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
0 1
10
1 1
0
0
Some Boolean functions can not be represented with one logic level(a b)
+ (ab)
43 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level logic is sufficient
0 1
10
1 1
0
0
bf(a,b)
a
All Boolean functions can be represented with two logic levels
Given k variables, 2K minterm functions exist
Select arbitrary union of minterms
44 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level well-understood
As we will see later, optimal minimization techniques known fortwo-level
However, optimal two-level solution may not be optimal solution
Sometimes a suboptimal solution to the right problem is betterthan the optimal solution to the wrong problem
45 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level sometimes impractical
00 11 1001
0 1
1
1
01
00
11
10 1
0
0
0
00
0 0
1
1 1
1
f(a,b,c ,d)cd
ab
Consider a 4-term XOR (parity) gate: a⊕ b ⊕ c ⊕ d(a b c d
)+(a b cd
)+(a bc d
)+ (a bcd) + (abc d) +
(abcd
)+(
ab c d)
+(ab cd
)
46 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level sometimes impractical
Consider a 4-term XOR (parity) gate: a⊕ b ⊕ c ⊕ d(a b c d
)+(a b cd
)+(a bc d
)+ (a bcd) + (abc d) +
(abcd
)+(
ab c d)
+(ab cd
)
46 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level weakness
Two-level representation is exponential
However, it’s a simple concept
Is∑n
i xi odd?
Problem with representation, not function
47 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Two-level weakness
Two-level representations also have other weaknesses
Conversion from SOP to POS is difficult
Inverting functions is difficult·-ing two SOPs or +ing two POSs is difficult
Neither general POS or SOP are canonical
Equivalence checking difficult
POS satisfiability ∈ NP-complete
48 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Outline
1. Transmission gates
2. Two-level logic
3. Kmaps
4. Homework
49 R. Dick Introduction to Computer Engineering – EECS 203
Transmission gatesTwo-level logic
KmapsHomework
Reading assignment
M. Morris Mano and Charles R. Kime. Logic and ComputerDesign Fundamentals. Prentice-Hall, NJ, fourth edition, 2008
Section 2.6
Also read TTL reference, Don Lancaster. TTL Cookbook.Howard W. Sams & Co., Inc., 1974, as needed
50 R. Dick Introduction to Computer Engineering – EECS 203
