Introduction to ASIC Design

Synopsys University Courseware2008 Synopsys, Inc.

Lecture - 1Developed By: Paul D. Franzon

Introduction to ASIC Design



Outline

1. The wonderful world of Silicon2. Application Specific Integrated Circuits (ASICs)• Typical applications, types, decision making1. ASIC Design Flow2. Trends



The Wonderful World of Silicon

“Moores Law”•About every eighteen months, the number of transistors on a CMOS silicon chip doubles and the clock speed doublesTransistors/Chip increasing by 50% per year (by 4× in 3.5 years)Gate Delay decreasing by 13% per year (by ½ in 5 years)

•This rate of improvement will continue until about 2018 at least.



Technology Drivers

• Decreasing lithographic feature size, e.g. measured by the transistor gate length:

0.13 μm, 0.090 μm, 0.065 μm, … 0.01 μm(?)

• Increasing wafer size: 8 inch diameter….. 12 in.

• Increasing number of metal interconnect layers:

6 ….. 8 …… 9 ….



Cost Scaling

• Cost per transistor scales down: Approximately constant cost per wafer to manufacture: About $2,000 - $4,000 per wafer Increasing IC yields for ‘large’ (> 1 sq. cm.chips): 60% …. 90%

• But cost to first chip scales up! Design cost increases with transistor count Mask cost increases with each new family



Semiconductor Roadmap

Projections for ‘leading edge’ ASIC/MPU: (www.itrs.net)



Other Scaling Trends

The impact of the wiring increases with each generation



ASICs vs. What?

Application Specific Integrated Circuit•A chip designed to perform a particular operation as opposed to General Purpose integrated circuits•An ASIC is generally NOT software programmable to perform a wide variety of different tasks

An ASIC will often have an embedded CPU to managesuitable tasks

An ASIC may be implemented as an FPGA (see later)•Sometimes considered a separate category



ASICs vs. What? (contd.)

General Purpose Integrated Circuits:Examples:•Programmable microprocessors (e.g. Intel Pentium Series, Motorola HC-11)Used in PCs to washing machinesProgrammable Digital Signal Processors (e.g. TI TMS 320 Series)

•Used in many multimedia, sensor processing and communications applications Memory (dRAM, SRAM, etc.)



Examples of ASICs

• Video processor to decode or encode MPEG-2 digital TV signals

• Low power dedicated DSP/controller /convergence device for mobile phones

• Encryption processor for security• Many examples of graphics chips• Network processor for managing packets, traffic flow,

etc.



ASIC Styles

Full Custom ASICs•Every transistor is designed and drawn by Hand•Typically only way to design analog portions of ASICs•Gives the highest performance but the longest design time•Full set of masks required for fabrication



ASIC Styles (Contd.)

Standard-Cell-Based ASICs• or ‘Cell Based IC’ (CBIC) or ‘semi-custom’•Standard Cells are custom designed and then inserted into a library•These cells are then used in the design by being placed in rows and wired together using ‘place and route’ CAD tools•Some standard cells, such as RAM and ROM cells, and some datapath cells (e.g. a multiplier) are tiled together to create macrocells

NOR gate:D-flip-flop:



Standard Cell ASICs (cont’d)

Sample ASIC floorplan:•Standard Cell designs are usually synthesized from an RTL (Register Transfer Language) description of the design

•Full set of masks (22+) still required



Cell based ASICs (cont’d)

Fabless semiconductor company model

•Company does design only. Fab performed by another company (e.g. TSMC, UMC, IBM, Philips, LSI).

•Back-end (place and route, etc.) might be performed at that company or with their assistance



ASIC Styles (cont’d)

Gate-Array Based ASICs

•In a gate array, the transistors level masks are fully defined and the designer can not change them

•The design instead programs the wiring and vias to implement the desired function

•Gate array designs are slower than cell-based designs but the implementation time is faster as less time must be spent in the factory

•RTL-based methods and synthesis, together with other CAD tools, are often used for gate arrays.



Gate Array (cont’d)

Examples:

Chip Express

•Wafers built with sea of macros + 4 metal layers

•2 metal layers customized for application

•Only 4 masks!

Triad Semiconductor

•Analog and Digital Macros

•1 metal layer for customization (2 week turnaround)



ASIC Styles (cont’d)

Programmable Logic Devices (PLDs and FPGAs)•FPGA= Field Programmable Gate Array

•Are off-the-shelf ICs that can be programmed by the user to capture the logic

•There are no custom mask layers so final design implementation is a few hours instead of a few weeks

•Simple PLDs are used for simple functions.

•FPGAs are increasingly displacing standard cell designs.

•Capable of capturing 100,000+ designed gates

•High power consumption

•High per-unit cost



FPGA (cont’d)

Sample internal architecture:•Store logic in look-up table (RAM)•Programmable interconnect

Programmable Interconnect Array:

Configurable Logic Block (CLB):



FPGA (cont’d)



Example

Total cost calculation:



Comments

Market currently dominated by standard cell ASICs and FPGAs•Ideally standard cell designs would be used for higher volume applications that justify the NRE

Many consider FPGAs separate from ASICs. Why?•Different level of design skills required, especially in “back end” (place and route or physical design)•Reduced level of verification required before “sending to factory”•Again reduces sophistication required of team•Low-cost (barrier) of entry•Often different, lower cost Design Automation (CAD) tools•Lower performance

However, front-end design (RTL coding) is virtually identical for each

implementation style

Sometimes FPGA done first and standard cell ASIC done later



ASIC Design Flow

Major Steps:

1.High Level Design•Specification Capture•Design Capture in C, C++, SystemC or SystemVerilog (etc.)•HW/SW partitioning•IP selection (choose from pre-existing designs or “Intellectual

Property”)

1.RTL Design•Major topic of this course

1.System, Timing and Logic Verification•Is the logic working correctly?



ASIC Design Flow

1. Physical Design• Floorplanning, Place and Route, Clock insertion

1. Performance and Manufacturability Verification• Extraction of Physical View• Verification of timing and signal integrity• Design Rule Checking



ASIC Design Methodology

Most ASICs are designed using a RTL/Synthesis basedmethodologyDesign details captured in a simulatable description of the hardware•Captured as Register Transfer Language (RTL)•Simulations done to verify design



Methodology (cont’d)

Automatic synthesis is used to turn the RTL into a gate-level description•ie. AND, OR gates, etc.•Chip-test features are usually inserted at this point

Gate level design verified for correctnessOutput of synthesis is a “net-list”•i.e. List of logic gates and their implied connectionsNOR2 U36 ( .Y(n107), .A0(n109), .A1(\value[2] ) );

NAND2 U37 ( .Y(n109), .A0(n105), .A1(n103) );

NAND2 U38 ( .Y(n114), .A0(\value[1] ), .A1(\value[0] ) );

NOR2 U39 ( .Y(n115), .A0(\value[3] ), .A1(\value[2] ) );




Physical Design tools used to turn the gate-level design into a set of chip masks (for photolithography) or a configuration file for downloading to an FPGAFloorplanning•Positioning of major functions

Placement•Gates arranged in rows




Clock and buffer Insertion•Distribute clocks to cells and locate buffers for use as amplifiers in long wires

Routing•Logic Cells wired together




Subflow example:Timing Closure:•“Front end” of design process= Design capture, simulation and synthesisAssumes abstract information about impact

of wires• “Back end” of design processPlace and routeRequires accurate wiring models



Future Issues

Increased cost of custom fab•First chip run will cost over $2M for 90 nm•Multiproject wafers

Increased cost of design•Must be addressing > $1B market to justify a new chip run

Globalization•Time-to-market and other competitive issues



Future Issues (cont’d)

Trends•Increased use of FPGA and Gate Arrays•Increased use of ‘platform’ solutionsMulti-core embedded CPU + ASIC acceleratorsConfigurable systemsExisting designs (‘IP’)

•Increased use of SystemVerilog, SystemC and other system modeling tools•Complexity shifting from design to logical and performance verificationLogical verification = function; Performance = speed

•Cost to first silicon getting so high that the total addressable market

must be very large and product risk low



Design Cost



Questions

• What basic technological trend drives the Semiconductor Industry?• What is the key difference between a standard cell ASIC and an FPGA?• What will be important challenges to future design houses?• What is a “fabless semiconductor vendor”?



Summary

Over the next ten years, product growth will be driven by:•Underlying technology push•High demand for graphics, multimedia and wireless connectivity•Insidious insertion of electronics and computers into our everyday lives

Many of the resulting products will require specialized silicon chips to meet performance (speed/size/weight/power/cost) demands – ASICsASIC design methodology includes logic, timing, and physical design•Unfortunately, design productivity is not keeping up with chip performance growth



To match this product need, the capability of a silicon CMOS chip will continue doubling every 2-3 years until after 2015.•To sell a product at $300-$1,000, it can only include one high value chipThus product performance is determined by the performance of that one chip

•AND talk about planned obsolescence!!

ASIC styles include full custom (for analog) and RTL-based design: Cell based (semi-custom), Gate Array or FPGA implementation

Summary (cont’d)

Introduction to ASIC Design

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