Intra-field stress impact on global wafer deformation

Richard van Harena, Ronald Ottena, Subodh Singha, Amandev Singha, Leon van Dijka,

David Owenb, Doug Anbergb, Jeffrey Milehamb, Yajun Gub, Jan Hermansc aASML, Flight Forum 1900 (no. 5846), 5657 EZ Eindhoven, The Netherlands

bVeeco-Ultratech, 3050 Zanker Road, San Jose, CA, USA 95134 cIMEC, Kapeldreef 75, B-30001, Leuven, Belgium

ABSTRACT

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin

film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in

process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for

the next layer exposure, in-plane distortion patterns may be apparent after clamping. The wafer alignment system inside

the scanner is designed to correct for these process-induced in-plane wafer distortion signatures. Depending on the

complexity of the distortion pattern, the choice of wafer alignment model can be adapted to achieve the required overlay

performance. While wafer overlay metrology is used to correct for the systematic part of the wafer distortion, the wafer

alignment functionality addresses the random part that is varying from wafer-to-wafer.

In the case of a homogeneous single film of uniform stress deposited on a substrate at elevated temperatures inside a

deposition tool, the resulting free-form wafer shape at room temperature will take a parabolic form (either bowl or

umbrella). The resulting in-plane distortion can be described by a radial scaling pattern. A linear wafer alignment model

can easily correct for these kinds of distortion patterns and the resulting overlay is close to the scanner baseline

performance. Also, in the case where there is a slight variation in one of the material parameters across the wafer, the

resulting wafer distortion can easily be corrected for by selecting one of the available wafer alignment models. A Higher

Order Wafer Alignment model up to the third order (HOWA3) has been proven to be sufficient to bring the overlay

performance down to the scanner baseline performance over the past years.

In this paper we will consider the impact of local stress variations on the global wafer deformation. One of the sources of

the local stress variation is linked to the intra-field or intra-die pattern density. We will demonstrate that the intra-field

stress distribution not only affects the intra-field overlay performance but has also a significant impact on the global

wafer distortion. The focus will be mainly on use-cases with high intra-field stress variations similar to what is

encountered in 3D-NAND processes. These cases in particular need a more advanced correction approach. However,

since the underlying root cause is generic, the same approach may also be applicable to other use-cases like DRAM and

Logic.

Keywords: Wafer distortion, Wafer shape, Overlay, Deposition, Intra-die, Stress, Wafer alignment

1. INTRODUCTION

During wafer processing, several processing steps are known that may cause wafer deformation [1,2]. For instance, in

the case where a film is deposited at an elevated temperature having a different thermal expansion coefficient than the

substrate, the wafer gets warped after it is brought back to room temperature. If the material parameters and the thickness

of the deposited film are constant across the wafer, the induced free-form wafer deformation can easily be corrected for

inside the scanner before exposure [3]. Most of the time, radial wafer scaling distortion patterns are introduced. A bowl-

shaped wafer results in a negative scaling pattern with distortion vectors pointing towards the center of the wafer, while

for an umbrella type of wafer the distortion vectors pointing away from the wafer center. A linear wafer alignment model

is sufficient to correct for these types of wafer distortions. Alternatively, the free form wafer shape can be monitored as a

*Richard.van.Haren@asml.com; Mobile: +31-6-11786083; fax +31-402685430; www.asml.com

function of processing step by utilizing the wafer scaling parameter from the linear wafer alignment model. In the case

where the film deposition is non-uniform in material parameters and/or film thickness, deviations from a radial wafer

scaling distortion pattern can be expected [4]. This may happen if the deposition temperature is non-uniform inside the

deposition chamber. One can expect that these kinds of non-uniformities will vary slowly across the wafer over multiple

dies and/or fields. ASML has developed higher order wafer alignment (HOWA) models to describe the wafer distortion

with a polynomial function. For instance, HOWA3 refers to a third-order polynomial that has proven to be very

successful in capturing the slowly varying distortion variations across the wafer. Since 10 parameters need to be fitted

per x- and y-direction, a minimum of 10 alignment marks providing (x, y) information is required. If possible, one can of

course always maximize the number of alignment marks for a more robust determination of the 10 parameters without

affecting the throughput of the scanner.

Another source of wafer distortion is linked to the annealing process step [5,6] that is required to activate the dopants

after ion implantation. Three types of annealing processing equipment exist: furnaces, rapid thermal anneal processing

(RTA and RTP), and millisecond annealing (e.g., laser spike annealing). Typically, many wafers are heated-up

simultaneously during furnace processing. The temperature ramp-up and ramp-down time is pre-defined, and the wafers

stay at an elevated temperature for a fixed time on the order of minutes to hours. Although, these anneal types are not

known to cause significant wafer deformation, sometimes local distortions are observed close to the wafer edge at higher

temperatures. These local distortions occur at the locations where the wafer is supported inside the boat and are referred

to as “boat marks”. In extreme conditions, temperatures may be sufficiently high (e.g., 1050°C) that slip lines can occur

in the silicon lattice. A different wafer support type (e.g., long finger boat) can be employed to eliminate these kinds

local wafer distortions.

The RTA or RTP equipment is based on single wafer processing. The wafer is heated up by an array of lamps to the

required temperature for a short period of time on the order of seconds to minutes. This process is sufficient to activate

the dopants and/or change the material properties (e.g., densify, improved conductivity, etc.). Any inhomogeneity in

radiation absorption may result in a global stress variation across the wafer. In Figure 1, we show ASML internal data

based on earlier work we did in collaboration with an IC manufacturer. The goal was to improve the Contact to Gate

overlay performance for a 28-nm technology logic device. The overlay was affected by the RTA processing step which

causes variations in the wafer deformation. This is clearly reflected when considering the linear alignment model

residuals for more than 1100 wafers that were exposed on the XT:1900Gi scanner. So-called dual swirls or butterfly

fingerprints were observed in the alignment model residuals. Figure 1 shows a comparison of the linear residuals (left) to

the HOWA3 residuals (right), and it is immediately clear that the HOWA3 model can effectively suppress the wafer

deformation variations due to the RTA processing step. We therefore consider the HOWA3 residuals the starting point

for further improvements.

Figure 1: Results from a case for which a linear model (or 6-parameter model) was insufficient to capture the wafer

distortions that were introduced by the Rapid Thermal Anneal tools. As can be observed in the right-side of the figure, a

third order polynomial was sufficient to reduce the alignment model residuals to the baseline performance of the scanner

that was used at the time.

Even shorter anneal times (micro-seconds to milli-seconds) can be achieved by laser spike anneal (LSA) tools. The wafer

is heated locally by scanning a laser spot over the wafer surface. To anneal the whole wafer, a laser spot with a long, thin

profile is swept in a serpentine pattern until the whole wafer is covered. In the case of a poorly adjusted or drifting tool, a

linear gradient in the material parameters (e.g., stress) might be introduced. When the stress is varied linearly across the

wafer, a dual swirl is observed in the linear alignment model residuals [4].

All the processing effects described above generally affect the global wafer distortion and the effect of the underlying

device pattern is assumed to be negligible. However, this assumption is only strictly valid in the case that the pattern

density is uniform across the whole wafer. In almost all practical cases, there is a repetitive pattern with varying density

as a direct result of the scanner exposures. Within one field several dies may exist, each with its own layout. Functional

areas within one die may result in different stress contributions directly affecting the local distortion. For 3D-NAND this

is most pronounced, since the individual dies consist of dense memory areas separated by periphery areas and scribe

lines.

In this paper, we will address the impact of local intra-field or die stresses on local displacement and hence overlay. We

will see that the local stresses not only affect the intra-field or intra-die overlay performance, but the global wafer

distortion as well. The impact of local stresses on overlay is expected to be most noticeable for 3D-NAND. However,

since the underlying physics is the same, similar overlay effects of smaller magnitude may be observed in DRAM and

logic devices. One of the goals would be to explore if free-form wafer shape measurements can be utilized to predict the

local distortions accurately.

1.1 The 3D-NAND use case: intra-die stress impact on overlay

In a previous study, we used a Finite Element (FE) based analysis to predict wafer-scale or global in-plane displacements

from measured wafer shape and compared those to in-plane displacements measured by the scanner alignment system

[11]. We are extending that work to investigate local wafer distortions that are caused by intra-field and intra-die stress

variations by modifying our FE approach, which is inspired by layouts encountered during interaction with our

3D-NAND customers. The use of FE model to predict in-plane displacement from shape is common in the literature and

different approaches and geometries have been considered. [e.g., 7]. Prior to demonstrating results on experimental

wafers, a virtual simulation was performed to illustrate the effects of intra-field stress on distortion. Local residual stress

on a bare silicon wafer was introduced by assigning different temperatures to the top surface (1 µm) of the wafer. The

coefficient of thermal expansion assigned to the top film in the x-direction is twice of that in the y-direction. Figure 2

shows an example of such a layout, where we have chosen a (4 × 2) die layout inside one exposure field. The

temperature of the blue rectangles is 1°C lower than the surrounding gray region mimicking the intra-die stress due to the

dense memory areas as opposed to the lower-density periphery.

Figure 2: Simulation layout as is used for the FEM analysis. The blue rectangular boxes represent areas where the

3D-NAND memory is located. Local stress is simulated by assigning a reduced temperature to the blue areas compared to

their surroundings.

Several interesting features are apparent upon closer inspection of the whole-wafer layout (left-side of Figure 2). Away

from the wafer edge, the pattern is very repetitive from field-to-field. This means that one would expect a consistent and

repeating field distortion signature. However, close to the edge of the wafer we may expect many discontinuities in the

stress distribution since the field layout in combination with the wafer edge results in partial dies and/or missing dies. It

may be obvious that the number, size, and layout of the dies within a field plays an important role in the discontinuities

in the stress distribution close to the wafer edge. For example, in the limit that the size of the stressed or blue regions

becomes a larger and larger fraction of the total wafer surface, the distortion will behave similarly to a continuous thin-

film of uniform stress.

Figure 3: Simulated free-form wafer shape change resulting from an imposed intra-field stress distribution. The main shape

change can be described by a paraboloid. After removal of the second order shape, the intra-field effects show up. Note

these intra-field effects are not uniform across the wafer. Global wafer topology changes of 4th order is introduced as well.

In Figure 3, we show the free-form or unclamped wafer shape change that results from the simulation input as described

above. At first glance, the wafer takes a parabolic shape (~100 µm in x and ~50 µm in y) as shown on the left-hand side

of the figure. The fine structure in the shape is revealed when a second order shape is fitted and removed from the free-

form wafer shape. The residual topology is in the order of hundreds of nanometers. In the 2nd order fitted residual

topology map on the right, both a 4th order global wafer shape and the field topology introduced by the (4 × 2) die layout

remain. It is interesting to see that higher order global topology effects are introduced by the application of intra-die

stresses. This implies that regularly distributed local stresses result in an effective average stress of an equivalent

continuous, uniform thin film. In the example of Figure 3, the curvature and hence stress parallel to the x-axis is higher

compared to that along the y-axis. These details are dependent on the exact field layout and applied stress; however, the

observations of a global 2nd order shape and edge non-uniformity in the residual shape are consistent.

The topology considerations described above imply that when these wafers are clamped on the chuck before exposure

and the free-form shape is removed, the majority of the wafer distortion of the clamped wafer can be described by an

asymmetric linear scaling. However, since the free-form wafer shape cannot be fully described by a second order

surface, higher-order wafer distortions are expected as well. Figure 4 shows the simulated displacements after correcting

for the linear wafer terms. The left-hand side shows the total distortion, which is separated into a large intra-field

displacement signature (center) and strong local distortion patterns close to the wafer edge (right).

Figure 4: On the left-hand side, the wafer distortion due to an imposed intra-field stress distribution is shown after correcting

for the linear terms (up to the first order). Apart from a strong intra-field distortion signature (center), higher order local

distortions at the wafer edge are introduced as well (right).

It is immediately clear from Figure 4 that the higher order local wafer distortions close to the wafer edge cannot easily be

captured by simply adding more wafer alignment marks. These very local distortions vary significantly from field-to-

field and die-to-die. In contrast, a continuous, smoothly-varying distortion behavior would be preferred since such

distortions can be corrected using a higher-order polynomial model such as HOWA3.

Similarly, the field distortion plot in the center of Figure 4 suggests that the intra-die distortion cannot be characterized at

all by simply adding more wafer alignment marks per field. Alignment marks can only be placed in the inner scribe line

areas and not in the memory areas. However, it is clear from the field distortion plot that the die-induced distortion is

generally absent in the scribe line areas. As a result, alignment marks placed in the scribe lines are insufficient to

characterize the within-die distortion pattern. The same arguments apply to the characterization of overlay, where scribe-

line overlay targets will be blind to any within-die overlay errors. Consequently, an in-die measurement technique is

required to characterize the local distortion pattern.

In the case where the intra-die stress induced distortion fingerprint is very stable from wafer-to-wafer and lot-to-lot, an

overlay feed-back solution might be sufficient. This is only possible if intra-die (device) overlay measurements are

available [8]. On the other hand, if the intra-die stress variations are too high and vary from wafer-to-wafer and lot-to-lot,

a feed-forward solution is required. An exploration of alternative methods enabling dense wafer intra- and inter-field

distortion prediction is required.

1.2 Free-form wafer shape measurements to enable in-plane intra- and inter-die wafer distortion corrections

An alternate approach to predict the process-induced in-plane displacement (IPD) is to use free-form wafer shape

measurements [3,9,10]. In this case, an accurate measurement the free-form shape of the unclamped wafer is used as the

input to a model to estimate the in-plane wafer distortion after clamping, assuming the clamping is frictionless. The

determination of in-plane distortions based on free form wafer shape measurements has several attractive characteristics

and potential advantages that we would like to highlight as follows:

• Shape-based IPD predictions minimize the need for a large number of alignment marks to capture the process

induced die and wafer distortion. The in-plane wafer distortion can be determined on any arbitrary location on

the wafer, in both active and inactive regions of the die. The IPD can be determined on > 3,000,000 points on

the wafer within a few seconds, thus enabling intra-die as well as inter-die process-induced distortion

corrections. It should be recognized that alignment marks are still required to anchor the IPD map and/or correct

for litho-induced displacements.

• Free-form wafer shape measurements can be performed on any layer stack whether the films are opaque or not.

High resolution shape changes can be captured and can be transformed into high resolution IPD maps using an

appropriate model. Since the scanner correction capability is continually improving with additional correction

parameters becoming available over time, a high resolution IPD input map could be included as one of the

inputs for the determination of corrections.

• Predictions of IPD based on wafer shape does not require device and process-specific optimization. With

traditional alignment and overlay measurements, the quality of the mark has a large impact on measurement

reliability. Each mark must be optimized for a given device and the design must consider a wide variety of

factors such as pattern density, illumination conditions, optical aberrations, and robustness during subsequent

processing.

A few attempts have been made to link free-form wafer shape measurements to in-plane wafer distortions [1-3,9,10]

based on layouts and stress distributions that were much simpler than the case described in section 1.1. The mathematical

prediction model describing the relationship between the free-form wafer shape and the in-plane deformation is key. In

addition, an on-wafer validation is needed to assess whether the prediction model is sufficiently accurate. In those

previous studies, plots of predicted versus measured residuals have been made after application of a linear model and

show good correlation for the simpler geometries, but the distortion ranges were always relatively large (in the range of

±20 nm).

However, the use of linear residuals and large distortion ranges are not particularly relevant to current on-product overlay

challenges. For example, we know that the scanner can easily correct for distortions that can be described by a third

order polynomial (HOWA3). Therefore, in practice the application of IPD from shape would have the biggest impact in

the characterization of higher order distortion patterns (i.e., > 3rd order), since low-order patterns can be corrected with

existing techniques. One of the goals of our work is to evaluate what limitations, if any, there are on the correlation

between measured distortion and distortion predicted from shape for small displacement magnitudes. Our previous study

demonstrated excellent correlation between the wafer-shape based IPD prediction and the measured distortion when the

distortion range is ±3 nm [11]. The accuracy was better than 1 nm and was limited by the baseline performance of the

scanner used. Since these results were so promising, we decided to continue the investigation for the effect of intra-field

stress on distortion, which cannot be captured by a third order model.

2. EXPERIMENTAL DETAILS

2.1 The Superfast 4G Turbo free-form wafer shape measurement tool

The wafer shape measurement tool we used for all the experiments in this paper is the Veeco-Ultratech Superfast™ 4G

Turbo as shown in Figure 5.

Figure 5: The Veeco-Ultratech Superfast 4G Turbo tool used for the wafer warp measurements. The unique self-referencing

interferometry technique enables accurate wafer shape measurements and as result sub-nm wafer distortion predictions.

The wafer shape measurement principle is based on a unique self-referencing CGS (Coherent Gradient Sensing)

interferometry technique [12]. This enables an accurate shape measurement and monitoring [13] for any type of

patterned surface. The self-referencing refers to the interference of light reflected from two adjacent points on the wafer

surface to provide a robust front-side wafer shape measurement since the stack contribution is common to both points

and effectively cancels out when interfered. As a result, the technique can be used to measure the wafer shape for both

transparent and non-transparent (opaque) film stacks. This capability is crucial for an accurate wafer shape measurement

but not always available with other interferometer systems [14] that use independent reference surfaces such as flat

mirrors. The measurement robustness for different film types is important because thin film deposition is not restricted to

the front or device side of the wafer. Back-side wafer processing may be intentional in the case of stressed films used to

compensate for wafer warpage or unintentional as a consequence of a specific deposition technique or thermal process.

Another intrinsic advantage of the self-referencing interferometry technique is its reduced sensitivity to vibrations as

adjacent measurements points experience the same vibration. These requirements are essential to obtain an accurate free-

form wafer shape measurement and facilitate accurate predictions of the in-plane wafer distortions within the nanometer

regime.

The throughput of the Superfast 4G Turbo is high (175 WPH) and not limited by the data acquisition, so further

improvements to throughput are possible. Dense measurements can be done at a selectable resolution of either 300 µm or

150 µm covering the full 300 mm wafer with an edge exclusion of only 1 mm. When the extended bow option is

enabled, wafer warp levels up to ± 1 mm can be measured, while still maintaining full throughput.

An accurate wafer shape measurement alone is not sufficient. Appropriate models are required to use wafer shape to

predict the in-plane wafer distortion after clamping on a scanner chuck. Simple analytical models as well as methods

based on Finite Element Modeling (FEM) have been proposed and evaluated [4,7]. The exact details of the model

implementation are crucial to successfully predict the in-plane distortion. The validation of the prediction model is one of

the primary challenges, and typically, on-product overlay measurements have been used as the reference for comparison

to IPD predictions from shape. However, we know that the on-product overlay is the sum of individual components of

which wafer distortion is only one of several. The model prediction accuracy can only be validated if the contribution

from wafer distortion can be isolated from the other overlay components. We developed a measurement approach to

isolate the wafer distortion contribution as discussed in the next section.

2.2 Scanner measurements to isolate the process induced wafer distortion contribution

We made use of the so-called BMMO (Baseliner Matched Machine Overlay) reference wafer creation reticle to fabricate

the wafers required to quantify the process-induced wafer distortion contribution. This reticle contains metrology

modules in a 13×19 layout, including a wafer alignment mark (XPA). The position of the XPA can be read by the

scanner alignment sensor (SMASH) within the scanner measurement grid. Test wafers are created by exposing the full

wafer (single chuck) with the BMMO reticle followed by a photo resist development and a silicon etch step. All the

metrology modules are shallowly etched (~80 nm deep) into the silicon substrate to minimize the etch-induced penalties.

The alignment marks can be read out after the photo resist development step and after the etch step; therefore, we also

verified that the etch did not introduce an additional fingerprint by comparing the two wafer fingerprints. Using the four

colors of the alignment system, we evaluated the color-to-color difference both after photo resist and after-etch, and

found the deltas were identical in each case (< 0.4 nm).

Figure 6 illustrates the approach for isolating the process-induced distortion. For this study, twenty-three wafers were

fabricated. Twenty wafers were used as the test wafers and three wafers were not processed further and used as reference

wafers to characterize and correct for any unexpected drift of the metrology systems. All twenty-three wafers were

exposed at the same time on the scanner in single chuck operation mode. The scanner exposure wafer fingerprint is

captured by the wafers inside the lot. All wafers were etched after the photo resist had been developed and the exposure

fingerprints embedded into each wafer. Scanner measurements were done on both the NXT:1950Ai and the NXT:1970Ci

to investigate the wafer table contribution as well. All wafers were read out on both scanners and measured on the

Superfast system to determine the free-form shape. The combination of the scanner readout and free-from shape define

the pre-processing state of the wafers.

The test wafers received additional processing to create different bow levels and patterned structures. After the additional

processing steps, the scanner readout and shape measurement were repeated to define the post-processing state of the

wafers. The process-induced wafer deformation was isolated by computing the difference between the post-processing

and pre-processing wafer distortion maps and shape. In this manner, the scanner exposure fingerprint is eliminated,

thereby enabling us to determine the process-induced wafer deformation below the scanner baseline performance.

Similarly, the difference in the pre- and post-process shape eliminates systematic offsets associated with that

measurement.

Figure 6: Measurement scheme to isolate the process induced wafer deformation. All exposed and etched wafers are read

out by the scanner prior to the process steps under investigation. After the processing steps, the wafers are read out again. If

the delta wafer distortion map is considered, the process induced wafer distortion fingerprint can be isolated.

2.3 Process induced wafer deformation

The processing splits were defined in a manner consistent with our previous study [11]. Free-form wafer shapes of

varying bow were generated by depositing silicon nitride films of varying thickness under different deposition conditions

to create bowl-shaped (tensile stress) or umbrella-shaped (compressive stress). Four groups of wafers were created:

• Homogeneous, continuous films: Wafers that are covered with a uniform homogeneous film of silicon nitride

out to the wafer edge. Two wafers were created with bow levels of +80 µm, +40 µm, -40 µm, and -80 µm (eight

total).

• Partial edge field removed: For this group of wafers, all the partial fields close to the wafer edge were cleared

from the silicon nitride film using an additional exposure and wet etch step. For these splits, wafers having

initial bow levels of +40 µm, -40 µm, and -80 µm were used; two for each bow level and six in total.

• Partial field wafers: For the third group, an intra-field stress pattern was created by removing the silicon nitride

from half of the field using an additional exposure and wet etch. For these splits, wafers having initial bow

levels of +40 µm, -40 µm, and -80 µm were used; two for each bow level and six in total.

• Reference wafers: These wafers had no further processing after the formation of the initial metrology modules.

The results obtained for first two groups of wafers were discussed in detail in a previous publication [11]. We are not

going the repeat these results here but focus our attention on the third group of wafers. Figure 7 shows the layout of the

partial field or group three wafers.

Figure 7: The process splits investigated in this paper. First, bowl and umbrella shaped wafers were created by depositing

silicon nitride under different conditions and thicknesses on the front-side of the wafer. The initial warp levels were +40 µm

(bowl), -40 µm, and -80 µm (umbrella), respectively. The silicon nitride is removed from half of the field after an additional

litho and etch step. The resulting wafer layout is shown on the right-hand side.

The partial field wafers are intended to provide a model layout that can be used to study the local stress impact on the

intra- and inter-field overlay performance. These wafers mimic production wafers where local stresses may be different

in different regions within the exposure field or die. For example, different functional areas within the die may have

varying pattern density and materials that result in stress variations, which is applicable to both memory and logic

devices. From the wafer layout on the right-hand side of Figure 7, one would already expect to see a distinct field

distortion signature associated with the periodicity of the layout. However, close to the wafer edge, the periodicity is

interrupted, and partial fields and dies are created. This results in stress and distortion variations on an intra-die length

scale that would be extremely challenging to capture with wafer alignment marks. However, distortion predictions based

on free-form wafer shape measurements nominally do not have such limitations and therefore, it is of interest to evaluate

the accuracy of such predictions.

3. RESULTS

3.1 Intra-field stress induced wafer shape change

The free-form wafer shape changes for the intra-field stress process splits are shown in Figure 8. The pre-processing

wafer shape was measured before the silicon nitride deposition and the post-processing wafer shape was measured after

deposition and the partial field etch. Removal of half of the field resulted in a reduction in bow by a factor of 2: before

etching the bows were approximately +40 µm, -40 µm, and -80 µm, whereas after etching the bows changed to +20 µm,

-20 µm, and -40 µm respectively. Note that the free-form wafer shape change remains a paraboloid even though half of

the silicon nitride has been removed. For this use-case, there is no noticeable asymmetry in the shape change when

comparing the x- and y-direction. This can be understood by the fact that the average contraction (or expansion) of the

top wafer surface per field is the same in the x- or y-direction. This implies that the main contributor of the wafer

deformation can be described by a symmetric (in this case) wafer scaling term.

Figure 8: Free-form wafer shape change due to intra-field stress. Three different process splits with tensile and compressive

stress were defined resulting in one bowl and two umbrella (of different magnitude) shaped wafers.

The free-form wafer shape changes after removal of the second order free-form shape are shown in Figure 9. Inspection

of Figure 9 results in a couple of interesting observations. First, the intra-field stress pattern is clearly observed in the

free-form wafer shape change as vertical stripes. The local shape change is approximately 2.5% of the global free-form

wafer shape change. However, besides the periodic pattern of the wafers stripes; other higher order wafer deformations

(≥ 3rd order) are present. That is, we do not observe a uniform stripe pattern across the whole wafer in the free-form

wafer shape change after removal of the second order free-form shape. To be more specific, the width of stripe is not

constant across the wafer and the topology is locally lower or higher at the 3 o’clock and 9 o’clock positions

respectively.

Figure 9: Free-form wafer shape change due to intra-field stress. Three different process splits were defined resulting in one

bowl and two umbrella shaped wafers.

This residual shape pattern seems to be a direct result from the interaction of the stripe geometry (or intra-field stress)

and the wafer edge, as was shown in Figure 7. The length of the silicon nitride stripes gets shorter near the wafer x-

coordinates at -150 mm and +150 mm. In addition, the local wafer shape at both ends of the stripe will change as well,

from a rectangular shape near x = 0 mm towards a sharp triangular shape near x = -150 mm and x = +150 mm. In the

region around x = -150 mm, even the width of the partial stripe is reduced. A more symmetric distortion signature could

have been created by applying a layer shift. However, in practice this may result in less yielding dies at the wafer edge.

The wafer shape modulation close to the wafer edge will result in local in-plane distortions on a die length scale. Since

the stripes are not perfectly parallel to the y-axis, local wafer distortions in both the x- the y-direction are expected. For

stress related overlay penalties close to the wafer edge, a strong correlation with the field and die layout is expected. This

can already be concluded by comparing the intra-field stress induced shape changes in Figure 3 and Figure 9. The

relation between the intra-field stress induced free-form wafer shape and the in-plane wafer distortion will be quantified

in the next section using scanner measurements.

3.2 Measured wafer distortions

Figure 10 shows the process-induced distortion maps from the scanner alignment readout after HOWA3 correction. The

two features that are immediately clear are the field distortion signature and the higher-amplitude local grid distortions

close to the wafer edge at the 3 o’clock and 9 o’clock positions. The intra-field stress-induced distortion penalties are

quite significant, even for moderate wafer bow changes of +20 µm, -20 µm, and -40 µm respectively. Note that the

displacements in the x-direction are typically ~1.5 times larger than the y-direction.

Figure 10: Measured wafer distortion for the three different process splits. The distortion pattern correlates with the warp

level (both in direction and magnitude). The intra-field stress signature is clearly visible in the full wafer distortion maps.

The distortion signatures near the wafer edge become much clearer if the intra-field distortion contribution is separated

from the global wafer distortion as shown in Figure 11. Comparing the statistics of the intra-field distortion (bottom row

of Figure 11) to the global wafer distortion (top row of Figure 11), it is clear the wafer distortion is dominated by the

field signature. At the locations where silicon nitride is present, either a contraction or expansion is visible depending on

whether the wafer is bowl or umbrella shaped, respectively. Consequently, the application of a static intra-field overlay

correction would be sufficient to remove most of the wafer distortion, leaving < 1.5 nm of displacement in the wafer

center.

However, near the wafer edge, a highly localized wafer distortion remains with the distortion vectors showing an

alternating pattern. The displacement vectors point inward and outward in a manner consistent with the residual of the

free-form wafer shape shown in Figure 9. Furthermore, in the regions near x = -150 mm and x = +150 mm the residual

maps show a significant distortion extending several millimeters from the edge, particularly for the +40 µm umbrella

split on the right of Figure 11.

Figure 11: Measured wafer distortion for the three different process splits. The distortion pattern is decomposed in an

average field contribution (bottom row) and a wafer contribution (top row). The local distortions at the wafer edge are

clearly visible.

3.3 Comparison between the measured and free-form wafer-shape based distortion prediction

In this section we would like to compare the free-form wafer-shape based distortion prediction with the on-wafer

measured distortion as shown in section 3.2.

Figure 12: Free-form wafer-shape based predictions of wafer distortion for the three different process splits. Both the field

and wafer distortion signatures visible in the measured results can be reproduced with the predicted results.

Figure 12 shows the predictions of a Finite Element based model that requires the free-form wafer shape measurements

as the input. Also, in this case HOWA3 corrections were applied to the modeled displacements to provide a direct

comparison with the measurements shown in Figure 11.

When comparing the free-form wafer-shape based distortion predictions with the measured distortions in Figure 11, we

observe a striking similarity. Both the intra-field and global wafer distortion signatures are predicted very well by the

free-form wafer shape to IPD prediction model that was developed. Even the localized distortions close to the wafer edge

are reproduced by the prediction model. It should be emphasized that the wafer distortions we are considering are on the

order of 2 nm.

The wafer-shape based IPD prediction and the measured distortion can be compared directly by subtracting the point-to-

point values as shown in Figure 13. The residuals are ~1.0 nm for the ±20 µm bow splits and around 1.5 nm for the

-40 µm bow split. These values are below the baseline overlay performance of the best performing scanner that was used

in the experiments (the NXT:1970Ci with ≤ 2 nm single machine overlay, dedicated chuck, full wafer coverage). Since

the minimum delta between the measured and the prediction is 1 nm for the ±20 µm bow splits, the accuracy of the free-

form wafer-shape based IPD prediction model is 1 nm or better. This means that free-form wafer shape measurements

are accurate and viable for correcting process-induced distortions.

Figure 13: Delta wafer maps between the measured and the predicted wafer distortions. The prediction accuracy is less than

1 nm and limited by the baseline performance of this experiment which is below the scanner baseline performance already.

4. DISCUSSION

The intra-field stress use-case that is discussed in the paper is generic in the sense that it is not related to a specific

product or device. If an intra-field distortion signature due to local stress is present, it will give rise to localized higher

order wafer distortions at the wafer edge as we have seen in both the simulations and experimental data. The layout of

the chip and/or the die plays an important role as well. The easiest way to eliminate these local wafer distortions would

be to reduce the stress variations within the die and/or field as much as possible by tighter process control and/or placing

dummy pattern features. However, this might be difficult to achieve in practice.

It is interesting to note that these kinds of higher order wafer distortions cannot be eliminated by applying a wafer back-

side stressed film. These back-side films are sometimes applied to compensate for high warp effects. Although the

magnitude of the second order free-form wafer shape may be reduced or eliminated by a uniform wafer back-side

coating, the higher order global wafer deformations due to a non-uniform intra-field stress distribution will remain.

The intra-field stress induced global wafer distortions are not restricted to 3D-NAND where high wafer warp levels

(above 100 µm, and even up to 1 mm) are typical. Note that the average intra-field stress levels we considered in this

paper are relatively small. They result in free-form wafer shape changes of only 20 µm to 40 µm, however, it is clear that

the stress non-uniformity is more important than the average stress in the generation of the higher order wafer distortions

close to the wafer edge.

The prediction model we developed to convert the free-form wafer shape measurements into an in-plane distortion

currently assumes a frictionless wafer clamping until the wafer edge at 150 mm. Since we observe a good match between

the predicted and measured wafer distortion already, we conclude that the clamping contribution in this experiment is

negligible. This has been confirmed scanner readouts on both the NXT:1950Ai and NXT:1970Ci. The prediction model

used is still in development and not ready for industrialization. However, the model in its current form is perfectly

suitable to judge the possibility of using free-form wafer shape measurements for an accurate prediction of the in-plane

wafer distortion. Promising results were already published before [11] and the current extension towards intra-field stress

is in line with those results.

An accurate in-plane wafer distortion prediction model based on free-form wafer shape measurements is very powerful

since it can predict the wafer distortion before the wafer is exposed. This wafer-based distortion prediction can be

utilized to enable wafer-level control by sending feed-forward corrections to the scanner. This is an attractive possibility

especially in cases for which the wafer-to-wafer or lot-to-lot process-induced distortion variation is high.

An extension of the current correction approach based on higher-order polynomial fitting (e.g., a polynomial of the 5th

order and higher) may not be sufficient for such localized deformation. This is illustrated in Figure 14, where we show

the decrease in the measured wafer distortion residuals as function of a polynomial fit. We see that even a polynomial of

the 10th order is not sufficient to reduce significantly the localized wafer distortions close to the wafer edge. As can be

seen in the figure, the free-form based distortion prediction on the far right provides a much better description of the

localized distortions close to the wafer edge.

Figure 14: Measured wafer distortion residuals after polynomial modelling. Even a 10th order polynomial fit is not sufficient

to reduce the residuals at the wafer edge significantly. A free-form wafer-shape based prediction shows a significant

improvement at the wafer edge compared to the polynomial fits. The statistics are left out since they are determined by

large number of points for the inner part of the wafer and do not represent what is happening at the wafer edge.

In addition to an accurate prediction of process-induced distortion, a corresponding correction capability is required on

the scanner as well. To this end, ASML has developed the so-called Overlay Optimizer (OVO) products. With the most

recent release of this product, the scanner correction capability is increased to 38 parameters per exposure field. In Figure

15, we illustrate the correction capability on the global wafer deformation after average field removal. The average field

distortion itself might be addressed by a combination of scanner and mask corrections [15,16]. On the left-hand side, the

measured in-plane distortion map for the umbrella shaped wafer (-40 µm) is shown (see also Figure 11). The wafer plot

in the center shows the OVO correction map that is based on the modeled in-plane distortions from free-form wafer

shape. The wafer plot on the right-hand side of Figure 15 shows the residuals after applying the correction map in the

center on the measured wafer distortions. The localized higher order wafer deformations at the wafer edge can be

strongly suppressed.

Figure 15: On the left-hand side, the measured global wafer distortion is shown. In the center, the OVO correction map

based on free-form wafer-shape based distortion predictions. On the right-hand side, the residual map.

5. CONCLUSIONS

In conclusion, we have shown that the presence of intra-field (or intra-die) stress distributions not only results in an

average intra-field or intra-die deformation but also causes a global wafer distortion. These global wafer distortions are

very pronounced close to the wafer edge and cannot easily be corrected by means of a polynomial fit. The wafer

distortions are not restricted to the edge-fields only, as the exposure fields further away from the wafer edge also

exhibited significant distortion. This first conclusion is based on both simulated and experimental data.

We further investigated if an accurate prediction of the in-plane wafer deformation after clamping could be derived that

is based on free-form wafer shape measurements. For this purpose, a Finite Element based prediction model has been

developed that takes free-form wafer shape measurements from the Veeco-Ultratech Superfast 4G Turbo inspection tool

as input. The model has been validated with on-wafer distortion measurements in a very controlled experiment in which

the wafer deformation can be isolated and determined directly by using the scanner alignment sensor. The obtained wafer

deformation is very clean and independent of contributions from other sources. This is in contrast to overlay

measurements which include contributions from several sources including, but not limited to, process-induced distortion.

This experimental technique enabled us to determine the model prediction accuracy better than 1 nm, which is below the

overlay performance specification of the scanner that was used (≤ 2 nm) and exceeds the performance of models

previously reported in the literature.

We evaluated the intra-field stress use-case and conclude that free form wafer shape measurements can be used to predict

the in-plane wafer distortion within 1 nm accuracy. Even for the small intra-field stress distributions that resulted in free-

form wafer shape changes of only 20 µm, the prediction capability was demonstrated. This opens the door to a broader

application space to device technologies beyond 3D-NAND such as DRAM and logic where lower intra-die stress

variations are known to be present.

6. ACKNOWLEDGEMENTS

The authors of the paper would like to acknowledge David Laidler from imec for performing the exposures and reading

out the wafers on the scanner, Harold Dekkers and Sven van Elshocht from imec for depositing the silicon nitride films

and Frans Spiering from ASML for helping with the OVO optimization.

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