verilog interview questions and answersHi all,Here is a nice collection of Interview questions with reponses:

CMOS interview questions.1/ What is latch up?

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS) 

2)Why is NAND gate preferred over NOR gate for fabrication?NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate.Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance p mos's are in series connection which again increases the resistance).

3)What is Noise Margin? Explain the procedure to determine Noise MarginThe minimum amount of noise that can be allowed on the input stage for which the output will not be effected.

4)Explain sizing of the inverter?In order to drive the desired load capacitance we have to increase the size (width) of the inverters to get an optimized performance.

5) How do you size NMOS and PMOS transistors to increase the threshold voltage?

6) What is Noise Margin? Explain the procedure to determine Noise Margin?The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.

7) What happens to delay if you increase load capacitance?delay increases.

8)What happens to delay if we include a resistance at the output of a CMOS circuit?Increases. (RC delay)

9)What are the limitations in increasing the power supply to reduce delay?The delay can be reduced by increasing the power supply but if we do so the heating effect comes because of excessive power, to compensate this we have to increase the die size which is not practical.

10)How does Resistance of the metal lines vary with increasing thickness and increasing length?

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R = ( *l) / A.11)For CMOS logic, give the various techniques you know to minimize power consumption?Power dissipation=CV2f ,from this minimize the load capacitance, dc voltage and the operating frequency.

12) What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?In the serially connected NMOS logic the input capacitance of each gate shares the charge with the load capacitance by which the logical levels drastically mismatched than that of the desired once. To eliminate this load capacitance must be very high compared to the input capacitance of the gates (approximately 10 times).

13)Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?Because it can not drive the output load straight away, so we gradually increase the size to get an optimized performance.

14)What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance conducting path between VDD and VSS with Disastrous results.

15) Give the expression for CMOS switching power dissipation?CV2

16) What is Body Effect?In general multiple MOS devices are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However while connecting the devices serially this may result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1.

17) Why is the substrate in NMOS connected to Ground and in PMOS to VDD?we try to reverse bias not the channel and the substrate but we try to maintain the drain,source junctions reverse biased with respect to the substrate so that we dont loose our current into the substrate.

18) What is the fundamental difference between a MOSFET and BJT ?In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device.

19)Which transistor has higher gain. BJT or MOS and why?BJT has higher gain because it has higher transconductance.This is because the current in BJT is exponentially dependent on input where as in MOSFET it is square law.

20)Why do we gradually increase the size of inverters in buffer design when trying to drive a high

capacitive load? Why not give the output of a circuit to one large inverter?We cannot use a big inverter to drive a large output capacitance because, who will drive the big inverter? The signal that has to drive the output cap will now see a larger gate capacitance of the BIG inverter.So this results in slow raise or fall times .A unit inverter can drive approximately an inverter thats 4 times bigger in size. So say we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a same ratio of output to input cap. This is the prime reason behind going for progressive sizing.

21)In CMOS technology, in digital design, why do we design the size of pmos to be higher than the nmos.What determines the size of pmos wrt nmos. Though this is a simple question try to list all the reasons possible?In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos helps in pulling down the output to ground ann PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for the output node.

22)Why PMOS and NMOS are sized equally in a Transmission Gates?In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's the reason why we need not size them like in CMOS. In CMOS design we have NMOS and PMOS competing which is the reason we try to size them proportional to their mobility.

23)All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged with one another in an inverter?I have seen similar Qs in some of the discussions. If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1 O/P will be degraded 1 Similarly degraded 0;

24)A good question on Layouts. Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?a)In digital design, decide the height of standard cells you want to layout.It depends upon how big your transistors will be.Have reasonable width for VDD and GND metal paths.Maintaining uniform Height for all the cell is very important since this will help you use place route tool easily and also incase you want to do manual connection of all the blocks it saves on lot of area.b)Use one metal in one direction only, This does not apply for metal 1. Say you are using metal 2 to do horizontal connections, then use metal 3 for vertical connections, metal4 for horizontal, metal 5 vertical etc...c)Place as many substrate contact as possible in the empty spaces of the layout.d)Do not use poly over long distances as it has huge resistances unless you have no other choice.e)Use fingered transistors as and when you feel necessary.f)Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.

25)What is metastability? When/why it will occur?Different ways to avoid this?

Metastable state: A un-known state in between the two logical known states.This will happen if the O/P cap is not allowed to charge/discharge fully to the required logical levels.

One of the cases is: If there is a setup time violation, metastability will occur,To avoid this, a series of FFs is used (normally 2 or 3) which will remove the intermediate states.

26)Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?The late coming signals are to be placed closer to the output node ie A should go to the nmos that is closer to the output.

Digital design interview questions & answers.

1) Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this?Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability

2) What is skew, what are problems associated with it and how to minimize it?In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times. Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point.Clock skew can be minimized by proper routing of clock signal (clock distribution tree) or putting variable delay buffer so that all clock inputs arrive at the same time

3) What is slack?'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must happen'.. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'.When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from when something 'actually happens' (call this Tact) until the deadline (call this Tdead).Slack = Tdead - Tact.Negative slack implies that the 'actually happen' time is later than the 'deadline' time...in other words it's too late and a timing violation....you have a timing problem that needs some attention.

4) What is glitch? What causes it (explain with waveform)? How to overcome it?

The following figure shows a synchronous alternative to the gated clock using a data path. The flip-flop is clocked at every clock cycle and the data path is controlled by an enable. When the enable is Low, the multiplexer feeds the output of the register back on itself. When the enable is High, new data is fed to the flip-flop and the register changes its state

5) Given only two xor gates one must function as buffer and another as inverter?

Tie one of xor gates input to 1 it will act as inverter.Tie one of xor gates input to 0 it will act as buffer.

6) What is difference between latch and flipflop?

The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only when there is a rising/falling edge of the clock.

7) Build a 4:1 mux using only 2:1 mux?

Difference between heap and stack?

The Stack is more or less responsible for keeping track of what's executing in our code (or what's been "called"). The Heap is more or less responsible for keeping track of our objects (our data, well... most of it - we'll get to that later.).Think of the Stack as a series of boxes stacked one on top of the next. We keep track of what's going on in our application by stacking another box on top every time we call a method (called a Frame). We can only use what's in the top box on the stack. When we're done with the top box (the method is done executing) we throw it away and proceed to use the stuff in the previous box on the top of the stack. The Heap is similar except that its purpose is to hold information (not keep track of execution most of the time) so anything in our Heap can be accessed at any time. With the Heap,

there are no constraints as to what can be accessed like in the stack. The Heap is like the heap of clean laundry on our bed that we have not taken the time to put away yet - we can grab what we need quickly. The Stack is like the stack of shoe boxes in the closet where we have to take off the top one to get to the one underneath it.

9) Difference between mealy and moore state machine?

A) Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model. A state machine which uses only Input Actions, so that the output depends on the state and also on inputs, is called a Mealy model. The models selected will influence a design but there are no general indications as to which model is better. Choice of a model depends on the application, execution means (for instance, hardware systems are usually best realized as Moore models) and personal preferences of a designer or programmerB) Mealy machine has outputs that depend on the state and input (thus, the FSM has the output written on edges)Moore machine has outputs that depend on state only (thus, the FSM has the output written in the state itself.Adv and DisadvIn Mealy as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level.All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as a Mealy state machine, although the converse is not true.Moore machine: the outputs are properties of states themselves... which means that you get the output after the machine reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output.The outputs are held until you go to some other state Mealy machine:Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.

10) Difference between onehot and binary encoding?Common classifications used to describe the state encoding of an FSM are Binary (or highly encoded) and One hot.A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM.A onehot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or "hot" state) is set at a time in a one hot FSM design. For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a onehot FSM requires a flip-flop for each state in the designFPGA vendors frequently recommend using a onehot state encoding style because flip-flops are plentiful in an FPGA and the combinational logic required to implement a onehot FSM design is typically smaller than most binary encoding styles. Since FPGA performance is typically related to the combinational logic size of the FPGA design, onehot FSMs typically run faster than a binary encoded FSM with larger combinational logic blocks11) What are different ways to synchronize between two clock domains?12) How to calculate maximum operating frequency?

13) How to find out longest path?You can find answer to this in timing.ppt of presentations section on this site14) Draw the state diagram to output a "1" for one cycle if the sequence "0110" shows up (the leading 0s cannot be used in more than one sequence)?

15)How to achieve 180 deree exact phase shift?Never tell using invertera) dcm's an inbuilt resource in most of fpga can be configured to get 180 degree phase shift.b) Bufgds that is differential signaling buffers which are also inbuilt resource of most of FPGA can be used.16) What is significance of ras and cas in SDRAM?SDRAM receives its address command in two address words.It uses a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the row address strobe (RAS).Following the RAS command is the column address strobe (CAS) for latching the second address word.Shortly after the RAS and CAS strobes, the stored data is valid for reading.17) Tell some of applications of buffer?a)They are used to introduce small delaysb)They are used to eliminate cross talk caused due to inter electrode capacitance due to close routing.c)They are used to support high fanout,eg:bufg18) Implement an AND gate using mux?This is the basic question that many interviewers ask. for and gate, give one input as select line,incase if u r giving b as select line, connect one input to logic '0' and other input to a.19) What will happen if contents of register are shifter left, right?It is well known that in left shift all bits will be shifted left and LSB will be appended with 0 and in right shift all bits will be shifted right and MSB will be appended with 0 this is a straightforward answerWhat is expected is in a left shift value gets Multiplied by 2 eg:consider 0000_1110=14 a left shift will make it 0001_110=28, it the same fashion right shift will Divide the value by 2.20)Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflow or overflow?RULES:1) frequency(clk_A) = frequency(clk_B) / 42) period(en_B) = period(clk_A) * 1003) duty_cycle(en_B) = 25%Assume clk_B = 100MHz (10ns)From (1), clk_A = 25MHz (40ns)From (2), period(en_B) = 40ns * 400 = 4000ns, but we only output for1000ns,due to (3), so 3000ns of the enable we are doing no output work. Therefore, FIFO size = 3000ns/40ns = 75 entries

21) Design a four-input NAND gate using only two-input NAND gates.A:Basically, you can tie the inputs of a NAND gate together to get an inverter, so...

22)Difference between Synchronous and Asynchronous reset.?Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.

The clock works as a filter for small reset glitches; however, if these glitches occur near the active clock edge, the Flip-flop could go metastable. In some designs, the reset must be generated by a set of internal conditions. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clock.Disadvantages of synchronous reset:Problem with synchronous resets is that the synthesis tool cannot easily distinguish the reset signal from any other data signal.Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock[ if you have a gated clock to save power, the clock may be disabled coincident with the assertion of reset. Only an asynchronous reset will work in this situation, as the reset might be removed prior to the resumption of the clock.Designs that are pushing the limit for data path timing, can not afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets.Asynchronous reset :The biggest problem with asynchronous resets is the reset release, also called reset removal. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path. Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.Disadvantages of asynchronous reset: ensure that the release of the reset can occur within one clock period. if the release of the reset occurred on or near a clock edge such that the flip-flops went metastable.

23) Why are most interrupts active low?This answers why most signals are active lowIf you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively. when it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. hence people prefer using active low signals.

24)Give two ways of converting a two input NAND gate to an inverter?

(a) short the 2 inputs of the nand gate and apply the single input to it.(b) Connect the output to one of the input and the other to the input signal.

25) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

set up time: - the amount of time the data should be stable before the application of the clock signal, where as the hold time is the amount of time the data should be stable after the application of the clock. Setup time signifies maximum delay constraints; hold time is for minimum delay constraints.Setup time is critical for establishing the maximum clock frequency.

26) Differences between D-Latch and D flip-flop?D-latch is level sensitive where as flip-flop is edge sensitive. Flip-flops are made up of latches.

27) What is a multiplexer?Is combinational circuit that selects binary information from one of many input lines and directs it to a single output line. (2n =>n).

28)How can you convert an SR Flip-flop to a JK Flip-flop?By giving the feed back we can convert, i.e !Q=>S and Q=>R.Hence the S and R inputs will act as J and K respectively.

29)How can you convert the JK Flip-flop to a D Flip-flop?By connecting the J input to the K through the inverter.

30)What is Race-around problem?How can you rectify it?The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0, this is called the race around problem.To avoid this undesirable operation, the clock pulse must have a time duration that is shorter than the propagation delay time of the F-F, this is restrictive so the alternative is master-slave or edge-triggered construction.

31)How do you detect if two 8-bit signals are same?XOR each bits of A with B (for e.g. A[0] xor B[0] ) and so on.the o/p of 8 xor gates are then given as i/p to an 8-i/p nor gate. if o/p is 1 then A=B.

32)7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?6 cycles

33) Convert D-FF into divide by 2. (not latch) What is the max clock frequency the circuit can handle, given the following information?T_setup= 6nS T_hold = 2nS T_propagation = 10nSCircuit: Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2. Max. Freq of operation: 1/ (propagation delay+setuptime) = 1/16ns = 62.5 MHz

34)Guys this is the basic question asked most frequently. Design all the basic gates(NOT,AND,OR,NAND,NOR,XOR,XNOR) using 2:1 Multiplexer?Using 2:1 Mux, (2 inputs, 1 output and a select line)(a) NOTGive the input at the select line and connect I0 to 1 & I1 to 0. So if A is 1, we will get I1 that is 0 at the O/P.(b) ANDGive input A at the select line and 0 to I0 and B to I1. O/p is A & B

(c) ORGive input A at the select line and 1 to I1 and B to I0. O/p will be A | B(d) NANDAND + NOT implementations together(e) NOROR + NOT implementations together(f) XORA at the select line B at I0 and ~B at I1. ~B can be obtained from (a) (g) XNORA at the select line B at I1 and ~B at I0

35)N number of XNOR gates are connected in series such that the N inputs (A0,A1,A2......) are given in the following way: A0 & A1 to first XNOR gate and A2 & O/P of First XNOR to second XNOR gate and so on..... Nth XNOR gates output is final output. How does this circuit work? Explain in detail?If N=Odd, the circuit acts as even parity detector, ie the output will 1 if there are even number of 1's in the N input...This could also be called as odd parity generator since with this additional 1 as output the total number of 1's will be ODD.If N=Even, just the opposite, it will be Odd parity detector or Even Parity Generator.

36)An assembly line has 3 fail safe sensors and one emergency shutdown switch.The line should keep moving unless any of the following conditions arise:(i) If the emergency switch is pressed(ii) If the senor1 and sensor2 are activated at the same time.(iii) If sensor 2 and sensor3 are activated at the same time.(iv) If all the sensors are activated at the same timeSuppose a combinational circuit for above case is to be implemented only with NAND Gates. How many minimum number of 2 input NAND gates are required?No of 2-input NAND Gates required = 6 You can try the whole implementation.

37)Design a circuit that calculates the square of a number? It should not use any multiplier circuits. It should use Multiplexers and other logic?This is interesting....1^2=0+1=12^2=1+3=43^2=4+5=94^2=9+7=165^2=16+9=25and so onSee a pattern yet?To get the next square, all you have to do is add the next odd number to the previous square that you found.See how 1,3,5,7 and finally 9 are added.Wouldn't this be a possible solution to your question since it only will use a counter,multiplexer and a couple of adders?It seems it would take n clock cycles to calculate square of n.

38) How will you implement a Full subtractor from a Full adder?

all the bits of subtrahend should be connected to the xor gate. Other input to the xor being one.The input carry bit to the full adder should be made 1. Then the full adder works like a full subtractor

39)A very good interview question... What is difference between setup and hold time. The interviewer was looking for one specific reason , and its really a good answer too..The hint is hold time doesn't depend on clock, why is it so...?Setup violations are related to two edges of clock, i mean you can vary the clock frequency to correct setup violation. But for hold time, you are only concerned with one edge and does not basically depend on clock frequency.

40)In a 3-bit Johnson's counter what are the unused states?2(power n)-2n is the one used to find the unused states in johnson counter.So for a 3-bit counter it is 8-6=2.Unused states=2. the two unused states are 010 and 101

41)The question is to design minimal hardware system, which encrypts 8-bit parallel data. A synchronized clock is provided to this system as well. The output encrypted data should be at the same rate as the input data but no necessarily with the same phase.

The encryption system is centered around a memory device that perform a LUT (Look-Up Table) conversion. This memory functionality can be achieved by using a PROM, EPROM, FLASH and etc. The device contains an encryption code, which may be burned into the device with an external programmer. In encryption operation, the data_in is an address pointer into a memory cell and the combinatorial logic generates the control signals. This creates a read access from the memory. Then the memory device goes to the appropriate address and outputs the associate data. This data represent the data_in after encryption. 41) What is an LFSR .List a few of its industry applications.?

LFSR is a linear feedback shift register where the input bit is driven by a linear function of the overall shift register value. coming to industrial applications, as far as I know, it is used for encryption and decryption and in BIST(built-in-self-test) based applications..

42)what is false path?how it determine in ckt? what the effect of false path in ckt?

By timing all the paths in the circuit the timing analyzer can determine all the critical paths in the circuit. However, the circuit may have false paths, which are the paths in the circuit which are never exercised during normal circuit operation for any set of inputs.An example of a false path is shown in figure below. The path going from the input A of the first MUX through the combinational logic out through the B input of the second MUS is a false path. This path can never be activated since if the A input of the first MUX is activated, then Sel line will also select the A input of the second MUX.STA (Static Timing Analysis) tools are able to identify simple false paths; however they are not able to identify all the false paths and sometimes report false paths as critical paths. Removal of false paths makes circuit testable and its timing performance predictable (sometimes faster)

43)Consider two similar processors, one with a clock skew of 100ps and other with a clock skew of 50ps. Which one is likely to have more power? Why?

Clock skew of 50ps is more likely to have clock power. This is because it is likely that low-skew processor has better designed clock tree with more powerful and number of buffers and overheads to make skew better.

44)What are multi-cycle paths?Multi-cycle paths are paths between registers that take more than one clock cycle to become stable.For ex. Analyzing the design shown in fig below shows that the output SIN/COS requires 4 clock-cycles after the input ANGLE is latched in. This means that the combinatorial block (the Unrolled Cordic) can take up to 4 clock periods (25MHz) to propagate its result. Place and Route tools are capable of fixing multi-cycle paths problem.

45)You have two counters counting upto 16, built from negedge DFF , First circuit is synchronous and second is "ripple" (cascading), Which circuit has a less propagation delay? Why?The synchronous counter will have lesser delay as the input to each flop is readily available before the clock edge. Whereas the cascade counter will take long time as the output of one flop is used as clock to the other. So the delay will be propagating. For Eg: 16 state counter = 4 bit counter = 4 Flip flops Let 10ns be the delay of each flop The worst case delay of ripple counter = 10 * 4 = 40ns The delay of synchronous counter = 10ns only.(Delay of 1 flop)

46) what is difference between RAM and FIFO?FIFO does not have address linesRam is used for storage purpose where as fifo is used for synchronization purpose i.e. when two peripherals are working in different clock domains then we will go for fifo.

47)The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate the direction of rotating.?

2 sensors are required to find out the direction of rotating. They are placed like at the drawing. One of them is connected to the data input of D flip-flop,and a second one - to the clock input. If the circle rotates the way clock sensor sees the light first while D input (second sensor) is zero - the output of the flip-flop equals zero, and if D input sensor "fires" first - the output of the flip-flop becomes high.

48) Draw timing diagrams for following circuit.?

49)Implement the following circuits:(a) 3 input NAND gate using min no of 2 input NAND Gates(b) 3 input NOR gate using min no of 2 inpur NOR Gates(c) 3 input XNOR gate using min no of 2 inpur XNOR GatesAssuming 3 inputs A,B,C?

3 input NAND:Connect :a) A and B to the first NAND gateb) Output of first Nand gate is given to the two inputs of the second NAND gate (this basically

realizes the inverter functionality)c) Output of second NAND gate is given to the input of the third NAND gate, whose other input is C((A NAND B) NAND (A NAND B)) NAND C Thus, can be implemented using '3' 2-input NAND gates. I guess this is the minimum number of gates that need to be used.3 input NOR:Same as above just interchange NAND with NOR ((A NOR B) NOR (A NOR B)) NOR C3 input XNOR:Same as above except the inputs for the second XNOR gate, Output of the first XNOR gate is one of the inputs and connect the second input to ground or logical '0'((A XNOR B) XNOR 0)) XNOR C

50) Is it possible to reduce clock skew to zero? Explain your answer ?Even though there are clock layout strategies (H-tree) that can in theory reduce clock skew to zero by having the same path length from each flip-flop from the pll, process variations in R and C across the chip will cause clock skew as well as a pure H-Tree scheme is not practical (consumes too much area).

51)Design a FSM (Finite State Machine) to detect a sequence 10110?

52)Convert D-FF into divide by 2. (not latch)? What is the max clock frequency of the circuit , given the following information?T_setup= 6nST_hold = 2nST_propagation = 10nSCircuit:Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2.Max. Freq of operation:1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz

53)Give the circuit to extend the falling edge of the input by 2 clock pulses?The waveforms are shown in the following figure.

54) For the Circuit Shown below, What is the Maximum Frequency of Operation?Are there any hold time violations for FF2? If yes, how do you modify the circuit to avoid them?

The minumum time period = 3+2+(1+1+1) = 8ns Maximum Frequency = 1/8n= 125MHz.And there is a hold time violation in the circuit,because of feedback, if you observe, tcq2+AND gate delay is less than thold2,To avoid this we need to use even number of inverters(buffers). Here we need to use 2 inverters each with a delay of 1ns. then the hold time value exactly meets.

55)Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch ?56)How to implement a Master Slave flip flop using a 2 to 1 mux?

57)how many 2 input xor's are needed to inplement 16 input parity generator ?It is always n-1 Where n is number of inputs.So 16 input parity generator will require 15 two input xor's .

58)Design a circuit for finding the 9's compliment of a BCD number using 4-bit binary adder and some external logic gates?9's compliment is nothing but subracting the given no from 9.So using a 4 bit binary adder we can just subract the given binary no from 1001(i.e. 9).Here we can use the 2's compliment method addition.

59) what is Difference between writeback and write through cache?A caching method in which modifications to data in the cache aren't copied to the cache source until absolutely necessary. Write-back caching is available on many microprocessors , including all Intel processors since the 80486. With these microprocessors, data modifications to data stored in the L1 cache aren't copied to main memory until absolutely necessary. In contrast, a write-through cache performs all write operations in parallel -- data is written to main memory and the L1 cache simultaneously. Write-back caching yields somewhat better performance than write-through caching because it reduces the number of write operations to main memory. With this performance improvement comes a slight risk that data may be lost if the system crashes.A write-back cache is also called a copy-back cache.60)Difference between Synchronous,Asynchronous & Isynchronous communication?Sending data encoded into your signal requires that the sender and receiver are both using the same enconding/decoding method, and know where to look in the signal to find data. Asynchronous systems do not send separate information to indicate the encoding or clocking information. The receiver must decide the clocking of the signal on it's own. This means that the receiver must decide where to look in the signal stream to find ones and zeroes, and decide for itself where each individual bit stops and starts. This information is not in the data in the signal sent from transmitting unit.Synchronous systems negotiate the connection at the data-link level before communication begins. Basic synchronous systems will synchronize two clocks before transmission, and reset their numeric counters for errors etc. More advanced systems may negotiate things like error correction and compression.Time-dependent. it refers to processes where data must be delivered within certain time constraints. For example, Multimedia stream require an isochronous transport mechanism to ensure that data is delivered as fast as it is displayed and to ensure that the audio is synchronized with the video.61) What are different ways Multiply & Divide? 

Set quotient to zero 

Repeat while dividend is greater than or equal to divisor 

Subtract divisor from dividend 

Add 1 to quotient 

End of repeat block 

quotient is correct, dividend is remainder 

STOP

Binary Division by Shift and SubtractBasically the reverse of the mutliply by shift and add.

Set quotient to 0 

Align leftmost digits in dividend and divisor 

Repeat 

If that portion of the dividend above the divisor is greater than or equal to the divisor 

Then subtract divisor from that portion of the dividend and 

Concatentate 1 to the right hand end of the quotient 

Else concatentate 0 to the right hand end of the quotient 

Shift the divisor one place right 

Until dividend is less than the divisor 

quotient is correct, dividend is remainder 

STOP 

Binary Multiply - Repeated Shift and AddRepeated shift and add - starting with a result of 0, shift the second multiplicand to correspond with each 1 in the first multiplicand and add to the result. Shifting each position left is equivalent to multiplying by 2, just as in decimal representation a shift left is equivalent to multiplying by 10.

Set result to 0 

Repeat 

Shift 2nd multiplicand left until rightmost digit is lined up with leftmost 1 in first multiplicand 

Add 2nd multiplicand in that position to result 

Remove that 1 from 1st multiplicand 

Until 1st multiplicand is zero 

Result is correct 

STOP 

62)What is a SoC (System On Chip), ASIC, "full custom chip", and an FPGA?

There are no precise definitions. Here is my sense of it all. First, 15 years ago, people were unclear on exactly what VLSI meant. Was it 50000 gates? 100000 gates? was is just anything bigger than LSI? My professor simply told me that; VLSI is a level of complexity and integration in a chip that demands Electronic Design Automation tools in order to succeed. In other words, big enough that manually drawing lots of little blue, red and green lines is too much for a human to reasonably do. I think that, likewise, SoC is that level of integration onto a chip that demands more expertise beyond traditional skills of electronics. In other words, pulling off a SoC demands Hardware, Software, and Systems Engineering talent. So, trivially, SoCs aggressively combine HW/SW on a single chip. Maybe more pragmatically, SoC just means that ASIC and Software folks are learning a little bit more about each other's techniques and tools than they did before. Two other interpretations of SoC are 1) a chip that integrates various IP (Intellectual Property) blocks on it and is thus highly centered with issues like Reuse, and 2) a chip integrating multiple classes of electronic circuitry such as Digital CMOS, mixed-signal digital and analog (e.g. sensors, modulators, A/Ds), DRAM memory, high voltage power, etc. 

ASIC stands for "Application Specific Integrated Circuit". A chip designed for a specific application. Usually, I think people associate ASICs with the Standard Cell design methodology. Standard Cell design and the typical "ASIC flow" usually means that designers are using Hardware Description Languages, Synthesis and a library of primitive cells (e.g. libraries containing AND, NAND, OR, NOR, NOT, FLIP-FLOP, LATCH, ADDER, BUFFER, PAD cells that are wired together (real libraries are not this simple, but you get the idea..). Design usually is NOT done at a transistor level. There is a high reliance on automated tools because the assumption is that the chip is being made for a SPECIFIC APPLICATION where time is of the essence. But, the chip is manufactured from scratch in that no pre-made circuitry is being programmed or reused. ASIC designer may, or may not, even be aware of the locations of various pieces of circuitry on the chip since the tools do much of the construction, placement and wiring of all the little pieces.

Full Custom, in contrast to ASIC (or Standard Cell), means that every geometric feature going onto the chip being designed (think of those pretty chip pictures we have all seen) is controlled, more or less, by the human design. Automated tools are certainly used to wire up different parts of the circuit and maybe even manipulate (repeat, rotate, etc.) sections of the chip. But, the human designer is actively engaged with the physical features of the circuitry. Higher human crafting and less reliance on standard cells takes more time and implies higher NRE costs, but lowers RE costs for standard parts like memories, processors, uarts, etc.

FPGAs, or Field Programmable Gate Arrays are completely designed chips that designers load a programming pattern into to achieve a specific digital function. A bit pattern (almost like a software program) is loaded into the already manufactured device which essentially interconnects lots of available gates to meet the designers purposes. FPGAs are sometimes thought of as a "Sea of Gates" where the designer specifies how they are connected. FPGA designers often use many of the same tools that ASIC designers use, even though the FPGA is inherently more flexible. All these things can be intermixed in hybrid sorts of ways. For example, FPGAs are now available that have microprocessor embedded within them which were designed in a full custom manner, all of which now demands "SoC" types of HW/SW integration skills from the designer.

63)What is "Scan" ? 

§Scan Insertion and ATPG helps test ASICs (e.g. chips) during manufacture. If you know what JTAG boundary scan is, then Scan is the same idea except that it is done inside the chip instead of on the entire board. Scan tests for defects in the chip's circuitry after it is manufactured (e.g. Scan does not help you test whether your Design functions as intended). ASIC designers usually implement the scan themselves and occurs just after synthesis. ATPG (Automated Test Pattern Generation) refers to the creation of "Test Vectors" that the Scan circuitry enables to be introduced into the chip. Here's a brief summary:

· Scan Insertion is done by a tool and results in all (or most) of your design's flip-flops to be replaced by special "Scan Flip-flops". Scan flops have additional inputs/outputs that allow them to be configured into a "chain" (e.g. a big shift register) when the chip is put into a test mode. 

· The Scan flip-flops are connected up into a chain (perhaps multiple chains) 

· The ATPG tool, which knows about the scan chain you've created, generates a series of test vectors. 

· The ATPG test vectors include both "Stimulus" and "Expected" bit patterns. These bit vectors are shifted into the chip on the scan chains, and the chips reaction to the stimulus is shifted back out again. 

· The ATE (Automated Test Equipment) at the chip factory can put the chip into the scan test mode, and apply the test vectors. If any vectors do not match, then the chip is defective and it is thrown away. 

· Scan/ATPG tools will strive to maximize the "coverage" of the ATPG vectors. In other words, given some measure of the total number of nodes in the chip that could be faulty (shorted, grounded, "stuck at 1", "stuck at 0"), what percentage of them can be detected with the ATPG vectors? Scan is a good technology and can achive high coverage in the 90% range. 

· Scan testing does not solve all test problems. Scan testing typically does not test memories (no flip-flops!), needs a gate-level netlist to work with, and can take a long time to run on the ATE. 

· FPGA designers may be unfamiliar with scan since FPGA testing has already been done by the FPGA manufacturer. ASIC designers do not have this luxury and must handle all the manufacturing test details themselves. 

· Check out the Synopsys WWW site for more info.

1) Write a verilog code to swap contents of two registers with and without a temporary register?

With temp reg ;

always @ (posedge clock)begintemp=b;b=a;a=temp;end

Without temp reg;

always @ (posedge clock)begina <= b; b <= a; end 2) Difference between blocking and non-blocking?(Verilog interview questions that is most commonly asked)

The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. For example, the following Verilog program // testing blocking and non-blocking assignment module blocking; reg [0] A, B; initial begin: init1 A = 3; #1 A = A + 1; // blocking procedural assignment B = A + 1; $display("Blocking: A= %b B= %b", A, B ); A = 3; #1 A <= A + 1; // non-blocking procedural assignmentB <= A + 1; #1 $display("Non-blocking: A= %b B= %b", A, B ); end endmodule produces the following output: Blocking: A= 00000100 B= 00000101 Non-blocking: A= 00000100 B= 00000100 The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. This reflects how register transfers occur in some hardware systems. blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential

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Difference between task and function?

Function:A function is unable to enable a task however functions can enable other functions.A function will carry out its required duty in zero simulation time. ( The program time will not be incremented during the function routine)Within a function, no event, delay or timing control statements are permittedIn the invocation of a function their must be at least one argument to be passed.Functions will only return a single value and can not use either output or inout statements.

Tasks:Tasks are capable of enabling a function as well as enabling other versions of a TaskTasks also run with a zero simulation however they can if required be executed in a non zero simulation time.Tasks are allowed to contain any of these statements.A task is allowed to use zero or more arguments which are of type output, input or inout.

A Task is unable to return a value but has the facility to pass multiple values via the output and inout statements .

4) Difference between inter statement and intra statement delay?

//define register variablesreg a, b, c;

//intra assignment delaysinitialbegina = 0; c = 0;b = #5 a + c; //Take value of a and c at the time=0, evaluate//a + c and then wait 5 time units to assign value//to b.end

//Equivalent method with temporary variables and regular delay controlinitialbegina = 0; c = 0;temp_ac = a + c;#5 b = temp_ac; //Take value of a + c at the current time and//store it in a temporary variable. Even though a and c//might change between 0 and 5,//the value assigned to b at time 5 is unaffected.end

5) What is delta simulation time?

6) Difference between $monitor,$display & $strobe?

These commands have the same syntax, and display text on the screen during simulation. They are much less convenient than waveform display tools like cwaves?. $display and $strobe display once every time they are executed, whereas $monitor displays every time one of its parameters changes.The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current simulation time unit rather than exactly where it is executed. The format string is like that in C/C++, and may contain format characters. Format characters include %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time), %m (hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the number instead of the space needed. Append b, h, o to the task name to change default format to binary, octal or hexadecimal.Syntax:$display ("format_string", par_1, par_2, ... );$strobe ("format_string", par_1, par_2, ... );$monitor ("format_string", par_1, par_2, ... );

7) What is difference between Verilog full case and parallel case?

A "full" case statement is a case statement in which all possible case-expression binary patterns can be matched to a case item or to a case default. If a case statement does not include a case default

and if it is possible to find a binary case expression that does not match any of the defined case items, the case statement is not "full." A "parallel" case statement is a case statement in which it is only possible to match a case expression to one and only one case item. If it is possible to find a case expression that would match more than one case item, the matching case items are called "overlapping" case items and the case statement is not "parallel."

8) What is meant by inferring latches,how to avoid it?

Consider the following :always @(s1 or s0 or i0 or i1 or i2 or i3)case ({s1, s0})2'd0 : out = i0;2'd1 : out = i1;2'd2 : out = i2;endcase

in a case statement if all the possible combinations are not compared and default is also not specified like in example above a latch will be inferred ,a latch is inferred because to reproduce the previous value when unknown branch is specified.For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is inferred.The same may be observed in IF statement in case an ELSE IF is not specified.To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided.

9) Tell me how blocking and non blocking statements get executed?

Execution of blocking assignments can be viewed as a one-step process:1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement. A blocking assignment "blocks" trailing assignments in the same always block from occurring until after the current assignment has been completed

Execution of nonblocking assignments can be viewed as a two-step process:1. Evaluate the RHS of nonblocking statements at the beginning of the time step. 2. Update the LHS of nonblocking statements at the end of the timestep.

10) Variable and signal which will be Updated first?

Signals

11) What is sensitivity list?

The sensitivity list indicates that when a change occurs to any one of elements in the list change, begin…end statement inside that always block will get executed.

12) In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?

Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

13) Tell me structure of Verilog code you follow?

A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the simulation`timescale 1 ns / 10 psmodule name (input and outputs);// parameter declarationsparameter parameter_name = parameter value;// Input output declarationsinput in1;input in2; // single bit inputsoutput [msb] out; // a bus output// internal signal register type declaration - register types (only assigned within always statements). reg register variable 1;reg [msb] register variable 2;// internal signal. net type declaration - (only assigned outside always statements) wire net variable 1;// hierarchy - instantiating another modulereference name instance name (.pin1 (net1),.pin2 (net2),..pinn (netn));// synchronous proceduresalways @ (posedge clock)begin.end// combinatinal proceduresalways @ (signal1 or signal2 or signal3)begin.endassign net variable = combinational logic;endmodule

14) Difference between Verilog and vhdl?

CompilationVHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

Data typesVHDL. A multitude of language or user defined data types can be used. This may mean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it's simplicity.

Design reusabilityVHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive. 

15) What are different styles of Verilog coding I mean gate-level,continuous level and others explain in detail?

16) Can you tell me some of system tasks and their purpose?

$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.The most useful of these is $display.This can be used for displaying strings, expression or values of variables.Here are some examples of usage.$display("Hello oni");--- output: Hello oni$display($time) // current simulation time.--- output: 460counter = 4'b10;$display(" The count is %b", counter);--- output: The count is 0010$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode where theuser can enter commands; $finish exits the simulator back to the operating system

17) Can you list out some of enhancements in Verilog 2001?

In earlier version of Verilog ,we use 'or' to specify more than one element in sensitivity list . In

Verilog 2001, we can use comma as shown in the example below.// Verilog 2k example for usage of commaalways @ (i1,i2,i3,i4)

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . This removes typo mistakes and thus avoids simulation and synthesis mismatches,Verilog 2001 allows port direction and data type in the port list of modules as shown in the example belowmodule memory (input r,input wr,input [7] data_in,input [3] addr,output [7] data_out);

18)Write a Verilog code for synchronous and asynchronous reset?

Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg:always @ (posedge clk )

begin if (reset). . . endAsynchronous means clock independent so reset must be present in sensitivity list.EgAlways @(posedge clock or posedge reset)beginif (reset). . . end

19) What is pli?why is it used?

Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs with programs written in C language. It also provides mechanism to access internal databases of the simulator from the C program.PLI is used for implementing system calls which would have been hard to do otherwise (or impossible) using Verilog syntax. Or, in other words, you can take advantage of both the paradigms - parallel and hardware related features of Verilog and sequential flow of C - using PLI.

20) There is a triangle and on it there are 3 ants one on each corner and are free to move along sides of triangle what is probability that they will collide?

Ants can move only along edges of triangle in either of direction, let's say one is represented by 1 and another by 0, since there are 3 sides eight combinations are possible, when all ants are going in same direction they won't collide that is 111 or 000 so probability of collision is 2/8=1/4

21) Tell me about file I/O?

21)What is difference between freeze deposit and force?

$deposit(variable, value);This system task sets a Verilog register or net to the specified value. variable is theregister or net to be changed; value is the new value for the register or net. The valueremains until there is a subsequent driver transaction or another $deposit task for thesame register or net. This system task operates identically to the ModelSimforce -deposit command.

The force command has -freeze, -drive, and -deposit options. When none of these isspecified, then -freeze is assumed for unresolved signals and -drive is assumed for resolvedsignals. This is designed to provide compatibility with force files. But if you prefer -freezeas the default for both resolved and unresolved signals.

Verilog interview Questions22)Will case infer priority register if yes how give an example?

yes case can infer priority register depending on coding stylereg r;// Priority encoded mux,always @ (a or b or c or select2)beginr = c;case (select2)2'b00: r = a;2'b01: r = b;endcaseend

Verilog interview Questions23)Casex,z difference,which is preferable,why?

CASEZ :Special version of the case statement which uses a Z logic value to represent don't-care bits. CASEX :Special version of the case statement which uses Z or X logic values to represent don't-care bits.

CASEZ should be used for case statements with wildcard don't cares, otherwise use of CASE is required; CASEX should never be used.This is because:Don't cares are not allowed in the "case" statement. Therefore casex or casez are required. Casex will automatically match any x or z with anything in the case statement. Casez will only match z's -- x's require an absolute match.

Verilog interview Questions24)Given the following Verilog code, what value of "a" is displayed?

always @(clk) begina = 0;a <= 1; $display(a); end This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time: 1: Active Events (blocking statements) 2: Inactive Events (#0 delays, etc) 3: Non-Blocking Assign Updates (non-blocking statements) 4: Monitor Events ($display, $monitor, etc). Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display

statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1. 25) What is the difference between the following two lines of Verilog code?#5 a = b;a = #5 b;

#5 a = b; Wait five time units before doing the action for "a = b;".a = #5 b; The value of b is calculated and stored in an internal temp register,After five time units, assign this stored value to a.

26)What is the difference between:

c = foo ? a : b;andif (foo) c = a;else c = b;

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

27)What are Intertial and Transport Delays ??

28)What does `timescale 1 ns/ 1 ps signify in a verilog code?

'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage : `timescale

34)what is verilog case (1) ? 

wire [3] x;always @(...) begincase (1'b1)x[0]: SOMETHING1;x[1]: SOMETHING2;x[2]: SOMETHING3;x[3]: SOMETHING4;endcaseendThe case statement walks down the list of cases and executes the first one that matches. So here, if the lowest 1-bit of x is bit 2, then something3 is the statement that will get executed (or selected by the logic). 

35) Why is it that "if (2'b01 & 2'b10)..." doesn't run the true case? 

This is a popular coding error. You used the bit wise AND operator (&) where you meant to use the logical AND operator (&&). 

36)What are Different types of Verilog Simulators ?

There are mainly two types of simulators available. 

Event Driven Cycle Based 

Event-based Simulator: 

This Digital Logic Simulation method sacrifices performance for rich functionality: every active signal is calculated for every device it propagated

Re: What is glitch and how it may affect the performance of the design?

"An electronics glitch is an undesired transition that occurs before the signal settles to its intended value. In other words, glitch is an electrical pulse of short duration that is usually the result of a fault or design error, particularly in a digital circuit. For example, many electronic components such as flip-flops are triggered by a pulse that must not be shorter than a specified minimum duration, otherwise the component may malfunction. A pulse shorter than the specified minimum is called a glitch. A related concept is the runt pulse, a pulse whose amplitude is smaller than the minimum level specified for correct operation, and a spike, a short pulse similar to a glitch but often caused by ringing or crosstalk. A glitch can occur in the presence of race condition in a poorly designed digital logic circuit."

Glitches in digital circuit can cause increased power consumption due to unnecessary switching. 

Step 1: Prepare an Requirement Specification

Step 2: Create an Micro-Architecture Document.

Step 3: RTL Design & Development of IP's

Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting Errors/Analyze whether the RTL is Synthesis friendly.

Step 4a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of the RTL

Step 4b: Perform Property Checking , to verify the RTL implementation and the specification understanding is matching.

Step 5: Prepare the Design Constraints file (clock definitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad load definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an SDC synopsys_constraints, specific to synopsys synthesis Tool (design-compiler)

Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which synthesis needs to be targeted for, which has the functional/timing information available for the standard-cell library and the wire-load models for the wires based on the fanout length of the connectivity), RTL files and the Design Constraint files, So that the Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet the design-constraints requirements. After performing synthesis, as a part of the synthesis flow, need to build scan-chain connectivity based on the DFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds the scan-chain.

7: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT) after synthesis.

Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting the power targets.

Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the design is meeting the functional requirements.

Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that the synthesis Tool has not altered the functionality.

Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format) file and synthesized netlist file, to check whether the Design is meeting the timing-requirements.

Step 7e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement.

Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog format) and the SDC (constraints file) is passed as input files to the Placement and Routing Tool to perform the back-end Actitivities.

Step 9: The next step is the Floor-planning, which means placing the IP's based on the connectivity,placing the memories, Create the Pad-ring, placing the Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper accessibility for Package routing), meeting the SSN requirements(Simultaneous Switching Noise) that when the high-speed bus is switching that it doesn't create any noise related acitivities, creating an optimised floorplan, where the design meets the utilization targets of the chip.

Step 9a : Release the floor-planned information to the package team, to perform the package feasibility analysis for the pad-ring .

Step 9b: To the placement tool, rows are cut, blockages are created where the tool is prevented from placing the cells, then the physical placement of the cells is performed based on the timing/area requirements.The power-grid is built to meet the power-target's of the Chip .

Step 10: The next step is to perform the Routing., at first the Global routing and Detailed routing, meeting the DRC(Design Rule Check) requirement as per the fabrication requirement.

Step 11: After performing Routing then the routed Verilog netlist, standard-cells LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is generated.

Step 12: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement and Routing step.

Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design has met the power targets.

Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the design is meeting the functional requirement .

Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm that the place & route Tool has not altered the functionality.

Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist file, to check whether the Design is meeting the timing-requirements.

Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement, Peform the Fault-coverage with the DFT tool and Generate the ATPG test-vectors.

Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL)

Step 12g: Perform DRC(Design Rule Check) verfication called as Physical-verification, to confirm that the design is meeting the Fabrication requirements.

Step 12h: Perform LVS(layout vs Spice) check, a part of the verification which takes a routed netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call it SPICE-S) and compare that the two are matching.

Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is meeting the ERC requirement.

Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and proper guarding is there in case if we have both analog and digital portions in our Chip. We have seperate Power and Grounds for both Digital and Analog Portions, to reduce the Substrate-noise.

Step 12k: Perform seperate STA(Static Timing Analysis) , to verify that the Signal-integrity of our Chip. To perform this to the STA tool, the routed netlist and SPEF file(parasitics including coupling capacitances values), are fed to the tool. This check is important as the signal-integrity effect can cause cross-talk delay and cross-talk noise effects, and hinder in the functionality/timing aspects of the design.

Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-stand the static and dynamic power-drops with in the design and the IR-drop is with-in the target limits.

Step 13: Once the routed design is verified for the design constraints, then now the next step is chip-finishing activities (like metal-slotting, placing de-coupling caps).

Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which the fab can understand, GDS file.

Step 15: After the GDS file is released , perform the LAPO check so that the database released to the fab is correct.

Step 16: Perform the Package wire-bonding, which connects the chip to the Package.    

VLSI flow was evolved similar to the flow involved in Building Construction.Now let us dwelve in to the constuction flow to better understand the VLSI Chip design flow development.When ever we start to construct a building, we will have an architecture, how the building should look like , the exterior looks and all, similar to that we will be designing an architecture in the chip-design, based on the requirement of the product, what the product is addressed for and whom to serve what needs, the so called specification, will having the modules.

Now lets go in to the implementation part of both the Building & Chip.

We at first come with the floorplan of the building, similarly we come with the floorplan of the Chip, Based on the connectivity/accessibility/vaasthu we place our rooms, similarly we have the constraints to place the blocks. Like we build the building with bricks, for  Chip Design  we have libraries, which are like pre-designed bricks, for a specific functionality.

Now let us try to understand the power-structure or electrical connectivity in our Building. Initially we have an Electrical plan for our building, where we have a requirement that all our electrical gadgets needs to get power. Similar to that we have a Chip power requirement, The required power is supplied through the power-pads, over a ring like topology to have a uniform distribution across all corners of the chip, and the supply has to reach all the standard-cells(bricks for Chip-Designing).,this is called as power-grid topology in the Chip-Design, now the requirement is how well we design our Power-grid, to reduce the IR-drop so that our standard-cells get proper power requirement.

I would not make justice, if I dont discuss about clock and clock-tree in the Chip-Design flow. We have synchronous way of designing and asynchronous way of designing(difficult to verify). Majority of chips follow Synchronous way of coding, for which Static Timing Analysis is possible. For the relevancy of the flops the clock to those flops should reach at the same time from the crystal, with in some skew targets with in the chip.In order to make this happen, a step called as clock-tree is performed after power-grid is created.

Let us try to visualize the concept behind Place & Route in Chip Design. We need to undergo lot of modelling concepts, to understand the process of Chip-Designing. To have a better understanding of this concept of place and route, let us assume a society where people who are speaking different languages are living , and let us visualize that people talking of the same languages are living in a community, then the communication is much easier , similar way in the chip-designing, the standard-cells who are having design relation-ships, are placed closer in the Placement flow this concept is called as regioning. Now with in the regioning, of the groups of the standard-cells, the cells which are really sharing data, has to placed close-by so that there timing is achieved and well optimized.This step is called placement, Connectivity across the standard-cells is called as routing, the challenge is having optimized or reduced wire-lengths.

Now let us try to try to understand the concept behind signal integrity in the Chip-Design , often called us SI Effect. As our process is shrinking day by day, and our silicon-realestate is costly, we try to accommodate more and more standard-cells in the limited area, so the cells are placed in very close proximity, so the switching of one can have an impact over the others behaviour, which can make the path to be faster or slower, this issue is called as signal-integrity. So similar way in our construction in order to maintain the integrity with in the house(neighbour free-zone), within the limited zone of modurality, we try to create fences, across buildings, similarly we can think of a

concept called as Shielding, the high frequency signal net with the power-nets running across. We perform spacing across the buildings, similar way we can perform spacing across the nets, which are in close proximities.

In order to validate the silicon from the manufacturability issues, the concept in the Chip Desigining is Design for Test(DFT). One of the DFT techniques is scan-chain. To understand the concept of the scan-chain, we can visualize that we have a front-door entry and a back-door exit, and a person passes from the front-door and exits from the back-door exit of the building, that we are sure that there is no blocking within the rooms in the building, to make that person stuck , similar to this analogy the flip-flops are connected to-gether creating a scan-chain and test-input values are passed from the scan-chain input of the chip and expected data is visualized in the scan-chain output of the chip, then the assumption is the chip is free from manufacturability issues like stuck-at faults(stuck-at one or stuck at zeros).

This is just a tip-of an ice-berg...I : can we sign-off in the Static Timing Analysis tool, with the real operating frequency or do you see any reason we need to have some extra margins.

J : Sir, we can close with the real operating frequency itself, but un-fortunately there are so much variations.

I : what do you mean by variations?

J : Die to Die there will be variations, Wafer to Wafer there will be Variations, lot to lot there will be variations, Package variations, on chip variations sir.

I : What do you mean by on-chip variations.

J : with in the chip itself, there are so many things which can cause Timing Variations, or Timing uncertanities Sir, like

    *      IR Drop related Timing Variation    *      Channel length Variation    *      temperature variations

to name a few...

I : good, do you really account it in your STA analysis or just leave it God .

J : We live in a technical world, when we know there can be an issue, we cannot leave it for chance and more over huge money is involved Sir, there are ways to take care in STA sir.

I : I like your attitude. let me know how will you do this.

J : Sir, I had used primetime for my STA analysis and there are concepts for OCV[on-chip variation] , we used to use Derate methodology.

I : what is this Derate methodology you are referring too?

J : what i meant was there are some commands like "set_timing_derate" , which can be used in the cell and for the net , for the clock path, for the Data path and OCV effects can be modelled and Analyzed and Qualified Sir.

I : Very Good. You know the practical aspects.

On Chip Variations or inter-die variations could be caused due to•IR drop•Vt variations•Channel length variation

So the normal flow of qualifying the Timing with plain worst and best corners is no more enough.

To account for this variations need to account an inbuilt pessimism by derating the paths thereby the cells will perform to be slower and then validate the design behaviour and qualifying upfront .

1. Library Characterizing: "Chip designing is all about Modeling the silicon", and how well we characterize the silicon, is all the game. So initially let us assume our process technology is say "32nm", for example: Now we need to develop a test-chip, having modules (digital & analog), and study our silicon timings. Now the toughest job is to generate library views(formats specific to each tool understandable formats).There is a bit of timing in accuracy possible in the views across the formats. 2. Modeling of Wires: How well do we co-relate the timing achieved in synthesis and the timing after place and route.Usually the synthesis and place and route (P & R) tools are different. let us take for example:For synthesis: Synopsys Design CompilerFor placement and Route tool : Magma Blast fusion. Synthesis Tool Timing:In the synthesis tool, in order to model the wires we use a concept called as "Wireload models", Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for "n" number of fanin then we estimate its delay as say "x" delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available. Place & Route Tool Timing:In the placement and Route Tool, there is no concept based on statistics for the wire-delay values, everything is real, what i mean here , this will what be seen close in the silicon.So in this scenario, The timing convergence is really required to attain closure in "Synthesis Vs placement & Route Tool" otherwise called as "Timing convergence or Timing correlation Frontend Vs Backend". 3. Multi-mode Scenario Timing Convergence:Todays world , we need more but we are greedy as well.We need more functionality, more interfaces, typically means more pin-count, but more pin count needs bigger package cost. We are neither ready for a bigger package cost, so now what is the alternative , nor comprise on reducing our interfaces. so here comes the solution "Pin-muxing". it means, the same pin will act for one or more interfaces depending upon the chip configuration and their timing requirement varies depending on their electrical Specification requirement.As on date, most of the placement and routing tool cannot operate on the Multimode timing requirement scenario and can read and perform with multiple constraints file, it is very difficult in the tools perspective also to understand multiple constraints and preserve multiple arrival time requirements at each node with different values, it is a really tough game, in optimizing memory requirements, run time requirements and all that stuff in terms of EDA tools.So if the path is not optimized for multi-mode and just optimized for a single worst case mode(which is very tough to predict what could be a worst case scenario) and give it to placement and routing tool, then while running Static Timing Analysis(STA) we could visualize lot of surprises, which will be very much new in terms of performance. 4. On chip Variations:Todays world everything changes, what to model and what not , i am going crazy.As per the famous quote by John.F. Kennedy "Change is the law of Life", which is very much true for semiconductor industry. And Variation is all about "Rate of Change". Wafer Variations: Every wafer can vary in terms of timing performance, it is hard to predict, there could fast lot , slow lot, typical lot in terms of timing performance. Intra die Variations: In a single wafer, distribution dies across the wafer will vary in terms of timing performance. Inter die Variations: Within a die/chip, there could be timing performance issue.. Now the Art is all about modeling these variations and prooving our Designs will be working for these variations in real time scenario and qualify the Design for Robustness.

 

Lets brush our Basics on Statistical Timing Analysis

What are the various Timing Paths in a Chip?

1. Path starting from Input Data pad and Ending at Register pin.

2. Path starting from clock-pin of a Register and Ending at Data pin of a Register(Reg-to-Reg path).

3. Path starting from output of a Register and Ends at output pad of a chip.

4. Path starting from input data pad and ends at output data pad(pure combo path).

How to time the output paths?

How to time Input paths?

How to deal with False-paths?

How to deal with Multicycle paths?

How to time the source-synchronous paths?

How many minimum modes i should qualify STA for a chip

1. Scan Shift mode

2. Scan Capture mode

3. MBIST mode

4. Functional modes for Each Interface

5. Boundary scan mode

6. scan-compression mode

How many minimum process lots , should STA be qualified.

1. Fast corner

2. Slow corner

3. Typical corner

How many minimum Timing , Should STA be qualified.

1. normal delay mode(with out applying deration)

2. On-chip variation mode (deration applied)

3. SI mode (Signal integrity cross talk impact on STA)

How many minimum STA runs should we needed to address = 6*3*3.

what do I need to look for in the design, to meet Timing Qualification/Closure1. Perform check design/model.2. check how many flops are not with clocks.3. check for any timing loop in the design4. check whether all the Ports are constrained for input/output delays5. Check whether all the clock-gating checks are performed.6. Is the clock skews/clock insertions are in the limit , rather it is in the acceptable targets.7. Did the design has setup/hold uncertainities mentioned for jitter and so on and meets timing requirements.8. Is the Design functionaly fine in a Multi mode Design Environment9. Is the Design meets asynchronous checks like recovery/removal.What is my next step to be performed?

Now Lets start with an assumption that anything may go wrong

What are the various areas can things go wrong?•List down the areas in the flow that things can go wrong and derive a methodology to verify at each and every stage.•List down all your uncertainities that could potentially happen and how to model it and how to constrain and verify up-front.

Lets Explore and re-visit each and every area in the Design flow to cover potential risk•Functional Verification (RTL level , Gate level)•Formal Verification•Static Timing Analysis•Physical Verification•Power Simulation•Thermal Simulation•Noise Simulation•Test Simulation•Emulation•Hardware proto-type•Hardware Software co-simulation•Transistor level Simulation

Now lets Venture in to each area and insure it

Functional Verification:•TLM(Transaction Level Modelling)•Linting•RTL Simulation ( Enivronment involving : stimulus generators, monitors, response checkers, transactors)•Gate level Simulation•Mixed-signal simulations•Regression

How Much Did I cover in the functional part - What is my Coverage Metric? and what are the methodologies used?•Is the verification tests covered pin-pointed tests or tests with random seeds to cover all the corner-cases.•Code-coverage•Line coverage•Functional coverage

Formal Verification:•Equivalence checkers

• RTL versus Gate• Pre-layout versus post-layout Netlist• Assertion based property checkers(Mathematical techniques to allow larger state space

coverage)Timing Verification:

• With whom the Chip is talking to (To know the Interface Timing's)• What is the Timing-budgets with in the chip, and how to constrain it within each I.P. and

finally analysing and sigining for Timing-targets• How to address the timing targets with varying process parameters(on-chip variation) what

is the optimal derating number to be set so that variations are addressed.• Steps to minimize the clock-jitter.

Physical Verification:Is my design process friendly ?

• DRC (Design Rule Check)• LVS• Antenna Checks• ERC• ESD checks• Speed monitor's

Noise Simulation:How Noisy is my design so need to perform noise simulations addressing these areas

• Simultaneous Switching Noise (SSN)• Package Noise• EMI Noise• Power-ground noise• Cross-talk noise• Analog Noise• Substrate noise

Power Simulations:Is my design meeting power-targets

• IR drop analysis• Dynamic power simulations

Power related methodologies• Optimum location for De-caps• Multiple Voltage domains• Multi Vt design• DVFS (Dynamic Voltage and Frequency scaling)• Clock-gating Techniques• Power Management Unit (to shut-off when not required)• Level-Shifters across cross-voltage domains

Thermal SimulationsStudy the thermal targets and mechanism to reduceTest SimulationsIs my design testable once chip comes out, methodologies to identify the problematic areas

• Boundary Scan• Memory BIST simulations• Tester specific vector generation and simulations• Tester vector compression techniques to reduce tester time• At-speed testing mechanism's• Scan-shift and scan-capture methodologies• IDDQ testing• Wafer Level Burn-in Tests to know Known Good Dies(KGD)• Wire pull tests• DC parameter tests• AC parameter tests• Path-delay tests• Delay tests• Transition fault testing

Addressing DSM and Yield Issues• Redundant via's• Spacing non critical areas to be lithography friendly• Wire widening• Metal Filling• Metal Slotting

Emulation:Emulates the functional behaviour of the design. Synthesizable assertions are mapped to emulators to perform at system speeds.Hardware prototype:

Proto-typing the system requirements in a programmble FPGA'sInspite of all the Verification Methodologies and Strategies if things goes wrong, how to address that in the design - Methodologies to reduce cost & time

• Spare-gates• Redundant rows/columns in the memories• Redundant vias• Built-in self repair memories• Focussed Ion Beam Methodologies

Synopsys Synthesis Constraints Template

###Customize according to your Design needs

########################################################

#### Portion to Edit

#### Variables clock1_name is the Clock name, clock1_period is the Clock period,

#### clock1_period_half is the half of the clock period

#### set clock1_name

#### set clock1_period

#### set clock1_period_half [expr $clock1_period / 2]

#### set clock1_period_onetenth [expr $clock1_period / 10]

#### set clock1_period_onetwenth [expr $clock1_period / 20]

#### set clock1_latency

#### set CTS_clock1_skew

########################################################

#### Source the .synopsys_dc_setup file, File which has all the library settings

source .synopsys_dc_setup

#### Read the rtl files

read_verilog

### Similar way read all the RTL files

### Specify the Top-level file name

current_design

#### Link the design

link

#### Uniquify the design, for designs with multiple instantiation

uniquify

#### Design Constraints following....####Specify the Clocks in the Design ######

#### Example for one Clock in the Design named clock1

create_clock -period $clock1_period -waveform [list 0 $clock1_period_half ] -name $clock1_name

set_clock_skew -ideal -uncertainty $CTS_clock1_skew $clock1_name

set_clock_transition 0.3 $clock1_name

set_clock_latency $clock1_latency_number $clock1_name

set_dont_touch_network $clock1_name

#### Generate the same list of constraints for all the clocks in the design

#### Generate the False and Multi-cycle paths in the design as Timing Exceptions for the tool.

#### False And Multi-cycle paths are purely Design Specific.

#set_false_path -from -to -setup

#set_false_path -from -to -hold

#set_multicycle_path -from -to

 

##### Steps to constrain the inputs/outputs and the design

set_input_transition $clock1_period_onetenth [all_inputs]

set_max_transition $clock1_period_onetwenth $current_design

#### Specify the wire-load model

set auto_wire_load_selection true ### Tool automatically selects the wire-load model

#### Create virtual clocks to constrain the ports.To understand concept behind the virtual clocks

#### Check out the ASIC FAQ's column.

#### To constrain inputs

set_input_delay -clock -clock -clock -clock

### Similar way define for all the inputs and w.r.t virtual clocks

#### To constrain out-puts

set_output_delay -clock

### Similar way define for all the outputs and w.r.t virtual clocks

35. What are the various ways to reduce Clock Insertion Delay in the Design

 

1. Number of Clock sinks2. Balancing two different clock frequencies3. Placement of clock sinks.4. Placement of Clock gating cells5. Clock tree buffers/inverters drive strength's6. Clock Transition 7. placement of Clockgating cells and the clock sinks8. Combinationals cells in the path of clocks (say clock dividers, muxes, clockgates) ... 

36. what are the various functional verification methodologies•TLM(Transaction Level Modelling)•Linting•RTL Simulation ( Enivronment involving : stimulus generators, monitors, response checkers, transactors)•Gate level Simulation•Mixed-signal simulations•Regression

36. What does formal verification mean?

Formal verification uses Mathematical techniquest by prooving the design through assertions or properties. Correctness of the design can be achieved through assertions with out the necessity for simulations. The methods of formal verification are 1. Equivalence checking In this method of checking the designs are compared based on mathematical equations and compared whether they are equal or not .

•Original RTL vs Modified RTL•RTL vs Netlist•Golden Netlist vs Modified/Edited Netlist•Synthesis Netlist vs Place and route NetlistRemember : Formal verification doesnt check for functionality of the RTL code. It will be only checking the equivalence.

2. Model checking Property specification languages like PSL or SVA, are formally analyzed to see if they are always true for a design. This can exhaustively prove if a property is correct, but does tend to suffer from state-space explosion: the time to analyse a design is directly propotional to the amount of states.

37. How will you time the output paths?

38. How will you time the input paths?

39. what is false path mean in STA and in what scenarios falsepath can come?

40. what does Multicycle path mean in STA and in what scenarios multicycle paths can come?

http://www.vlsichipdesign.com/images/timing_paths_multicycle_path.gif

41. what are source synchronous paths in STA?

42. assume you have defined latency specified by user both in Master clock and in the Generated clock in STA, how the tool will behave any idea?

If we have defined only Master latency and Generated clock with latency numbers, and the clocks are set to propagated mode after clock-tree, then the Static Timing Analysis Tool, will honour the Generated clock source and Generated clock network latency numbers only and the master clock source and master clock network latencies are ignored.

43. Assume there is a specific requirement to preserve the logic during synthesis, how will do it.

If there is a requirement that some logic needs to be preserved then we can use a command called set_dont_touch or set_dont_design (complete module) and convey the message to the tool not to optimize or smash the logic.

44. We have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage?

While writing RTL(Register Transfer language),say in verilog or in VHDL language, we dont write the same module functionality again and again, we use a concept called as instantiation, where in as per the language, the instanciation of a module will behave like the parent module in terms of functionality, where during synthesis stage we need the full code so that the synthesis tool can study the logic , structure and map it to the library cells, so we

use a command in synthesis , called as "UNIQUIFY" which will replace the instantiations with the real logic, because once we are in a synthesis stages we have to visualize as real cells and no more modelling just for functionality alone, we need to visualize in-terms of physical world as well.

45. what do you call an event and when do you call an assertion?

Assertion based Verification Tools, checks whether a statement holds a defined property or not, whereas, Event based Simulators, checks whether there is change in any event, say for every edge of a clockwhether there is some activity in a signal or not, in case of an asynchronous designs, checks whether a signal is enabled or not.

44. We have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage?

While writing RTL(Register Transfer language),say in verilog or in VHDL language, we dont write the same module functionality again and again, we use a concept called as instantiation, where in as per the language, the instanciation of a module will behave like the parent module in terms of functionality, where during synthesis stage we need the full code so that the synthesis tool can study the logic , structure and map it to the library cells, so we use a command in synthesis , called as "UNIQUIFY" which will replace the instantiations with the real logic, because once we are in a synthesis stages we have to visualize as real cells and no more modelling just for functionality alone, we need to visualize in-terms of physical world as well.

45. what do you call an event and when do you call an assertion?

Assertion based Verification Tools, checks whether a statement holds a defined property or not, whereas, Event based Simulators, checks whether there is change in any event, say for every edge of a clockwhether there is some activity in a signal or not, in case of an asynchronous designs, checks whether a signal is enabled or not.

44. We have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage?

While writing RTL(Register Transfer language),say in verilog or in VHDL language, we dont write the same module functionality again and again, we use a concept called as instantiation, where in as per the language, the instanciation of a module will behave like the parent module in terms of functionality, where during synthesis stage we need the full code so that the synthesis tool can study the logic , structure and map it to the library cells, so we use a command in synthesis , called as "UNIQUIFY" which will replace the instantiations with the real logic, because once we are in a synthesis stages we have to visualize as real cells and no more modelling just for functionality alone, we need to visualize in-terms of physical world as well.

45. what do you call an event and when do you call an assertion?

Assertion based Verification Tools, checks whether a statement holds a defined property or not, whereas, Event based Simulators, checks whether there is change in any event, say for every edge of a clockwhether there is some activity in a signal or not, in case of an asynchronous designs, checks whether a signal is enabled or not.

clock uncertainityLet me try to clear up some of the confusing terminology - clear terminology allows for clear thinking.

The first important point is that there are two phases in the design of a clock signal. At first the clock is in "ideal mode" (e.g.: during RTL design, during synthesis and during placement). An "ideal" clock has no physical distribution tree, it just shows up magically on time at all the clock pins.The second phase comes when clock tree synthesis (CTS) inserts an actual tree of buffers into the design that carries the clock signal from the clock source pin to the (thousands) of flip-flops that need to get it. CTS is done after placement and before routing. After CTS is finished, the clock is said to be in "propagated mode".

Now we can get to your questions:

What is clock latency? Clock latency is an ideal mode term. It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin. This is a delay specified by the user - not a real, measured thing. (In fact there is 'clock source latency' and 'clock network latency' - the difference is not important for this discussion). When the clock is actually created, then that same delay is now referred to as the "insertion delay". Insertion delay (ID) is a real, measurable delay path through a tree of buffers. Sometimes the clock latency is interpreted as a desired target value for the insertion delay.

What is clock uncertainty? In ideal mode the clock signal can arrive at all clock pins simultaneously. But in fact, that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty. For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps. A deeper question gets into *why* the clock does not always arrive exactly one clock period later. There are several possible reasons but I will list 3 major ones:(a) The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.(b) The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.(c) Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.

Re: about clock skew?Ans to What is Clock Skew ?--In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times.

--ans from wiki.

However, purposely skewing  clock arrivals to produce useful skew can achieve timing closure and reduce area at the same time.

And finally leave most part of these jobs to beckend tools .

Clock tree is needed to ensure that the clock signal (from the clock source to logic cells) are synchronised at the same time with the same clock delay.

Clock skew is the variation of arrival time (of the clock signal) to the destination logic cell using the same clock source. Clock skew is due to (1) variation in the RC of the clock interconnect due to the geometrical layout of the length and width, (2) process variation in permittivity and thickness (due to the actual fabrication of the interconnect), thus causes imperfection.

To improve clock skew, 1. Use clock tree, with branches as short as possible to reduce R and C, and using wider width for the higher branches closer to the clock source. 2. Use a DLL (delay lock loop).3. Avoid using clock interconnect over many layers. Try to design the clock interconnect on the same metal layer or within 2 layers in order to reduce vertical resistance due to vias, which is highly resistive.

Maximum insertion delay = setup time + hold time + maximum propagation delay of the logic cell + maximum time of flight (propagation delay of the interconnect)

To improve max insertion delay, 1. Reduce maximum time of flight2. Reduce propagation delay of logic cell3. Reduce critical path in the logic cell4. Alternatively, expand maximum insertion delay by re-timing.

why clock tree needed in synchronous asic design? ----------------------------------------------------------two reasons:1. to maintain a reasonable rising time of the clock signal2. to help reduce clock skew

what is clock skew? ----------------------------------------------------------clock skew is the the difference of clock arriving time at the DFF's clock pin

how to improve clock skew? --------------------------------use a clock tree

what is max insertion delay? ---------------------------------max insertion delay is the longest delay from the clock source point to the DFF clock pin in a clock network

how to improve max insertion delay?------------------------------------------max insertion delay depends on several facts,1. the number of DFFs the clock is driving2. the die area the DFFs scatteredto reduce masx insertion delay, you need to reduce the area, minizie the number of DFFs that driven by a single clock, this may lead to changing your clocking strategy.

Hi tachyons,

Prior to CTS the design should be

1. Placement completed2. Power and ground nets should be routed

3. Congestion and timing analysis should give acceptable results4. No cap/tran violations5. HFNS completed6. All clocks are defined and No propagated clocks

For skew/latency numbers

the tool calculates the skew values by comparing the arrival times of the clock signals in a clock domain..if you do not specify max skew it will be considered as "0".Similarly the insertion delay will be checked after synthesizing the initial clock tree to meet the min value if not buffers will be inserted to meet the value.Default is "0".Balancing of Skew is the most important metric for qualifying CTS

What is Body effect ?

The threshold voltage of a MOSFET is affected by the voltage which is applied to the back contact. The voltage difference between the source and the bulk, VBS changes the width of the depletion layer and therefore also the voltage across the oxide due to the change of the charge in the depletion region. This results in a difference in threshold voltage which equals the difference in charge in the depletion region divided by the oxide capacitance, yielding:.

Click hear to view more 

 

What are standard Cell's? 

In semiconductor design, standard cell methodology is a method of designing Application Specific Integrated Circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level VLSI-layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology (the general class that standard-cell belongs to) makes it possible for one designer to focus on the high-level (logical function) aspect of digital-design, while another designer focused on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology was responsible for allowing designers to scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate devices (SoC). 

Click hear to view more 

 

What are Design Rule Check (DRC) and Layout Vs Schematic (LVS) ? 

Design Rule Check (DRC) and Layout Vs Schematic (LVS) are verification processes. Reliable device fabrication at modern deep submicrometre (0.13 µm and below) requires strict observance of transistor spacing, metal layer thickness, and power density rules. DRC exhaustively compares the physical netlist against a set of "foundry design rules" (from the foundry operator), then flags any observed violations. LVS is a process that confirms that the layout has the same structure as the associated schematic; this is typically the final step in the layout process. The LVS tool takes as an input a schematic diagram and the extracted view from a layout. It then generates a netlist from

each one and compares them. Nodes, ports, and device sizing are all compared. If they are the same, LVS passes and the designer can continue. Note: LVS tends to consider transistor fingers to be the same as an extra-wide transistor. For example, 4 transistors in parallel (each 1 um wide), a 4-finger 1 um transistor, and a 4 um transistor are all seen as the same by the LVS tool. Functionality of .lib files will be taken from spice models and added as an attribute to the .lib file. 

What is Antenna effect ? 

The antenna effect, more formally plasma induced gate oxide damage, is an efffect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. Fabs normally supply antenna rules, which are rules that must be obeyed to avoid this problem. A violation of such rules is called an antenna violation. The word antenna is somewhat of a misnomer in this context—the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents. Occasionally the phrase antenna effect is used this context[6] but this is less common since there are many effects[7] and the phrase does not make clear which is meant. 

What are steps involved in Semiconductor device fabrication ? 

This is a list of processing techniques that are employed numerous times in a modern electronic device and do not necessarily imply a specific order. 

Wafer processing Wet cleans Photolithography Ion implantation (in which dopants are embedded in the wafer creating regions of increased (or decreased) conductivity) Dry etching Wet etching Plasma ashing Thermal treatments Rapid thermal anneal Furnace anneals Thermal oxidation Chemical vapor deposition (CVD) Physical vapor deposition (PVD) Molecular beam epitaxy (MBE) Electrochemical Deposition (ECD). See Electroplating Chemical-mechanical planarization (CMP) Wafer testing (where the electrical performance is verified) Wafer backgrinding (to reduce the thickness of the wafer so the resulting chip can be put into a thin device like a smartcard or PCMCIA card.) Die preparation Wafer mounting Die cutting IC packaging Die attachment IC Bonding Wire bonding Flip chip Tab bonding IC encapsulation 

Baking Plating Lasermarking Trim and form IC testing 

What is Clock distribution network ? 

In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. The clock distribution network distributes the clock signal(s) from a common point to all the elements that need it. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the electrical networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.Clock signals are typically loaded with the greatest fanout, travel over the greatest distances, and operate at the highest speeds of any signal, either control or data, within the entire synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling (see Moore's law), in that long global interconnect lines become significantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register. The clock distribution network often takes a significant fraction of the power consumed by a chip. Furthermore, significant power can be wasted in transitions within blocks, even when their output is not needed. These observations have lead to a power saving technique called clock gating, which involves adding logic gates to the clock distribution tree, so portions of the tree can be turned off when not needed.

What is Clock Gating ? 

Clock gating is one of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor. To save power, clock gating refers to adding additional logic to a circuit to prune the clock tree, thus disabling portions of the circuitry where flip flops do not change state. Although asynchronous circuits by definition do not have a "clock", the term "perfect clock gating" is used to illustrate how various clock gating techniques are simply approximations of the data-dependent behavior exhibited by asynchronous circuitry, and that as the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit.

What is Netlist ? 

Netlists are connectivity information and provide nothing more than instances, nets, and perhaps some attributes. If they express much more than this, they are usually considered to be a hardware description language such as Verilog, VHDL, or any one of several specific languages designed for input to simulators. Most netlists either contain or refer to descriptions of the parts or devices used. Each time a part is used in a netlist, this is called an "instance." Thus, each instance has a "master", or "definition". These definitions will usually list the connections that can be made to that kind of device, and some basic properties of that device. These connection points are called "ports" or "pins", among several other names. 

An "instance" could be anything from a vacuum cleaner, microwave oven, or light bulb, to a resistor, capacitor, or integrated circuit chip. Instances have "ports". In the case of a vacuum cleaner, these ports would be the three metal prongs in the plug. Each port has a name, and in continuing the vacuum cleaner example, they might be "Neutral", "Live" and "Ground". Usually, each instance will have a unique name, so that if you have two instances of vacuum cleaners, one might be "vac1" and the other "vac2". Besides their names, they might otherwise be identical. Nets are the "wires" that connect things together in the circuit. There may or may not be any special attributes associated with the nets in a design, depending on the particular language the netlist is written in, and that language's features. Instance based netlists usually provide a list of the instances used in a design. Along with each instance, either an ordered list of net names are provided, or a list of pairs provided, of an instance port name, along with the net name to which that port is connected. In this kind of description, the list of nets can be gathered from the connection lists, and there is no place to associate particular attributes with the nets themselves. SPICE is perhaps the most famous of instance-based netlists. Net-based netlists usually describe all the instances and their attributes, then describe each net, and say which port they are connected on each instance. This allows for attributes to be associated with nets. EDIF is probably the most famous of the net-based netlists. 

What Physical timing closure ? 

Physical timing closure is the process by which an FPGA or a VLSI design with a physical representation is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer. The term is also sometimes used as a characteristic, which is ascribed to an EDA tool, when it provides most of the features required in this process. Physical timing closure became more important with submicrometre technologies, as more and more steps of the design flow had to be made timing-aware. Previously only logic synthesis had to satisfy timing requirements. With present deep submicrometre technologies it is unthinkable to perform any of the design steps of placement, clock-tree synthesis and routing without timing constraints. Logic synthesis with these technologies is becoming less important. It is still required, as it provides the initial netlist of gates for the placement step, but the timing requirements do not need to be strictly satisfied any more. When a physical representation of the circuit is available, the modifications required to achieve timing closure are carried out by using more accurate estimations of the delays.

What Physical verification ? 

Physical verification of the design, involves DRC(Design rule check), LVS(Layout versus schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks.XOR Check

This step involves comparing two layout databases/GDS by XOR operation of the layout geometries. This check results a database which has all the mismatching geometries in both the layouts. This check is typically run after a metal spin, where in the re-spin database/GDS is compared with the previously taped out database/GDS.Antenna Check

Antenna checks are used to limit the damage of the thin gate oxide during the manufacturing process due to charge accumulation on the interconnect layers (metal, polysilicon) during certain fabrication steps like Plasma etching, which creates highly ionized matter to etch. The antenna basically is a metal interconnect, i.e., a conductor like polysilicon or metal, that is not electrically connected to silicon or grounded, during the processing steps of the wafer. If the connection to

silicon does not exist, charges may build up on the interconnect to the point at which rapid discharge does take place and permanent physical damage results to thin transistor gate oxide. This rapid and destructive phenomenon is known as the antenna effect. The Antenna ratio is defined as the ratio between the physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected.ERC (Electrical rule check)

ERC (Electrical rule check) involves checking a design for all well and substrate areas for proper contacts and spacings thereby ensuring correct power and ground connections. ERC steps can also involve checks for unconnected inputs or shorted outputs. 

What is Stuck-at fault ? 

A Stuck-at fault is a particular fault model used by fault simulators and Automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an output is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the output could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin. 

What is Different Logic family ? 

Listed here in rough chronological order of introduction along with their usual abbreviations of Logic family* Diode logic (DL)* Direct-coupled transistor logic (DCTL)* Complementary transistor logic (CTL)* Resistor-transistor logic (RTL)* Resistor-capacitor transistor logic (RCTL)* Diode-transistor logic (DTL)* Emitter coupled logic (ECL) also known as Current-mode logic (CML)* Transistor-transistor logic (TTL) and variants* P-type Metal Oxide Semiconductor logic (PMOS)* N-type Metal Oxide Semiconductor logic (NMOS)* Complementary Metal-Oxide Semiconductor logic (CMOS)* Bipolar Complementary Metal-Oxide Semiconductor logic (BiCMOS)* Integrated Injection Logic (I2L)

What is Different Types of IC packaging ? 

IC are packaged in many types they are: * BGA1* BGA2* Ball grid array* CPGA* Ceramic ball grid array* Cerquad* DIP-8* Die attachment* Dual Flat No Lead* Dual in-line package* Flat pack* Flip chip

* Flip-chip pin grid array* HVQFN* LQFP* Land grid array* Leadless chip carrier* Low insertion force* Micro FCBGA* Micro Leadframe Package* MicroLeadFrame* Mini-Cartridge* Multi-Chip Module* OPGA* PQFP* Package on package* Pin grid array* Plastic leaded chip carrier* QFN* QFP* Quadruple in-line package* ROM cartridge* Shrink Small-Outline Package* Single in-line package* Small-Outline Integrated Circuit* Staggered Pin Grid Array* Surface-mount technology* TO220* TO3* TO92* TQFP* TSSOP* Thin small-outline package* Through-hole technology* UICC* Zig-zag in-line package

What is Substrate coupling ? 

In an integrated circuit, a signal can couple from one node to another via the substrate. This phenomenon is referred to as substrate coupling or substrate noise coupling.The push for reduced cost, more compact circuit boards, and added customer features has provided incentives for the inclusion of analog functions on primarily digital MOS integrated circuits (ICs) forming mixed-signal ICs. In these systems, the speed of digital circuits is constantly increasing, chips are becoming more densely packed, interconnect layers are added, and analog resolution is increased. In addition, recent increase in wireless applications and its growing market are introducing a new set of aggressive design goals for realizing mixed-signal systems. Here, the designer integrates radio frequency (RF) analog and base band digital circuitry on a single chip. The goal is to make single-chip radio frequency integrated circuits (RFICs) on silicon, where all the blocks are fabricated on the same chip. One of the advantages of this integration is low power dissipation for portability due to a reduction in the number of package pins and associated bond wire capacitance. Another reason that an integrated solution offers lower power consumption is that routing high-frequency signals off-chip often requires a 50O impedance match, which can result in higher power dissipation. Other advantages include improved high-frequency performance due to

reduced package interconnect parasitics, higher system reliability, smaller package count, smaller package interconnect parasitics, and higher integration of RF components with VLSI-compatible digital circuits. In fact, the single-chip transceiver is now a reality. 

What is Latchup ? 

A latchup is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure, which then acts as a short circuit, disrupting proper functioning of the part and possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation. The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. During a latchup when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates. 

Q1.How do we know, if given a circuit, whether it is a Combinational Circuit or a Sequential Circuit?

[Ans]  If a circuit has only combinational devices (e.g.. gates like AND, OR etc and MUX(s))and no Memory elements then it is a Combinational circuit. If the circuit has memory elements such as Flip Flops, Registers, Counters, or other state devices then it is a Sequential Circuit.  Synchronous sequential circuits will also have a clearly labeled clock input.

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Q2. Are the following circuits combinational or sequential?

[Ans]

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Q3. Why do we have to identify the type of circuit? Does it really matter?

[Ans]  It is important to identify the type of circuit because our timing calculation approach differs accordingly. Combinational circuits timing analysis deals primarily with propagation delay issues. Sequential circuits have additional specific timing characteristics that must be satisfied in order to prevent metastability, including setup time, hold time, and minimum clock period. Designers of sequential devices must specify these important timing characteristics in order to allow the device to be used without error.

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Q4. Do all Digital Devices like gates and Flip Flops have timing parameters?

[Ans] Yes, all digital devices have timing parameters. In the real environment (not Ideal as in our lab) there will be a real (non zero) value associated with every digital device. Observe the examples below

Example 1 and 2:

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Q5.Phew!!! So many things all at the same time.....what is propagation delay?

[Ans] All devices have some delay associated with transferring an input change to the output. These changes are not immediate in a real environment. This delay that is due to the signal propagation through the device is called the propagation delay. 

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Q6. What is Setup time?

[Ans] Setup time is a timing parameter associated with Sequential Devices (for simplicity henceforth I will be only referring to the Flip Flop). The Setup time is used to meet the minimum pulse width requirement for the first (Master) latch makes up a flip flop is. More simply, the setup time is the amount of time that an input signal (to the device) must be stable (unchanging) before the clock ticks in order to guarantee minimum pulse width and thus avoid possible metastability.

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Q7. What is Hold time?

[Ans] Hold time is also a timing parameter associated with Flip Flops and all other sequential devices. The Hold time is used to further satisfy the minimum pulse width requirement for the first (Master) latch that makes up a flip flop. The input must not change until enough time has passed after the clock tick to guarantee the master latch is fully disabled. More simply, hold time  is the amount of time that an input signal (to a sequential device) must be stable (unchanging) after the clock tick in order to guarantee minimum pulse width and thus avoid possible metastability.

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Q8. Can you give an example that can help me better understand the Setup and Hold time concept?

[Ans] Lets consider the situation where-in I am the Flip Flop and I am to receive an Input (a photo of an old friend whom I have to recognize ) now the amount of time it would take to setup the photo in the right position so that it is visible to me from where I am sitting  (since I am lazy to walk over) can be considered as the "Setup time". Now once shown the photo the amount of time that I keep staring at it till I feel comfortable enough to start relating it to known faces can be considered as the "Hold time".

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Q9. What is a timing diagram? Can we use it to better understand Setup and Hold time?

[Ans] Timing diagram is a complete description of a digital machine. We can use the timing diagram (waveform) to illustrate Setup and Hold time. Observe the waveform given below:

 

From the timing diagram we observe that we have three signals: the Clock, the Flip Flop Input (D) and the Flip Flop output (Q). We have four timing instances and three time periods. The inferences from this waveform will help us understand the concept of propagation delay Setup and Hold time. 

(1) i.e. [t2 - t1] is the Setup Time: the minimum amount of time Input must be held constant BEFORE the clock tick. Note that D is actually held constant for somewhat longer than the minimum amount. The extra “constant” time is sometimes called the setup margin.

(2) i.e. [t3 - t2] is the Propagation delay of the Flip Flop: the minimum/maximum time for the input to propagate and influence the output.

(3) i.e. [t4 - t2] is the Hold time: the minimum amount of time the Input is held constant AFTER the clock tick. Note that Q is actually held constant for somewhat longer than the minimum amount. The extra “constant” time is sometimes called the hold margin.

(The above timing diagram has 2 clock cycles; the timing parameters for the second cycle will also be similar to that of the first cycle)

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PART 2: Equations

========================================================================

 This part of the tutorial introduces us to the various different timing calculations associated with this course. We may be given a sequential circuit and asked to solve for the timing parameters. Let us discuss in detail how we should approach such problems.

Q11. What is the first thing to do if given a sequential circuit and asked to analyze its timing?

[Ans] Given a sequential circuit it is often advisable to first divide the circuit in to three distinct parts i.e. Input Logic, State Memory and the Output Logic. Such division will also help with identifying whether the given circuit is Mealy or Moore.  The input logic (Next State Logic) and the output logic blocks constitute of only combinational logic components like gates, muxes etc. The state memory block is made of only sequential components like Flip Flops etc.

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Q12. Can you explain the answer to Q11 more elaborately?

[Ans] Let me explain using block diagrams. A given sequential circuit can be represented in either of the two ways as shown below.

The first representation shows the sequential circuit where the input(s) have to pass through the State memory to affect the output. Such machines are called Moore machines.

The second representation shows the ‘red bypass’ which signifies that the output can be directly affected by the inputs without having to pass through the state memory device(s). Such devices are called Mealy machines.

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Q13. Can you explain this with an example?

[Ans] Ok, consider the sequential circuit shown below

Let us now identify the three distinct parts in this given sequential circuit. Observe the division on the circuit below.

.

Observation: This given circuit is a MEALY machine.

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Q14. Now that we have divided the circuit into more distinct parts how do we proceed with calculating the timing parameters?

[Ans] Remember from our discussion in Part 1 of this tutorial we know that combinational devices and sequential devices have different timing parameters. Now that we have separated them both into separate blocks we can define them more clearly. To relate them to the blocks let us follow some convention (already discussed in part 1). Let us refer to the timing parameters for the input logic (also referred to as the next state logic) and output logic with the letter ‘F’ and ‘G’ respectively. Similarly, let us refer to all timing parameters associated with the State memory block with the letter ‘R’.

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Q15. What timing parameters are commonly used?

[Ans] The list of the timing parameters that you may be asked to calculate for a given sequential circuit is

1.           Propagation delay, Clock to Output (minimum)

2.           Propagation delay, Clock to Output (maximum)

3.           Propagation delay, Input to Output (minimum)

4.           Propagation delay, Input to Output (maximum)

5.           Setup Time (Data input before clock)

6.           Hold Time (Data input after clock)

7.           Maximum Clock rate (or its reciprocal, minimum clock period)

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Q16. How do we find the Propagation delay, Clock to Output?

[Ans] Propagation delay (PD) for the circuit can be calculated as the summation of all delays encountered from where the clock occurs to the output. In short, the delays of the State memory and the output logic.

PD Clock- Output  (min) = Rpd (min)  + Gpd (min)   

PD Clock- Output  (max) = Rpd (max)  + Gpd (max)---------------------------------------------------------------------------------------------------------------------------

Q17. How do we find the Propagation delay, Input to Output?

[Ans] This is a property associated with Mealy machines only. In other words, for a Moore machine the value for this timing parameter is infinity (∞). The calculation (for mealy machines) is the summation of all propagation delays encountered between the input (that influences the output by bypassing the state memory) and the output.

For   MOORE   machines:

PD  Input- Output  (min) = infinity (∞)

PD  Input- Output  (max) = infinity (∞)

For MEALY Machines

PD  Input- Output  (min) = Gpd (min)   

PD  Input- Output  (max) = Gpd (max)---------------------------------------------------------------------------------------------------------------------------

Q18. How do we calculate Setup time?

[Ans] The calculation for setup time is the sum of the setup time for the concerned flip flop and the maximum delay from the input logic.   

T SETUP = RSETUP+ Fpd (MAX)   ---------------------------------------------------------------------------------------------------------------------------

Q19. How do we get the value for the Hold time?

[Ans] The value for the Hold time can be obtained by the following formulae 

T HOLD = RHOLD  - Fpd (MIN)   The concern here is how soon (minimum time) an erroneous input can propagate in from the Input logic while the Flip Flop is attempting to hold on to a stable value. The negative sign can be associated with ‘after the clock occurs’ to ease in remembering this formulae.

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Q20. How do we calculate the Maximum Clock rate (MCLK)?

[Ans] Maximum clock rate is calculated using the formula

MCLK = 1/ TMIN 

So we will have to calculate TMIN  first. TMIN here refers to the minimum time period for correct operation of the circuit, so it is calculated using all worst cases (maximum delays).

TMIN =     Fpd (MAX)  + RSETUP  + Rpd (MAX)       

So having found the minimum clock period let us now calculate for the MCLK

MCLK = 1/ TMIN     = (Fpd (MAX)     + RSETUP  + Rpd (MAX)  )-1

       

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Q21. Please summarize.

[Ans] Ok, here is everything we discussed so far in Part 2

1.     PD Clock- Output  (min) = Rpd (min)  + Gpd (min)   

2.     PD Clock- Output  (max) = Rpd (max)  + Gpd (max)

3.     PD  Input- Output  (min) = infinity (∞) (For MOORE machines)

4.     PD  Input- Output  (max) = infinity (∞) (For MOORE machines)

5.     PD  Input- Output  (min) = Gpd (min) (For MEALY machines)

6.     PD  Input- Output  (max) = Gpd (max) (For MEALY machines)

7.     T SETUP = RSETUP+ Fpd (MAX)   

8.     T HOLD = RHOLD  - Fpd (MIN)   

9.     MCLK = 1/ TMIN     = (Fpd  (MAX)      + RSETUP + Rpd (MAX)  )-1

       

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PART 3:  Examples

========================================================================

Q23. Can we go through a timing example (solved problem) so that we can have a better understanding of the concepts dealt so far?

[Ans] Sure, here is a simple example to begin with, you are given a sequential circuit as shown below and asked to calculate all the timing parameters discussed in Part 2 of this tutorial. The information provided to you with the question is the individual timing parameters of the components listed in the table below.

Device Propagation Delay (Minimum)

Propagation Delay (Maximum) Setup Time Hold Time

D Flip Flop 4 ns 8 ns 10 ns 3 ns

NAND Gate 3 ns 6 ns X X

Bubbled AND Gate 2 ns 4 ns X X

With this information we can approach the problem as discussed in Part 2 of this tutorial i.e. we shall first divide the given circuit into three distinct parts and then solve for timing. With practice, we can afford to skip this step of dividing the circuit into distinct parts (thereby saving time) and directly solve for timing. Since this is the first example I shall religiously follow the steps discussed in Part 2.

Observation: This is a MEALY Machine.

 Now let us calculate for all the timing parameters.

1.       PD Clock- Output  (min) = Rpd (min) + Gpd (min)     = 4ns + 2ns = 6ns

2.       PD Clock- Output  (max) = Rpd (max)  + Gpd (max)   = 8ns + 4ns = 12ns

3.       PD  Input- Output  (min) = Gpd (min)   = 2ns

4.       PD  Input- Output  (max) = Gpd (max)   = 4ns

5.       T SETUP = RSETUP+ Fpd (MAX)   = 10ns + 6ns = 16ns

6.       T HOLD  = RHOLD  - Fpd (MIN)     = 3ns – 3ns = 0ns.   

7.       TMIN   = Fpd  (MAX)     + RSETUP  + Rpd (MAX)   = 6ns +10ns + 8ns = 24ns

8.       MCLK = 1/ TMIN    = (Fpd  (MAX)      + RSETUP + Rpd (MAX)  )-1

       = 1/24ns.

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Q24. Can we go through another timing example (solved problem) using more than one Flip Flop?

[Ans]   Ok, here is an example (notice how I write down the corresponding timing values for simplicity in understanding)

Given with the question is the individual timing parameter for all the components used in the Circuit. Observe the table given below.

Device Propagation Delay (minimum)

Propagation Delay (maximum) Setup Time Hold Time

D Flip Flop 2ns 6ns 4ns 2ns

AND Gate 2ns 4ns X X

2 i/p NOR Gate 2ns 3ns X X

OR Gate 2ns 3ns X X

3 i/p NOR Gate 1ns 2ns X X

Writing the timing parameters next to the components (for ease in solving)

  So with the timing parameters next to the components the circuit now looks like this

Dividing the circuit into distinct parts is left to the reader (will give the reader some hands-on practice)

Now let us calculate for all the timing parameters.

1.       PD Clock- Output  (min) = Rpd (min) + Gpd (min)     =  2ns + 1ns = 3ns

2.       PD Clock- Output  (max) = Rpd (max)  + Gpd (max)   = 6ns + 3ns + 2ns = 11ns

3.       PD  Input- Output  (min) = Gpd (min) (For MEALY machines)   = 1ns

4.       PD  Input- Output  (max) = Gpd (max) (For MEALY machines) = 2ns

5.       T SETUP = RSETUP+ Fpd (MAX)   = 4ns + 4ns = 8ns

6.       T HOLD  = RHOLD  - Fpd (MIN)     = 2ns – 2ns = 0ns.   

7.       TMIN   = Fpd  (MAX)     + RSETUP  + Rpd (MAX)   = 3ns + 4ns + 4ns + 6ns = 17ns

8.       MCLK = 1/ TMIN    = (Fpd  (MAX)      + RSETUP + Rpd (MAX)  )-1

       = 1/17ns.

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Q25. Are these two solved examples enough to introduce us to the timing concepts necessary for this course?

[Ans] Absolutely, the two examples together cover almost all the concepts necessary to get you started with understanding timing problems (the intent of this tutorial). More examples would result in spoon-feeding and would not be recommended. Interested students can now read the text and attempt to solve other timing related questions for practice.

What is FPGA ?

A field-programmable gate array is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. Logic blocks and interconnects can be programmed by the customer or designer, after the FPGA is manufactured, to implement any logical function—hence the name "field-programmable". FPGAs are usually slower than their application-specific integrated circuit (ASIC) counterparts, cannot handle as complex a design, and draw more power (for any given semiconductor process). But their advantages include a shorter time to market, ability to re-program in the field to fix bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less flexible versions of their FPGAs which cannot be modified after the design is committed. The designs are developed on regular FPGAs and then migrated into a fixed version that more resembles an ASIC. 

What logic is inferred when there are multiple assign statements targeting the same wire?

 

It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one source.However, it is legal to drive a three-state wire by multiple assign statements. 

What do conditional assignments get inferred into?

Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals get inferred into a multiplexor. For example, the following is the code for a simple multiplexor

assign wire1 = (sel==1'b1) ? a : b; 

 

What value is inferred when multiple procedural assignments made to the same reg variable in an always block?

When there are multiple nonblocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up for logic synthesis. For example 

always @ (posedge clk) beginout <= in1^in2;out <= in1 &in2;out <= in1|in2;

 

In the example just shown, it is the OR logic that is the last assignment. Hence, the logic synthesized was indeed the OR gate. Had the last assignment been the “&” operator, it would have synthesized an AND gate. 

1) What is minimum and maximum frequency of dcm in spartan-3 series fpga? 

Spartan series dcm’s have a minimum frequency of 24 MHZ and a maximum of 248 

2)Tell me some of constraints you used and their purpose during your design? 

There are lot of constraints and will vary for tool to tool ,I am listing some of Xilinx constraints a) Translate on and Translate off: the Verilog code between Translate on and Translate off is ignored for synthesis. b) CLOCK_SIGNAL: is a synthesis constraint. In the case where a clock signal goes through combinatorial logic before being connected to the clock input of a flip-flop, XST cannot identify what input pin or internal net is the real clock signal. This constraint allows you to define the clock

net. c) XOR_COLLAPSE: is synthesis constraint. It controls whether cascaded XORs should be collapsed into a single XOR. For more constraints detailed description refer to constraint guide. 

3) Suppose for a piece of code equivalent gate count is 600 and for another code equivalent gate count is 50,000 will the size of bitmap change?in other words will size of bitmap change it gate count change? 

The size of bitmap is irrespective of resource utilization, it is always the same,for Spartan xc3s5000 it is 1.56MB and will never change. 

4) What are different types of FPGA programming modes?what are you currently using ?how to change from one to another? 

Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes Mode selecting pins can be set to select the mode, refer data sheet for further details. 

5) Tell me some of features of FPGA you are currently using? 

I am taking example of xc3s5000 to answering the question . 

Very low cost, high-performance logic solution forhigh-volume, consumer-oriented applications- Densities as high as 74,880 logic cells- Up to 784 I/O pins- 622 Mb/s data transfer rate per I/O- 18 single-ended signal standards- 6 differential I/O standards including LVDS, RSDS- Termination by Digitally Controlled Impedance- Signal swing ranging from 1.14V to 3.45V- Double Data Rate (DDR) support• Logic resources- Abundant logic cells with shift register capability- Wide multiplexers- Fast look-ahead carry logic- Dedicated 18 x 18 multipliers- Up to 1,872 Kbits of total block RAM- Up to 520 Kbits of total distributed RAM• Digital Clock Manager (up to four DCMs)- Clock skew elimination• Eight global clock lines and abundant routing

6) What is gate count of your project? 

Well mine was 3.2 million, I don’t know yours.! 

7) Can you list out some of synthesizable and non synthesizable constructs? 

not synthesizable->>>>initial ignored for synthesis.delays ignored for synthesis.events not supported.real Real data type not supported.time Time data type not supported.force and release Force and release of data types not supported.fork join Use nonblocking assignments to get same effect.user defined primitives Only gate level primitives are supported.

synthesizable constructs->>assign,for loop,Gate Level Primitives,repeat with constant value...

8)Can you explain what struck at zero means? 

These stuck-at problems will appear in ASIC. Some times, the nodes will permanently tie to 1 or 0 because of some fault. To avoid that, we need to provide testability in RTL. If it is permanently 1 it is called stuck-at-1 If it is permanently 0 it is called stuck-at-0. 

9) Can you draw general structure of fpga? 

 

10) Difference between FPGA and CPLD? 

FPGA:

a)SRAM based technology.b)Segmented connection between elements.c)Usually used for complex logic circuits.d)Must be reprogrammed once the power is off.e)Costly

CPLD:a)Flash or EPROM based technology.b)Continuous connection between elements.c)Usually used for simpler or moderately complex logic circuits.d)Need not be reprogrammed once the power is off.e)Cheaper 

11) What are dcm's?why they are used? 

Digital clock manager (DCM) is a fully digital control system thatuses feedback to maintain clock signal characteristics with ahigh degree of precision despite normal variations in operatingtemperature and voltage. That is clock output of DCM is stable over wide range of temperature and voltage , and also skew associated with DCM is minimal and all phases of input clock can be obtained . The output of DCM coming form global buffer can handle more load. 

12) FPGA design flow? 

 

Also,Please refer to presentation section synthesis ppt on this site. 

13)what is slice,clb,lut?

I am taking example of xc3s500 to answer this question 

The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. CLB are configurable logic blocks and can be configured to combo,ram or rom depending on

coding styleCLB consist of 4 slices and each slice consist of two 4-input LUT (look up table) F-LUT and G-LUT.

14) Can a clb configured as ram? 

YES.

The memory assignment is a clocked behavioral assignment, Reads from the memory are asynchronous, And all the address lines are shared by the read and write statements. 

15)What is purpose of a constraint file what is its extension? 

The UCF file is an ASCII file specifying constraints on the logical design. You create this file and enter your constraints in the file with a text editor. You can also use the Xilinx Constraints Editor to create constraints within a UCF(extention) file. These constraints affect how the logical design is implemented in the target device. You can use the file to override constraints specified during design entry. 

16) What is FPGA you are currently using and some of main reasons for choosing it? 

17) Draw a rough diagram of how clock is routed through out FPGA? 

 

18) How many global buffers are there in your current fpga,what is their significance? 

There are 8 of them in xc3s5000 An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the global clock network or an Input Buffer (IBUF). Clock signals within the FPGA drive a global clock net using a Global Clock Multiplexer Buffer (BUFGMUX). The global clock net connects directly to the CLKIN input. 

19) What is frequency of operation and equivalent gate count of u r project? 

20)Tell me some of timing constraints you have used? 

21)Why is map-timing option used? 

Timing-driven packing and placement is recommended to improve design performance, timing, and packing for highly utilized designs.

22)What are different types of timing verifications? 

Dynamic timing:a. The design is simulated in full timing mode.b. Not all possibilities tested as it is dependent on the input test vectors.c. Simulations in full timing mode are slow and require a lot of memory.d. Best method to check asynchronous interfaces or interfaces between different timing domains.Static timing:a. The delays over all paths are added up.b. All possibilities, including false paths, verified without the need for test vectors.c. Much faster than simulations, hours as opposed to days.d. Not good with asynchronous interfaces or interfaces between different timing domains.

23) Compare PLL & DLL ? 

PLL:PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high performance and high reliability are required. The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply voltage, and manufacturing process affect the stability and operating performance of PLLs.

DLLs, however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to the feedback pin of the DLL.The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the clock skew are reduced to zero.Advantages:· precision· stability· power management· noise sensitivity· jitter performance.

24) Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work together without modifying the design?

Slow the clock down on the one with setup violations..And add redundant logic in the path where you have hold violations.

25)Suggest some ways to increase clock frequency?

· Check critical path and optimize it.· Add more timing constraints (over constrain).· pipeline the architecture to the max possible extent keeping in mind latency req's. 

26)What is the purpose of DRC? 

DRC is used to check whether the particular schematic and corresponding layout(especially the mask sets involved) cater to a pre-defined rule set depending on the technology used to design. They are parameters set aside by the concerned semiconductor manufacturer with respect to how the masks should be placed , connected , routed keeping in mind that variations in the fab process does not effect normal functionality. It usually denotes the minimum allowable configuration. 

27)What is LVs and why do we do that. What is the difference between LVS and DRC? 

The layout must be drawn according to certain strict design rules. DRC helps in layout of the designs by checking if the layout is abide by those rules.After the layout is complete we extract the netlist. LVS compares the netlist extracted from the layout with the schematic to ensure that the layout is an identical match to the cell schematic. 

28)What is DFT ? 

DFT means design for testability. 'Design for Test or Testability' - a methodology that ensures a design works properly after manufacturing, which later facilitates the failure analysis and false product/piece detectionOther than the functional logic,you need to add some DFT logic in your design.This will help you in testing the chip for manufacturing defects after it come from fab. Scan,MBIST,LBIST,IDDQ testing etc are all part of this. (this is a hot field and with lots of opportunities) 

29) There are two major FPGA companies: Xilinx and Altera. Xilinx tends to promote its hard processor cores and Altera tends to promote its soft processor cores. What is the difference between a hard processor core and a soft processor core? 

A hard processor core is a pre-designed block that is embedded onto the device. In the Xilinx Virtex II-Pro, some of the logic blocks have been removed, and the space that was used for these logic blocks is used to implement a processor. The Altera Nios, on the other hand, is a design that can be compiled to the normal FPGA logic. 

30)What is the significance of contamination delay in sequential circuit timing? 

Look at the figure below. tcd is the contamination delay. 

 

Contamination delay tells you if you meet the hold time of a flip flop. To understand this better please look at the sequential circuit below. 

 

The contamination delay of the data path in a sequential circuit is critical for the hold time at the flip flop where it is exiting, in this case R2.mathematically, th(R2) <= tcd(R1) + tcd(CL2)Contamination delay is also called tmin and Propagation delay is also called tmax in many data sheets. 

31)When are DFT and Formal verification used? 

DFT:· manufacturing defects like stuck at "0" or "1".· test for set of rules followed during the initial design stage.

Formal verification:· Verification of the operation of the design, i.e, to see if the design follows spec.· gate netlist == RTL ?· using mathematics and statistical analysis to check for equivalence.

32)What is Synthesis?

Synthesis is the stage in the design flow which is concerned with translating your Verilog code into

gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor. 

33)We need to sample an input or output something at different rates, but I need to vary the rate? What's a clean way to do this?

Many, many problems have this sort of variable rate requirement, yet we are usually constrained with a constant clock frequency. One trick is to implement a digital NCO (Numerically Controlled Oscillator). An NCO is actually very simple and, while it is most naturally understood as hardware, it also can be constructed in software. The NCO, quite simply, is an accumulator where you keep adding a fixed value on every clock (e.g. at a constant clock frequency). When the NCO "wraps", you sample your input or do your action. By adjusting the value added to the accumulator each clock, you finely tune the AVERAGE frequency of that wrap event. Now - you may have realized that the wrapping event may have lots of jitter on it. True, but you may use the wrap to increment yet another counter where each additional Divide-by-2 bit reduces this jitter. The DDS is a related technique. I have two examples showing both an NCOs and a DDS in my File Archive. This is tricky to grasp at first, but tremendously powerful once you have it in your bag of tricks. NCOs also relate to digital PLLs, Timing Recovery, TDMA and other "variable rate" phenomena 

1) What is latch up?

 

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS) . 

2)Why is NAND gate preferred over NOR gate for fabrication?

 

NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate.Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance p mos's are in series connection which again increases the resistance).

3)What is Noise Margin? Explain the procedure to determine Noise Margin

The minimum amount of noise that can be allowed on the input stage for which the output will not be effected. 

4)Explain sizing of the inverter?

In order to drive the desired load capacitance we have to increase the size (width) of the inverters to get an optimized performance. 

5) How do you size NMOS and PMOS transistors to increase the threshold voltage? 

6) What is Noise Margin? Explain the procedure to determine Noise Margin? 

The minimum amount of noise that can be allowed on the input stage for which the output will not be effected. 

7) What happens to delay if you increase load capacitance?

delay increases. 

8)What happens to delay if we include a resistance at the output of a CMOS circuit? 

Increases. (RC delay) 

9)What are the limitations in increasing the power supply to reduce delay? 

The delay can be reduced by increasing the power supply but if we do so the heating effect comes because of excessive power, to compensate this we have to increase the die size which is not practical. 

10)How does Resistance of the metal lines vary with increasing thickness and increasing length? 

R = ( *l) / A. 

11)For CMOS logic, give the various techniques you know to minimize power consumption? 

Power dissipation=CV2f ,from this minimize the load capacitance, dc voltage and the operating frequency. 

12) What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus? 

In the serially connected NMOS logic the input capacitance of each gate shares the charge with the load capacitance by which the logical levels drastically mismatched than that of the desired once. To eliminate this load capacitance must be very high compared to the input capacitance of the gates (approximately 10 times). 

13)Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? 

Because it can not drive the output load straight away, so we gradually increase the size to get an optimized performance. 

14)What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up? 

Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance conducting path between VDD and VSS with Disastrous results. 

15) Give the expression for CMOS switching power dissipation? 

CV2 

16) What is Body Effect?

In general multiple MOS devices are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However while connecting the devices serially this may result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1. 

17) Why is the substrate in NMOS connected to Ground and in PMOS to VDD? 

we try to reverse bias not the channel and the substrate but we try to maintain the drain,source junctions reverse biased with respect to the substrate so that we dont loose our current into the substrate. 

18) What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device. 

19)Which transistor has higher gain. BJT or MOS and why? 

BJT has higher gain because it has higher transconductance.This is because the current in BJT is exponentially dependent on input where as in MOSFET it is square law. 

20)Why do we gradually increase the size of inverters in buffer design when trying to drive a high capacitive load? Why not give the output of a circuit to one large inverter? 

We cannot use a big inverter to drive a large output capacitance because, who will drive the big inverter? The signal that has to drive the output cap will now see a larger gate capacitance of the BIG inverter.So this results in slow raise or fall times .A unit inverter can drive approximately an inverter thats 4 times bigger in size. So say we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a same ratio of output to input cap. This is the prime reason behind going for progressive sizing. 

21)In CMOS technology, in digital design, why do we design the size of pmos to be higher than the nmos.What determines the size of pmos wrt nmos. Though this is a simple question try to list all the reasons possible? 

In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos helps in pulling down the output to ground ann PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for the output node.

22)Why PMOS and NMOS are sized equally in a Transmission Gates? 

In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's the reason why we need not size them like in CMOS. In CMOS design we have NMOS and PMOS competing which is the reason we try to size them proportional to their mobility. 

23)All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged with one another in an inverter? 

I have seen similar Qs in some of the discussions. If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1 O/P will be degraded 1 Similarly degraded 0; 

24)A good question on Layouts. Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits? 

a)In digital design, decide the height of standard cells you want to layout.It depends upon how big your transistors will be.Have reasonable width for VDD and GND metal paths.Maintaining uniform Height for all the cell is very important since this will help you use place route tool easily and also incase you want to do manual connection of all the blocks it saves on lot of area.b)Use one metal in one direction only, This does not apply for metal 1. Say you are using metal 2 to do horizontal connections, then use metal 3 for vertical connections, metal4 for horizontal, metal 5 vertical etc...c)Place as many substrate contact as possible in the empty spaces of the layout.d)Do not use poly over long distances as it has huge resistances unless you have no other choice.e)Use fingered transistors as and when you feel necessary.f)Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner. 

25)What is metastability? When/why it will occur?Different ways to avoid this? 

Metastable state: A un-known state in between the two logical known states.This will happen if the O/P cap is not allowed to charge/discharge fully to the required logical levels.One of the cases is: If there is a setup time violation, metastability will occur,To avoid this, a series of FFs is used (normally 2 or 3) which will remove the intermediate states. 

26)Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output? 

The late coming signals are to be placed closer to the output node ie A should go to the nmos that is closer to the output. 2)

3) What is the fundamental difference between a MOSFET and BJT ?

In MOSFET,current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS)- In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device. 

4) What is the basic difference between Analog and Digital Design?

Digital design is distinct from analog design. In analog circuits we deal with physical signals which

are continuous in amplitude and time. Ex: biological data, sesimic signals, sensor output, audio, video etc. 

Analog design is quite challenging than digital design as analog circuits are sensitive to noise, operating voltages, loading conditions and other conditions which has severe effects on performance. Even process technology poses certain topological limitations on the circuit. Analog designer has to deal with real time continuous signals and even manipulate them effectively even in harsh environment and in brutal operating conditions.Digital design on the other hand is easier to process and has great immunity to noise. No room for automation in analog design as every application requires a different design. Where as digital design can be automated. Analog circuits generally deal with instantaneous value of voltage and current(real time). Can take any value within the domain of specifications for the device.consists of passive elements which contribute to the noise( thermal) of the circuit . They are usually more sensitive to external noise more so because for a particular function a analog designuses lot less transistors providing design challenges over process corners and temperature ranges. deals with a lot of device level physics and the state of the transistor plays a very important role Digital Circuits on the other hand deal with only two logic levels 0 and 1(Is it true that according to quantum mechanics there is a third logic level?) deal with lot more transistors for a particular logic, easier to design complex designs, flexible logic synthesis and greater speed although at the cost of greater power. Less sensitive to noise. design and analysis of such circuits is dependant on the clock. challenge lies in negating the timing and load delays and ensuring there is no set up or hold violation. 

5)What is ring oscillator? And derive the freq of operation? 

Ring oscillator circuit is a coupled inverter chain with the output being connected to the input as feedback. The number of stages(inverters) is always odd to ensure that there is no single stable state(output value). sometimes one of the stages consists of a logic gate which is used to initialise and control the circuit. The total time period of operation is the product of 2*number of gates and gate(inverter) delay. And frequency of operation will be inverse of time period.Application: used as prototype circuits for modeling and designing new semiconductor processes due to simplicity in design and ease of use. Also forms a part of clock recovery circuit. 

6)What are RTL, Gate, Metal and FIB fixes? What is a "sewing kits"?

There are several ways to fix an ASIC-based design. >From easiest to most extreme:

RTL Fix -> Gate Fix -> Metal Fix -> FIB Fix

First, let's review fundementals. A standard-cell ASIC consists of at least 2 dozen manufactured layers/masks. Lower layers conists of materialsmaking up the actual CMOS transistors and gates of the design. The upper 3-6 layers are metal layers used ti connect everything together. ASICs, of course, are not intended to be flexible like an FPGA, however, important "fixes" can be made during the manufacturing process. The progression of possible fixes in the manufacturing life cycle is as listed above.

An RTL fix means you change the Verilog/VHDL code and you resynthesize. This usually implies a new Plance&Route. RTL fixes would also imply new masks, etc. etc. In other words - start from scratch.

A Gate Fix means that a select number of gates and their interconections may be added or subtracted from the design (e.g. the netlist). This avoids resynthesis. Gate fixes preserve the previous synthesis effort and involve manually editing a gate-level netlist - adding gates, removing gates, etc. Gate level fixes affect ALL layers of the chip and all masks.

A Metal Fix means that only the upper metal interconnect layers are affected. Connections may be broken or made, but new cells may not be added. A Sewing Kit is a means of adding a new gate into the design while only affecting the metal layers. Sewing Kits are typically added into the initial design either at the RTL level or during synthesis by the customer and are part of the netlist. A Metal Fix affects only the top layers of the wafers and does not affect the "base" layers.

Sewing Kits are modules that contain an unused mix of gates, flip-flops or any other cells considered potentially useful for an unforseen metal fix. A Sewing Kit may be specified in RTL by instantiating the literal cells from the vendor library. The cells in the kit are usually connected such that each cell's output is unconnected and the inputs are tied to ground. Clocks and resets may be wired into the larger design's signals, or not.

A FIB Fix (Focussed Ion Beam) Fix is only performed on a completed chip. FIB is a somewhat exotic technology where a particle beam is able to make and break connections on a completed die. FIB fixes are done on individual chips and would only be done as a last resort to repair an otherwise defective prototype chip. Masks are not affected since it is the final chip that is intrusively repaired.

Clearly, these sorts of fixes are tricky and risky. They are available to the ASIC developer, but must be negotiated and coordinated with the foundry. ASIC designers who have been through enough of these fixes appreciate the value of adding test and fault-tolerant design features into the RTL code so that Software Fixes can correct mior silicon problems!

VLSI Interview question 2

 

Below interview questions are contributed by ASIC_diehard (Thanks a lot !). Below questions are asked for senior position in Physical Design domain. The questions are also related to Static Timing Analysis and Synthesis. Answers to some questions are given as link. Remaining questions will be answered in coming blogs. Common introductory questions every interviewer asks are: 

• Discuss about the projects worked in the previous company.• What are physical design flows, various activities you are involved?• Design complexity, capacity, frequency, process technologies, block size you handled.

 

Intel• Why power stripes routed in the top metal layers?

The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.

• Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?

Answer:This approach allows routability of the design and better usage of routing resources.

 • What are several factors to improve propagation delay of standard cell?

Answer:Improve the input transition to the cell under consideration by up sizing the driver. Reduce the load seen by the cell under consideration, either by placement refinement or buffering. If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.

• How do you compute net delay (interconnect delay) / decode RC values present in tech file?• What are various ways of timing optimization in synthesis tools?

Answer:Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.Less number of logics between Flip Flops speedup the design.Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.Better selection of design ware component (select timing optimized design ware components).Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed. 

• What would you do in order to not use certain cells from the library?

Answer:Set don’t use attribute on those library cells.

• How delays are characterized using WLM (Wire Load Model)?

Answer: 

For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net. 

Fanout vs net length is tabulated in WLMs. 

Values of unit resistance R and unit capacitance C are given in technology file. 

Net length varies based on the fanout number. 

Once the net length is known delay can be calculated; Sometimes it is again tabulated. 

• What are various techniques to resolve congestion/noise?

Answer:Routing and placement congestion all depend upon the connectivity in the netlist , a better floor plan can reduce the congestion.Noise can be reduced by optimizing the overlap of nets in the design.

• Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?

Answer:No. You should not increase clock buffers in the clock network. Increase in clock buffers cause more

area , more power. When everything is fine why you want to touch clock tree??• How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?

Answer:Better skew targets and insertion delay values provided while building the clocks.Choose appropriate tree structure – either based on clock buffers or clock inverters or mix of clock buffers or clock inverters.For multi clock domain, group the clocks while building the clock tree so that skew is balanced across the clocks. (Inter clock skew analysis).

• What are pros/cons of latch/FF (Flip Flop)?

Answer: Pros and cons of latch and flip flop 

• How you go about fixing timing violations for latch- latch paths?• As an engineer, let’s say your manager comes to you and asks for next project die size

estimation/projection, giving data on RTL size, performance requirements. How do you go about the figuring out and come up with die size considering physical aspects?

• How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?

• What are various formal verification issues you faced and how did you resolve?• How do you calculate maximum frequency given setup, hold, clock and clock skew?• What are effects of metastability?

Answer: Metastability 

• Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency?

• How to solve cross clock timing path?• How to determine the depth of FIFO/ size of the FIFO?

Answer: FIFO Depth 

STmicroelectronics• What are the challenges you faced in place and route, FV (Formal Verification), ECO

(Engineering Change Order) areas?• How long the design cycle for your designs?• What part are your areas of interest in physical design?• Explain ECO (Engineering Change Order) methodology.• Explain CTS (Clock Tree Synthesis) flow.

Answer: Clock Tree Synthesis 

• What kind of routing issues you faced?• How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done?

How do you set OCV (On Chip Variation) in IC compiler? How is timing correlation done before and after place and route?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA) 

• If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?

• Define hash/ @array in perl.• Using TCL (Tool Command Language, Tickle) how do you set variables?• What is ICC (IC Compiler) command for setting derate factor/ command to perform physical

synthesis?• What are nanoroute options for search and repair?• What were your design skew/insertion delay targets?• How is IR drop analysis done? What are various statistics available in reports?• Explain pin density/ cell density issues, hotspots?• How will you relate routing grid with manufacturing grid and judge if the routing grid is set

correctly?• What is the command for setting multi cycle path?• If hold violation exists in design, is it OK to sign off design? If not, why?

Texas Instruments (TI)• How are timing constraints developed?• Explain timing closure flow/methodology/issues/fixes.• Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange

Format) timing correlation flow.• Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed

in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?

• With respect to clock gate, what are various issues you faced at various stages in the physical design flow?

• What are synthesis strategies to optimize timing?• Explain ECO (Engineering Change Order) implementation flow. Given post routed database

and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?

Qualcomm• In building the timing constraints, do you need to constrain all IO (Input-Output) ports?• Can a single port have multi-clocked? How do you set delays for such ports?• How is scan DEF (Design Exchange Format) generated?• What is purpose of lockup latch in scan chain?• Explain short circuit current.

Answer: Short Circuit Power 

• What are pros/cons of using low Vt, high Vt cells?

Answer: Multi Threshold Voltage Technique 

Issues With Multi Height Cell Placement in Multi Vt Flow 

• How do you set inter clock uncertainty?

Answer:set_clock_uncertainty –from clock1 -to clock2

• In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran?

• What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?

Answer: 

Difference in clock uncertainty values; Clocks are propagated in post CTS. In post CTS clock latency constraint is modified to model clock jitter.

• How is clock gating done?

Answer: Clock Gating 

• What constraints you add in CTS (Clock Tree Synthesis) for clock gates?

Answer:Make the clock gating cells as through pins.

• What is trade off between dynamic power (current) and leakage power (current)?

Answer: Leakage Power Trends Dynamic Power 

• How do you reduce standby (leakage) power?

Answer: Low Power Design Techniques 

• Explain top level pin placement flow? What are parameters to decide?• Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange

Format/Library Exchange Format), how will you start floor planning?• With net length of 1000um how will you compute RC values, using equations/tech file info?• What do noise reports represent?• What does glitch reports contain?• What are CTS (Clock Tree Synthesis) steps in IC compiler?• What do clock constraints file contain?• How to analyze clock tree reports?• What do IR drop Voltagestorm reports represent?• Where /when do you use DCAP (Decoupling Capacitor) cells?• What are various power reduction techniques?

Answer: Low Power Design Techniques

Hughes Networks• What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup

and hold violations?• Explain function of Muxed FF (Multiplexed Flip Flop) /scan FF (Scal Flip Flop).• What are tested in DFT (Design for Testability)?• In equivalence checking, how do you handle scanen signal?• In terms of CMOS (Complimentary Metal Oxide Semiconductor), explain physical parameters

that affect the propagation delay?• What are power dissipation components? How do you reduce them?

Answer: Short Circuit Power Leakage Power Trends Dynamic Power   Low Power Design Techniques 

• How delay affected by PVT (Process-Voltage-Temperature)?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA) 

• Why is power signal routed in top metal layers?

 

Avago Technologies (former HP group)• How do you minimize clock skew/ balance clock tree?• Given 11 minterms and asked to derive the logic function.• Given C1= 10pf, C2=1pf connected in series with a switch in between, at t=0 switch is open

and one end having 5v and other end zero voltage; compute the voltage across C2 when the switch is closed?

• Explain the modes of operation of CMOS (Complimentary Metal Oxide Semiconductor) inverter? Show IO (Input-Output) characteristics curve.

• Implement a ring oscillator.• How to slow down ring oscillator?

 

Hynix Semiconductor• How do you optimize power at various stages in the physical design flow?• What timing optimization strategies you employ in pre-layout /post-layout stages?• What are process technology challenges in physical design?• Design divide by 2, divide by 3, and divide by 1.5 counters. Draw timing diagrams.• What are multi-cycle paths, false paths? How to resolve multi-cycle and false paths?• Given a flop to flop path with combo delay in between and output of the second flop fed back to

combo logic. Which path is fastest path to have hold violation and how will you resolve?• What are RTL (Register Transfer Level) coding styles to adapt to yield optimal backend design?• Draw timing diagrams to represent the propagation delay, set up, hold, recovery, removal,

minimum pulse width.

About ContributorASIC_diehard has more than 5 years of experience in physical design, timing, netlist to GDS flows of Integrated Circuit development. ASIC_diehard's fields of interest are backend design, place and route, timing closure, process technologies. Readers are encouraged to discuss answers to these questions. Just click on the 'post a comment' option below and put your comments there. Alternatively you can send your answers/discussions to my mail id: shavakmm@gmail.com 1 comments Links to this post      

Labels: ASIC, Physical Design, Static Timing Analysis (STA), Synthesis, Timing Analysis, VLSI

Physical Design Objective Type of Questions and Answers

• 1) Chip utilization depends on ___.

a. Only on standard cellsb. Standard cells and macrosc. Only on macrosd. Standard cells macros and IO pads

• 2) In Soft blockages ____ cells are placed.

a. Only sequential cellsb. No cellsc. Only Buffers and Invertersd. Any cells

• 3) Why we have to remove scan chains before placement?

a. Because scan chains are group of flip flopb. It does not have timing critical pathc. It is series of flip flop connected in FIFOd. None

• 4) Delay between shortest path and longest path in the clock is called ____.

a. Useful skewb. Local skewc. Global skewd. Slack

• 5) Cross talk can be avoided by ___.

a. Decreasing the spacing between the metal layersb. Shielding the netsc. Using lower metal layersd. Using long nets

• 6) Prerouting means routing of _____.

a. Clock netsb. Signal netsc. IO netsd. PG nets

• 7) Which of the following metal layer has Maximum resistance?

a. Metal1b. Metal2c. Metal3d. Metal4

• 8) What is the goal of CTS?

a. Minimum IR Dropb. Minimum EMc. Minimum Skewd. Minimum Slack

• 9) Usually Hold is fixed ___.

a. Before Placementb. After Placementc. Before CTSd. After CTS

• 10) To achieve better timing ____ cells are placed in the critical path.

a. HVTb. LVTc. RVTd. SVT

• 11) Leakage power is inversely proportional to ___.

a. Frequencyb. Load Capacitancec. Supply voltaged. Threshold Voltage

• 12) Filler cells are added ___.

a. Before Placement of std cellsb. After Placement of Std Cellsc. Before Floor planningd. Before Detail Routing

• 13) Search and Repair is used for ___.

a. Reducing IR Dropb. Reducing DRCc. Reducing EM violationsd. None

• 14) Maximum current density of a metal is available in ___.

a. .libb. .vc. .tfd. .sdc

• 15) More IR drop is due to ___.

a. Increase in metal widthb. Increase in metal lengthc. Decrease in metal lengthd. Lot of metal layers

• 16) The minimum height and width a cell can occupy in the design is called as ___.

a. Unit Tile cellb. Multi heighten cellc. LVT celld. HVT cell

• 17) CRPR stands for ___.

a. Cell Convergence Pessimism Removalb. Cell Convergence Preset Removalc. Clock Convergence Pessimism Removald. Clock Convergence Preset Removal

• 18) In OCV timing check, for setup time, ___.

a. Max delay is used for launch path and Min delay for capture pathb. Min delay is used for launch path and Max delay for capture pathc. Both Max delay is used for launch and Capture pathd. Both Min delay is used for both Capture and Launch paths

• 19) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.

a. Utilizationb. Aspect Ratioc. OCVd. Antenna Ratio

• 20) The Solution for Antenna effect is ___.

a. Diode insertionb. Shieldingc. Buffer insertiond. Double spacing

• 21) To avoid cross talk, the shielded net is usually connected to ___.

a. VDDb. VSSc. Both VDD and VSSd. Clock

• 22) If the data is faster than the clock in Reg to Reg path ___ violation may come.

a. Setupb. Holdc. Bothd. None

• 23) Hold violations are preferred to fix ___.

a. Before placementb. After placementc. Before CTSd. After CTS

• 24) Which of the following is not present in SDC ___?

a. Max tranb. Max capc. Max fanoutd. Max current density

• 25) Timing sanity check means (with respect to PD)___.

a. Checking timing of routed design with out net delaysb. Checking Timing of placed design with net delaysc. Checking Timing of unplaced design without net delaysd. Checking Timing of routed design with net delays

• 26) Which of the following is having highest priority at final stage (post routed) of the design

___?

a. Setup violationb. Hold violationc. Skewd. None

• 27) Which of the following is best suited for CTS?

a. CLKBUFb. BUFc. INVd. CLKINV

• 28) Max voltage drop will be there at(with out macros) ___.

a. Left and Right sidesb. Bottom and Top sidesc. Middled. None

• 29) Which of the following is preferred while placing macros ___?

a. Macros placed center of the dieb. Macros placed left and right side of diec. Macros placed bottom and top sides of died. Macros placed based on connectivity of the I/O

• 30) Routing congestion can be avoided by ___.

a. placing cells closerb. Placing cells at cornersc. Distributing cellsd. None

• 31) Pitch of the wire is ___.

a. Min widthb. Min spacingc. Min width - min spacingd. Min width + min spacing

• 32) In Physical Design following step is not there ___.

a. Floorplaningb. Placementc. Design Synthesisd. CTS

• 33) In technology file if 7 metals are there then which metals you will use for power?

a. Metal1 and metal2b. Metal3 and metal4c. Metal5 and metal6d. Metal6 and metal7

• 34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

a. Metal1 and metal2b. Metal3 and metal4c. Metal4 and metal5d. Metal6 and metal7

• 35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.

a. 1nsb. 3nsc. 5nsd. 6ns

• 36) Difference between Clock buff/inverters and normal buff/inverters is __.

a. Clock buff/inverters are faster than normal buff/invertersb. Clock buff/inverters are slower than normal buff/invertersc. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/invertersd. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.

• 37) Which configuration is more preferred during floorplaning ?

a. Double back with flipped rowsb. Double back with non flipped rowsc. With channel spacing between rows and no double backd. With channel spacing between rows and double back

• 38) What is the effect of high drive strength buffer when added in long net ?

a. Delay on the net increasesb. Capacitance on the net increasesc. Delay on the net decreasesd. Resistance on the net increases.

• 39) Delay of a cell depends on which factors ?

a. Output transition and input load

b. Input transition and Output loadc. Input transition and Output transitiond. Input load and Output Load.

• 40) After the final routing the violations in the design ___.

a. There can be no setup, no hold violationsb. There can be only setup violation but no holdc. There can be only hold violation not Setup violationd. There can be both violations.

• 41) Utilisation of the chip after placement optimisation will be ___.

a. Constantb. Decreasec. Increased. None of the above

• 42) What is routing congestion in the design?

a. Ratio of required routing tracks to available routing tracksb. Ratio of available routing tracks to required routing tracksc. Depends on the routing layers availabled. None of the above

• 43) What are preroutes in your design?

a. Power routingb. Signal routingc. Power and Signal routingd. None of the above.

• 44) Clock tree doesn't contain following cell ___.

a. Clock bufferb. Clock Inverterc. AOI celld. None of the above

• Answers:

1)b2)c3)b4)c5)b6)d7)a8)c

9)d10)b11)d12)d13)b14)c15)b16)a17)c18)a19)d20)a21)b22)b23)d24)d25)c26)b27)a28)c29)d30)c31)d32)c33)d34)c35)d36)c37)a38)c39)b40)d41)c42)a43)a44)c