Interrupt of 8085

Prof. Nitin Ahire 1

Microprocessor & Microcontroller - I

T.E Sem V (Rev)

Prof. Nitin Ahire

XIE, Mahim

Prof. Nitin Ahire 2

Connection of I/O devices.

� Polling method

� Interrupt method

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Interrupt system of 8085

� Definition: “It is a mechanism by which an

I/O device ( Hardware interrupt) or an

instruction (software interrupt) can suspend

the normal execution of the processor and

get it self serviced.”

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Types of interrupt

� 1) Hardware interrupt

� 2) Software interrupt

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Hardware interrupt

� Interrupt : “It is an external asynchronous

input that inform the ‘up’ to complete the

instruction that it is currently executing and

fetch a new routine in order to offer a service

to that I/O devices. Once the I/O device is

serviced, the ‘up’ will continue with execution

of its normal program.”

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Hardware interrupt

� 8085 has ‘5’ hardware interrupt

1)Trap

2)RST 7.5

3)RST 6.5

4)RST 5.5

5)INTR

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Types of Hardware interrupt

� NMI( non maskable)

1) It can’t be masked or made pending

2) Highest priority

3) This interrupt disable all maskable interrupts

4) Used for emergency

purpose like power failure, smoke detector

e.g. TRAP

� Maskable

1) It can be masked or made pending

2) Lower priority

3) These interrupt dose not disable non maskable interrupt

4) Used to interface peripherals.

e.g. RST 7.5

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Hardware Interrupt

Priority interrupt ISR address trigger

1 TRAP 0024h edge +level

2 RST 7.5 003Ch edge

3 RST 6.5 0034h level

4 RST 5.5 002Ch level

5 INTR No specific level

location

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Software interrupt

� 8085 has ‘8’ software interrupt

1)RST0

2)RST1

3)RST2

4)RST3

5)RST4

6)RST5

7)RST6

8)RST7

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Software interrupt

� These instruction ( RST0-RST7) allow the

‘up’ to transfer the program control from main

program to the subroutine program (i.e. ISR)

ISR: interrupt service routing


Software interrupt

Interrupt Restart locations

RST 0 0 X 8 = 0000h

RST 1 1 X 8 = 0008h

RST 2 2 x 8 = 0010h

RST 3 3 X 8 = 0018h

RST 4 4 X 8 = 0020h

RST 5 5 X 8 = 0028h

RST 6 6 X 8 = 0030h

RST 7 7 X 8 = 0038h


Software interrupt / hardware interrupt

� Software interrupt

1)It is as synchronous event

2)This interrupt is requested by executing instruction

3)PC is incremented

4)The priority is highest

5)It can’t be ignored

6)It is not used to interface the peripheral

Used in debugging

� Hardware interrupt 1)It is an asynchronous event2)This interrupt is requested

by external device 3)PC is not incremented4)The priority is lower than

softer interrupt5)Can be masked6)It is used to interface

peripheral devices


Interrupt related instructions

1) EI : it is used to enable the all maskable

interrupt. It required 1-byte, one MC (4T). It

does not affect on TRAP

2) DI : it is used to disable all maskable

interrupt. 1-byte (4T). It does not affect on

TRAP



SIM : (set interrupt mask)

1-byte (4T) state.

� Used to enable or disable RST 7.5, RST 6.5, RST 5.5 interrupts.

� It does not affect on TRAP & INTR .

� It is used in serial data transmission

� It also transfer serial data bit ‘D7’of ‘A’ to the SOD pin

� Hence the CWR format must be load in the ‘A’ before execution of SIM instruction.


SIM (bit pattern)� SOD pin

� D7= SOD

� D6= serial data enable 1=enable, 0=disable

� D5= Don’t care

� D4= Reset R7.5 F/F, 1=Reset 0=no effect

� D3=MSE Mask set enable 1=D2,D1,D0 bit are effective

0=D2,D1,D0 bit are ignored

� D2= M’7.5 Mask RST 7.5 1= Mask or disable R7.5

0= Enable RST 7.5

� D1=M’6.5 Mask RST 6.5 1= Mask or disable R6.5

0= Enable RST 6.5

� D0=M’5.5 Mask RST 5.5 1= Mask or disable R5.5

0= Enable RST 5.5

SOD SDE M’ 6.5M’ 7.5MSER 7.5X M’ 5.5



RIM : ( read interrupt mask)

1-byte (4T) state.

� It gives the status of the pending maskable interrupt

(RST 7.5 – RST 5.5)

� It does not affect on TRAP & INTR

� It can also transfer the contents of the serial input data

on the SID pin into the accumulator (‘D7’ bit.)

� Hence after execution of this instruction serial data get

load in to the accumulator


RIM (bit pattern)� SID pin

� D7= SID

� D6=

� D5= if 1 respective interrupt is pending

� D4= 0 respective interrupt is not pending

� D3=IE interrupt enable

� D2=

� D1= if 1 respective interrupt is Masked

� D0= 0 respective interrupt is unmasked

SID I 7.5 M 6.5M 7.5IEI 5.5I 6.5 M 5.5

Interrupt of 8085

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Transcript of Interrupt of 8085