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    Interpretation of admittance, capacitance-voltage, and current-voltagesignatures in Cu(In,Ga)Se2 thin film solar cellsTobias Eisenbarth, Thomas Unold, Raquel Caballero, Christian A. Kaufmann, and Hans-Werner Schock

    Citation: J. Appl. Phys. 107, 034509 (2010); doi: 10.1063/1.3277043

    View online: http://dx.doi.org/10.1063/1.3277043

    View Table of Contents: http://jap.aip.org/resource/1/JAPIAU/v107/i3

    Published by the American Institute of Physics.

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    Interpretation of admittance, capacitance-voltage, and current-voltagesignatures in CuIn,GaSe2 thin film solar cells

    Tobias Eisenbarth, Thomas Unold,a Raquel Caballero, Christian A. Kaufmann, andHans-Werner Schock

    Helmholtz-Zentrum Berlin fr Materialien und Energie, Glienicker Strasse 100, 14109 Berlin, Germany

    Received 3 August 2009; accepted 26 November 2009; published online 12 February 2010

    A series of CuIn,GaSe2 CIGS thin film solar cells with differently prepared heterojunctions hasbeen investigated by admittance spectroscopy, capacitance-voltage CV profiling, and temperaturedependent current-voltage IVT measurements. The devices with different CdS buffer layerthicknesses, with an In2S3 buffer or with a Schottky barrier junction, all show the characteristic

    admittance step at shallow energies between 40 and 160 meV, which has often been referred to as

    the N1 defect. No correlation between the buffer layer thickness and the capacitance step is found.

    IVT measurements show that the dielectric relaxation frequency of charge carriers in the CdS layers

    is smaller than the N1-resonance frequency at low temperatures where the N1 step in admittance is

    observed. These results strongly contradict the common assignment of the N1 response to a donor

    defect at or close to the heterointerface. In contrast, an explanation for the N1 response is proposed,

    which relates the admittance step to a non-Ohmic back-contact acting as a second junction in the

    device. The model, which is substantiated with numerical device simulations, allows a unified

    explanation of characteristic admittance, CV, and IVT features commonly observed in CIGS solar

    cells. 2010 American Institute of Physics. doi:10.1063/1.3277043

    I. INTRODUCTION

    During the past decades, thin film solar cells employing

    the quaternary semiconductor CuIn,GaSe2 CIGS as aphotoactive layer have made significant progress with the

    demonstration of conversion efficiencies close to 20%.1

    However, knowledge about defects in CIGS and their influ-

    ence on the device performance is still incomplete. Phenom-

    ena such as the rollover, crossover, and a red kink in the IV

    characteristics are often observed for CIGS solar cells and

    have been subject to controversial debate for many years.Capacitance profiling is a standard technique widely used for

    deriving material quantities essential to the understanding of

    solar cell device operation, such as the carrier concentration

    and the distribution of defects in the absorber layer. For

    CIGS capacitance profiling yields charge carrier profiles,

    which are very difficult to interpret.

    Controversy has also surrounded the interpretation of ad-

    mittance measurements on CIGS solar cells. In many such

    studies, CIGS solar cells have been found to exhibit a shal-

    low defect contribution with an activation energy EA100 meV, which has been denoted as the N1 defect bymany authors, in order to distinguish it from another com-

    monly observed deeper defect state contribution, N2, with an

    activation energy EA250 300 meV.2

    The identification of

    the spatial location of the N1 defect has been a subject of

    discussion for the past 20 years. Air annealing experiments3

    revealed an energetic shift of the N1 defect to deeper ener-

    gies, whereas the energetic position of the N2 defect was

    unaffected. This observation suggested the identification of

    the N1 as an interface defect. Also, deep level transient spec-

    troscopy DLTS investigations4 associated this defect with a

    minority carrier trap thus supporting the interface defect

    theory. On the other hand, admittance measurements with

    applied reverse bias2

    indicated no change in the energetic

    position of the N1. Such a behavior is a general characteristic

    of a bulk defect, but may also be consistent with an interface

    contribution, if the Fermi level is pinned at the interface.

    Thus, in accordance with this result, doping-type inversion

    and Fermi level pinning at the interface were deduced.4

    Such

    a Fermi level pinning at the interface was also used to ex-plain the minor role of recombination at the heterointerface.

    5

    The interface inversion was assumed3

    to be caused by the

    VSe donor vacancy providing the necessary charge at the in-

    terface. This picture also seemed to be in agreement with the

    N1 shift during annealing experiments, by assuming a passi-

    vation of selenium vacancies by oxygen impurities.

    These interpretations of the N1-admittance response rely

    on an interaction of electrons in the conduction band with the

    N1-interface states in order to explain the admittance mea-

    surements. Consequently, the N1 contribution to capacitance

    measurements should be affected by changes in the charge

    distribution on the n-side of the heterojunction. In particular,one expects a dependence of the defect step height in admit-

    tance on the extension of the space charge region SCR at

    the n-side of the junction and therefore also on the thickness

    of the CdS buffer layer. Indeed, a reduction in the step height

    with decreased CdS buffer layer thickness was found in one

    study.6

    However, in several other studies,7,8,2

    the change in

    the admittance step could not be quantitatively correlated

    with changes in the n-side of the heterojunction. To under-

    stand this discrepancy, it was proposed that the N1 relatedaElectronic mail: [email protected].

    JOURNAL OF APPLIED PHYSICS 107, 034509 2010

    0021-8979/2010/1073 /034509/12/$30.00 2010 American Institute of Physics107, 034509-1

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    http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043http://-/?-http://-/?-http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043http://-/?-http://dx.doi.org/10.1063/1.3277043http://dx.doi.org/10.1063/1.3277043
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    defect states are not located at the interface but within an

    n-type inverted region in the absorber close to the

    heterointerface.9

    Other characteristics and unusual features in CIGS solar

    cells are the observed crossing of the dark and illuminated IV

    curves crossover,10 the distortion of the red illuminated IVcurve in the fourth quadrant and fill factor losses red kink,11

    and the partial saturation of the forward current rollover.12

    The IV rollover was initially explained by a double-diode

    effect13

    caused by a Schottky diode at the back-contact with

    opposite polarity compared to the heterojunction. However,

    subsequent detailed investigations of the CIGS/Mo interface

    indicated an Ohmic back-contact and revealed good collec-

    tion efficiencies for electrons generated at the

    back-contact.1416

    Further studies17

    showed the crossover ef-

    fect only for blue light but not for red illumination, indicat-

    ing that the crossover was caused by photon absorption andcharge carrier generation in the CdS buffer layer. Based on

    the assumption of an Ohmic back-contact and a significant

    influence of the CdS buffer layer on the device characteris-

    tics, a model was introduced assuming deep acceptor states

    in the CdS buffer layer, which compensate donors and result

    in a low net CdS charge density in equilibrium.18

    Such an

    insulating characteristic causes a substantial fraction of the

    built-in voltage to drop across the CdS resulting in a barrier

    for both injected and photogenerated carriers as shown in

    Fig. 1a, thus explaining the red kink in the IV characteristicdescribed above.

    10However, since such a barrier is inconsis-

    tent with Fermi level pinning at the buffer/absorber interface

    Fig. 1b a revised model was put forward to explain thetemperature dependent current-voltage IVT crossover ef-fects and the N1-admittance characteristics.

    6For this model

    the presence of a so-called p+ layer with deep acceptors in

    an ordered defect compound ODC layer close to the het-erointerface was assumed. The IV crossover was explained

    by an illumination-induced change in the potential barrier

    associated with the p+ layer: Photogenerated holes in the

    CdS and the ODC neutralize ionized deep acceptors in the

    ODC leading to a reduction in the voltage drop in the ODC.

    The resulting increase in the electron density leads to an

    increased recombination under illumination. This concept of

    a p+ layer has been generally adopted for the explanation of

    the crossover behavior. We note that all of the above men-

    tioned models for explaining the IVT characteristics in CIGS

    solar cells are very sensitive to specific assumptions about

    material properties such as band offsets, interface defect, and

    charge density, and the values of the capture cross sections of

    defects.

    Another controversial issue in CIGS is the interpretation

    of capacitance-voltage CV profiling measurements. The de-

    termination of the built-in voltage and doping concentrationfrom a standard interpretation of a MottSchottky plot

    breaks down when the location of charge response is signifi-

    cantly shifted away from the edge of the depletion region

    due to the presence of deeper states within the band gap.

    Polycrystalline materials, such as CIGS thin films and de-

    vices, are very likely to contain a significant number of deep

    defects. The measurement of defect profiles Ntx by meansof CV profiling has often led to U-shaped profiles with an

    apparent increase in the defect density toward the bulk and

    an increase toward the heterointerface.8

    Recent

    publications19,20

    explained the increase in defect profiles at

    large distances from the heterointerface by an accumulation

    of static charge in deep acceptor states caused by the dc biassweep.

    21The increase in the defect profiles toward the h et-

    erointerface has often been interpreted as a real effect.22

    Here, a systematic analysis of capacitance and IVT measure-

    ments on standard CIGS solar cells is provided. The results

    are discussed in the context of existing models leading to a

    contradiction with a number of assumptions that have been

    essential to these models. In turn, an alternative comprehen-

    sive model is outlined, which can consistently explain most

    phenomena observed in capacitance and IVT measurements.

    The outline of this article is as follows. Section II sum-

    marizes the possible admittance contributions. Section III

    gives a brief outline of the experimental procedures used in

    this study. In Sec. IV admittance and capacitance profiling

    data, as well the IVT results, are presented. In Sec. V the

    results are discussed in the light of the existing models and

    an alternative, much simpler explanation for the main mea-

    surement characteristics is presented. In Sec. VI the model is

    substantiated by device simulations and final conclusions are

    drawn in Sec. VII.

    II. ADMITTANCE SPECTROSCOPY

    Admittance spectroscopy involves the measurement of

    the complex admittance

    Y,T = iC,T + G,T , 1

    consisting of the capacitance C and the conductance G, as a

    function of frequency and temperature T. In the case of a

    p-n junction containing only shallow donors and acceptors,

    the capacitance is determined by the width of the SCR, pro-

    vided the majority carriers can respond at the ac frequency

    = 2f and temperature T of the measurement. The charac-

    teristic frequency of carrier response is related to the dielec-

    tric relaxation time D by

    FIG. 1. Band diagrams show possible barriers for the diode current. aIllumination dependent net carrier concentration in the CdS modulates the

    barrier height for the current transport at the CdS/CIGS interface. b Lightmodulated charge occupation of deep acceptor states in the OVC changes

    the barrier height in the OVC layer whereas the position of the Fermi level

    at the CdS/CIGS interface stays constant.

    034509-2 Eisenbarth et al. J. Appl. Phys. 107, 034509 2010

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    D =2

    D

    =

    , 2

    with the dielectric constant and conductivity . For mea-

    surement frequencies D, the carriers are frozen out

    Fig. 2, the whole semiconductor behaves as a dielectric,and the capacitance approaches its geometrical value Cgeo

    =A /d, where d is the sample thickness.At higher temperatures additional steps in the admittance

    spectra may occur due to the charging and discharging of

    defects at a location where the energy level Et of electron

    hole traps crosses the quasi Fermi level EFn EFp. This isillustrated in Fig. 2 left as a step between the capacitance athigher frequencies, CHf, and the capacitance at lower fre-

    quencies, CLf step 1. The same step is also visible if thecapacitance is plotted versus the temperature as shown in

    Fig. 2 right. For consistency with the notation commonlyused in literature, the lower capacitance plateau will be

    called CHf and the higher capacitance plateau will be called

    CLf for both cases. The characteristic frequency for this ca-

    pacitance response is related to the thermal emission depthEA of the defect and can be expressed by the following equa-

    tion:

    0 = 2f0 = NC,Vvthn,peEA/kT = 20T

    2eEA/kT, 3

    where NC,V is the effective density of states in the conduction

    or valence band, vth is the thermal velocity, and n,p is the

    electron/hole capture cross section. On the right hand side of

    Eq. 3, a thermal emission prefactor 0 is introduced, whichcomprises all temperature independent terms of the thermal

    velocity vth and the effective density of states NC,V. As shown

    in earlier investigations,23

    an increase in 0 with increasing

    activation energy EA

    is commonly found, in accordance with

    the generally observed MeyerNeldel rule.24

    The junction capacitance response may be obtained from

    an integration of the Poisson equation and can be written as

    C=A

    x x =

    xxdx

    0

    xdx

    , 4

    where x describes the distance to the interface and is the

    variation of charge density caused by the oscillating bias. In

    the general case the integral extends over both sides of the

    homojunction or heterojunction device. In Sec. II A and II B

    the capacitance response expected for different defects and

    junction geometries proposed for CIGS devices in literature

    is briefly outlined.

    A. Bulk defect response

    Figure 3a shows a p-type absorber with a shallow dop-ing density NA and a defect level EtA above the valence band,

    crossing the Fermi level within the p-side of the SCR. The

    applied alternating voltage induces a change in the charge

    density at the edges of the SCR and at the position xtA where

    the defect crosses the Fermi level. For smaller than the

    thermal emission frequency of the defect, 0, the first mo-

    ment of charge response x decreases to a value xp=NtAxtA +NAxp / NtA +NA. For frequencies larger than 0,the defect does not follow the alternating voltage. Thus, the

    two values of the capacitances CHf and CLf are

    CLf = A1

    xp + xn CHf = A1

    xp + xn . 5

    B. Interface defect response

    In the case of a defect crossing the Fermi level at or

    close to the interface Fig. 3b, an interaction of the defectlevel EtD with electrons from the conduction band takes

    place, if the energetic distance from the Fermi level at the

    interface to the conduction band minimum is sufficiently

    small. At frequencies, larger than the thermal emission rate

    0 of the defects at the interface, the capacitance is deter-

    mined by the extension of the space charge regions xn and xp

    FIG. 2. Admittance spectra for a standard CIGS solar cell reveal the freeze-

    out of the majority carriers of the absorber layer. With increasing tempera-

    tures an admittance step occurs between CHf high frequency and CLf lowfrequency.

    FIG. 3. Possible defect responses of the device with a single discrete defect

    illustrated for a pn-junction. a An acceptor level EtA crosses the Fermilevel in the SCR of the bulk and affects the charge response xp of thep-side. b A donor level EtD crossing the Fermi level at or close to theheterointerface and shifts the charge response xn of the n-side of the

    junction.

    034509-3 Eisenbarth et al. J. Appl. Phys. 107, 034509 2010

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    as described in Sec. II A. For 0 the space charge of the

    p-type region is essentially counterbalanced by the charge

    response at the interface, reducing xn to zero.

    The two values of the capacitance are

    CLf = A 1xp

    CHf = A 1xp + xn

    . 6This capture and emission of electrons by defect states at the

    interface depends on the supply of electrons from the n-side.This means that both processes, electron supply through the

    buffer and capture/emission of electrons by the interface

    states, are connected in series.

    III. EXPERIMENT

    CuIn1xGaxSe2 thin films were grown on Mo coated float

    glass substrates using a multistage coevaporation physical

    vapour deposition PVD process.25,26 Solar cells with a totalarea of 0.5 cm2 were prepared from the absorber layers by

    chemical bath deposition of a CdS buffer layer, rf sputtering

    of a transparent ZnO/ZnO:Al bilayer front contact, and

    evaporation of a Ni/Al contact grid. All devices investigated

    were produced using absorber layers from a single deposi-

    tion process. The CdS series thickness of the CdS buffer

    layer was varied by changing the dipping time in the chemi-

    cal bath. Schottky-contact devices were produced by evapo-

    rating Al contacts immediately after etching the absorber sur-

    face with a 1% solution of bromine in methanol. For one

    device an In2S3 buffer layer evaporated by PVD technique27

    was employed.

    Solar cell characterization was performed under standard

    conditions: AM1.5 illumination, 100 mW/cm2 intensity, and

    at 25 C. Temperature dependent electrical measurements

    were carried out using a closed-cycle helium cryostat with a

    measurement range 40310 K. The sample temperature was

    determined by a calibrated Si diode mounted on a glass sub-

    strate identical to the glass substrates used for the CIGS

    deposition. Admittance spectroscopy was performed with an

    HP4284 LCR meter and four-point probes. To ensure a re-

    laxed state of the investigated devices, the samples were kept

    at 300 K for 1 h in darkness prior to cooling down. Drive-

    level capacitance profiling DLCP was measured using thesame setup. IVT measurements were performed with a Kei-

    thley 238 source-measure unit using the same cryostat and

    the same electrical contacts utilized for the capacitance mea-

    surements. The thickness of the deposited CdS buffer layerwas determined in a scanning electron microscope SEM oncomplete solar cell device cross sections.

    IV. RESULTS

    The solar cell parameters of the different devices with

    varying CdS thickness are shown in Table I. The thickness of

    the buffer layers was determined from SEM cross sections. A

    best efficiency of 15% is reached for devices with CdS-layer

    thicknesses of 25 and 60 nm, whereas the lowest efficiency is

    found for the device without a CdS buffer layer.

    A. Admittance

    The admittance spectra for the samples with different

    CdS thicknesses, In2S3 buffer layers, and Schottky contacts

    measured at zero bias are shown in Fig. 4. All spectra show

    two distinct plateaus CHf and CLf, respectively, and a transi-

    tion region in between. The plateau of almost constant CHfcorresponds to the sum of the SCRs of the devices. For all

    samples the capacitance decreases toward the geometric ca-

    pacitance value at low temperatures indicating the freeze-out

    of the majority carriers. The value of the geometric capaci-

    tance is estimated at Cgeo =5.2 nF cm2 for a total devicethickness of 2 m and a dielectric constant CIGS =11.70.

    28

    The activation energy of the capacitance step between

    the CHf and CLf plateaus can be evaluated from the inflection

    points of the C-f-T spectra. An Arrhenius plot for the differ-

    ent samples is shown in Fig. 5a with the calculated activa-tion energies, and the corresponding thermal prefactors 0are shown in Fig. 5b as a function of the activation energy.The values for the N1 step from literature

    29,8,4,3have also

    been added. A MeyerNeldel type relationship24

    between the

    prefactor and the activation energy is found, which agrees

    very well with the results from literature. Note that this re-

    lationship between prefactor and activation energy is found

    TABLE I. Device parameters of the samples from the CdS thickness varia-

    tion with composition ratios of Ga / III0.27 and Cu/ III0.88.

    CdS-SEM

    nmVOCmV

    JSCmA cm2

    FF

    %

    %

    0 413 31.2 56.8 7.3

    25 652 32.1 72.9 15.2

    60 654 30.4 76 15.1

    160 652 29.8 74.3 14.4

    FIG. 4. Admittance spectra for solar cells with different CdS thicknesses,

    In2S3 buffer layers, and Schottky contacts in dependence of the temperature

    T. For all heterostructures an evident admittance step is visible between CLfand CHf.

    034509-4 Eisenbarth et al. J. Appl. Phys. 107, 034509 2010

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    for all structures, regardless of the presence, type, or thick-

    ness of the buffer layer. From the good agreement of the

    activation energies and prefactors we conclude that the ca-

    pacitance step observed in our measurements corresponds to

    the N1 step reported in literature for all samples measured.

    As mentioned above, this N1-admittance response was

    previously interpreted as a defect contribution at or close to

    the absorber/buffer interface. In this model,6

    CHf reflects the

    contribution of the n- and p-side SCR widths xn and xp

    whereas CLf is determined only by the SCR width xp of theabsorber Eq. 6. Thus the measured difference in spacecharge width x = /CHf /CLf should directly yield the

    thickness of the presumably depleted buffer layer. The val-ues of /CLf, /CHf, and x are shown in Table II for all

    measured devices. It can be seen that the total SCR width

    xtotal = /CHf and the activation energy of N1 increases with

    increasing thickness of CdS, whereas x shows no clear cor-

    relation with the CdS-layer thickness. In particular, it can be

    seen that even devices with a highly doped n-side such as the

    Schottky contact also show a significant difference between

    CHf and CLf. Admittance measurements performed with ap-

    plied reverse bias of 1 V do not lead to a shift of the

    activation energy, in agreement with previous results re-

    ported in literature.2

    Also shown in Table II are values for the

    net doping density NA deduced from the capacitance values

    of the high frequency plateaus in Fig. 4. It can be seen that

    these values are around 2 31015 cm3 for all sampleswith a somewhat higher value for the device with the In2S3buffer layer.

    B. Capacitance profiling

    Capacitance profiles were measured by means of the

    DLCP and the CV-profiling technique. Both methods showed

    good agreement, with the DLCP measurement featuring an

    improved signal-to-noise ratio. For this reason, in Sec. IV,

    only the DLCP profiles will be reported. In the following the

    concentration Nx extracted from the CV techniques iscalled the defect concentration, comprising both the carrier

    and the defect concentration. In order to avoid metastability

    effects arising from voltage bias perturbation, the CIGS solar

    cells were cooled down in the relaxed state. The measure-ment temperature was selected such that the low frequencies

    1 kHz were just below the N1-turn-on frequency whereasfor high frequencies 1 MHz only the free carrier concen-tration should contribute to the profile.

    In Fig. 6a, the DLCP profiles for 25 nm CdS are shownfor low and high frequencies. The defect profiles show the

    typical U-shaped form commonly reported in literature,8,19

    with a minimum at a profiling distance of 400800 nm. Both

    profiles exhibit a significant increase in the defect profile

    toward the junction and toward the bulk of the sample.

    Trying to discern differences between the low frequency

    and high frequency profiles, it can be seen that the curves

    have an almost identical shape, but seem to be shifted by adistance xCV. If the apparent x-shift of the curves is taken

    into account, there is no actual difference in the magnitude of

    the profiling density visible, indicating that the magnitude of

    the defect concentration is not affected by the N1-signal re-

    sponse. Note also that exactly the same behavior is observed

    for the DLCP profiles of the Schottky contacts as shown in

    Fig. 6b.The CV profiles of all samples investigated show a simi-

    lar behavior with respect to low frequency and high fre-

    quency measurements. Also, as is shown in Fig. 7, the shift

    in profiling distance xCV and the shift xC-f-T computed

    FIG. 5. a Arrhenius diagram derived from the admittance results in Fig. 4.

    b The change in the thermal emission prefactor with increasing activationenergy reflects the MeyerNeldel rule and is compared to the values from

    literature Refs. 29, 8, 4, and 3.

    TABLE II. Comparison of the spatial extensions derived from CHf and CLf in admittance for the different CdS

    thicknesses, InS buffers, and the Schottky contacts. The carrier concentration NA is extracted from CHf with an

    assumed built-in voltage of 0.9 V.

    CdS-SEM

    nmx

    nm /CLfnm

    /CHfnm

    EAmeV

    0s1 K2

    NAcm3

    0 99 592 691 63 6 700 2.41015

    25 156 616 772 85 8 200 2.11015

    60 235 681 916 160 270 000 1.61015

    160 214 821 1035 161 240 000 1.51015

    50 In2S3 144 288 432 106 37 000 8.01015

    0 Schottky 98 531 629 40 1 000 3.01015

    034509-5 Eisenbarth et al. J. Appl. Phys. 107, 034509 2010

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    from the admittance measurements closely agree with each

    other whereas again no direct correlation of xCV with the

    CdS thickness is found.

    It has previously been argued that the increase in thedefect concentration toward the heterojunction, as found in

    our measurement, represents a real increase in defect

    concentration.19

    However, we note that the increase toward

    the heterojunction is only observed for very large positive

    voltages, corresponding to forward biasing the main junc-

    tion. In Fig. 8, this is illustrated for the 60 nm CdS sample

    measured at 130 K where the different applied biases are

    indicated for the 10 kHz profile. To observe the minimum in

    the defect profile, a modest forward bias 0.3 V is necessary,and for the strong apparent increase in defect concentration

    at x = 200 nm a very large forward bias of 0.9 V is necessary.

    Since this large forward bias even exceeds the built-in volt-

    age of the junction, the interpretation of an apparent increase

    in defect concentration at such a large bias is questionable aswill be discussed in Sec. V below.

    C. IVT

    IVT measurements have been performed for the same

    devices and are discussed in this section. To ensure a relaxed

    state, the samples were kept in darkness at 300 K for 1 h and

    then cooled down in darkness. The measurements were then

    performed starting at low temperatures and proceeding up to

    room temperature. The recording of the IV curves started

    from low intensities 0% up to full intensity 100%.Dark IV curves for different devices are shown in Fig. 9

    for a measurement performed at 100 K. It can be seen Fig.

    FIG. 6. a DLCP profiles for 25 nm CdS are shown for high 1 MHz andlow 1 kHz frequencies. The profiles are measured at temperatures wherethe N1 has a strong impact on the admittance in this frequency range. Hence

    the DLCP profiles at 1 kHz should be affected by the N1 but not the curves

    at 1 MHz. However, the shape of the profiles does not change and only a

    shift by xCV occurs. b The same effect occurs for the Schottky-contactdevice.

    FIG. 7. Admittance step xC-f-T plotted against the shift xCV derived from

    the difference of high and low frequency DLCP profiles. Expect the sample

    without CdS 0 nm CdS, both are in good agreement.

    FIG. 8. DLCP profile for the device with a 60 nm CdS layer measured at 10

    kHz and 130 K. For dc values +0.3 V an increase toward the bulk mate-

    rial is observable. Between +0.3 and +0.9 V a minimum and an increase in

    NDLCP toward the heterointerface is observable. For voltages +0.9 V a

    steep increase in NDLCP and an increase in the profile distance x can beobserved. We note that the measured VOC of the device is close to 0.9 V at

    this temperature.

    FIG. 9. a Dark IV curves of the devices with different CdS thicknessesmeasured at 100 K in the relaxed condition. b Layer resistance plottedagainst the buffer thickness extracted from a. The displayed series resis-tances are calculated in the forward bias range around 1.2 V. The specific

    resistance is calculated from the slope.

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    9a that the current through the devices is limited by asignificant series resistance RS, which increases with increas-

    ing CdS thickness. When the observed series resistance is

    plotted versus the CdS thickness as shown in Fig. 9b, alinear behavior is found. This indicates that the series resis-

    tance is caused by the bulk resistivity of the CdS, with a

    value ofCdS=1.6107 m at 100 K.

    The generally accepted interpretation of the N1-

    admittance response assumes a defect contribution at or close

    to the heterointerface, which implies a supply of electrons

    from the ZnO through the CdS. To estimate whether current

    transport through the CdS may be limiting the N1-

    admittance response, the dielectric turn-on frequency corre-

    sponding to the observed resistivity of the CdS at different

    temperatures can be computed using the dielectric relaxation

    time30

    D = 1 /D Eq. 2 as follows:

    D = 1CdS

    . 7

    The CdS turn-on frequency D is shown together with the

    inflection frequency 0 of the N1 response for the device

    with 25 nm CdS in Fig. 10. The values have been calculated

    assuming a dielectric constant of CdS = 100 for the CdS

    buffer layer. It can be seen that the N1-inflection frequency

    0 is larger than D for the whole temperature range. This

    result indicates that a heterointerface defect causing the N1

    response is highly unlikely as will be discussed below.

    Illuminated and dark IV curves are shown together for

    different temperatures in Fig. 11a for temperatures between100 and 300 K. It can be seen that the superposition of dark

    and illuminated IV curves is violated and that a crossover of

    the dark and illuminated curves is observed, in agreement

    with the literature data mentioned above. It can be seen that

    the effect is much more pronounced at lower temperatures

    than at room temperature. In Fig. 11b illuminated IV curvesare shown for different illumination intensities at a measure-

    ment temperature of 100 K. The curves show a significant

    rollover effect in the forward bias range, which becomes

    more pronounced for lower illumination intensities. A more

    detailed investigation of these effects will be presented in a

    separate forthcoming publication.

    V. DISCUSSION

    A. Evaluation of existing models

    In this section the experimental results presented in Sec.

    IV will be discussed with regard to the different models pro-

    posed earlier to explain the N1-admittance response. We start

    with summarizing the main experimental results obtained in

    Sec. IV.

    1 An admittance response corresponding to the N1-admittance signal reported in literature has been found

    for all CIGS devices investigated. However, the capaci-

    tance step x = /CHf /CLf does not agree with the

    different CdS buffer layer thicknesses present in the de-

    vices. A CIGS Schottky barrier device with neither CdS

    nor ZnO layers present and a device with an In2S3 buffer

    show N1 steps with x =100 nm. These last two de-

    vices have not received any CdS treatment and thus

    should have strongly modified interface properties com-

    pared to the other samples.

    2 Dark IV measurements at low temperatures 100150 K

    show that the resistivity of CdS limits the current flowthrough the device, with a dielectric relaxation fre-

    quency smaller than the measured inflection frequency

    of the N1-admittance response.

    3 DLCP measurements at frequencies lower and higherthan the N1-resonance frequency show identical profile

    shapes, shifted by a distance xCV, which closely corre-

    sponds to the admittance step xC-f-T.

    The first two findings are in strong contradiction to the

    commonly accepted model, which explains the N1 response

    with the presence of a CdS/CIGS interface defect that is

    being charged and discharged through conduction band elec-

    FIG. 10. Reciprocal value D of the calculated dielectric relaxation time

    Eq. 7 is plotted together with the inflection point 0 from admittanceagainst the temperature. D is higher than 0 by one order of magnitude in

    the shown temperature range.

    FIG. 11. a The dark and illuminated 100% IV curves are displayed

    between 100 and 300 K. The crossover occurs in the whole temperaturerange and increases for decreasing temperatures. b IV curves for differentillumination intensities at 100 K. The rollover effect and its dependence on

    illumination intensity can be observed.

    034509-7 Eisenbarth et al. J. Appl. Phys. 107, 034509 2010

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    trons from the CdS side. The presence of a capacitance step

    ofx = 100 nm for the sample with 0 nm CdS cannot also be

    explained with a freeze-out of the i-ZnO for high measure-

    ment frequencies since the doping concentration31

    of this

    layer is larger than 1017 cm3. In addition, for the Schottky

    barrier device, no CdS and no ZnO is present, but still a

    capacitance step of about 100 nm is observed. Because of the

    large resistivity of the CdS layer also the charging and dis-

    charging of a donor defect either directly at the interface or

    at a buried junction interface about 100 nm away from the

    main junction are unlikely.

    The third result indicates that the N1-admittance re-

    sponse does not arise from a bulk defect contribution be-

    cause in this case the profiling density would be expected to

    change for low and high measurement frequencies. Appar-

    ently this is not the case neither for solar cells with or with-

    out CdS nor for Schottky contacts.

    Therefore it is concluded that none of the hitherto pro-

    posed models, intended to explain the N1-admittance signa-ture, is compatible with the experimental results presented in

    this paper.

    In Sec. V B an alternative model will be proposed that,

    in our opinion, provides a natural explanation for the N1-

    admittance signature. The main ingredient of this model is

    the assumption of a non-Ohmic back-contact at the

    CIGS/Mo interface, a concept that has been discussed earlier

    for CdTe and also CIGS solar cells and appears physically

    very reasonable. By discussing the effects of a back-contact

    barrier on the ac and dc responses of CIGS devices, it will be

    shown that the experimental results presented in this paper

    can be explained consistently.

    B. Alternative model: Admittance response in thepresence of back-contact barrier

    In Fig. 12 the band diagram of a CdS/CIGS junction is

    shown with a non-Ohmic Schottky barrier at the CIGS/Mo

    back-contact. The difference between the Fermi level in

    equilibrium and the valence band maximum at the Mo metal

    surface defines the barrier height B of the back-contact. In

    addition to the main junction depletion region wj, a second

    depletion region with a width of wC is present at the

    CIGS/Mo back junction resulting from the non-Ohmic back-

    contact. It is assumed that the main junction and the back-

    contact can be treated as independent circuit elements with

    no interaction between the two diodes. This is a reasonable

    assumption for the relaxed state with a doping density NA1015 cm3 and a device thickness d2 m, where wj600 nm and wC200 nm for a typical back barrier heightofB =0.2 eV.

    The equivalent circuit model shown in Fig. 13 consists

    of a series connection of two diodes with opposite polarity.The resulting complex admittance is derived from the

    equivalent circuit model in Fig. 13 as follows:

    1

    Ytotal=

    1

    Gj + iCj+

    1

    GC + iCC. 8

    The total capacitance Ctotal of the solar cell is defined by the

    measured admittance in the parallel equivalent circuit Ytotal= Gtotal + iCtotal and thus Ctotal results from the imaginary

    part ImY as follows:

    Ctotal =CCGj

    2 + CjGC2 + 2CcCjCc + Cj

    GC + Gj2 + 2Cc + Cj

    2. 9

    It is useful to analyze Eq. 9 using the characteristic fre-quency C defined as follows:

    32

    C =1

    C

    =GC + Gj

    CC + Cj. 10

    Two limiting cases can be distinguished.

    1 For high frequencies C of the applied alternatingvoltage, the capacitance is reduced to a series connection

    of CC and Cj.

    CHf =CCCj

    CC + Cj. 11

    2 For low frequencies C and for V=0 where theback-contact does not limit the current GCGj, thetotal capacitance equals the junction capacitance

    CLf = Cj . 12

    Therefore the applied alternating voltage does not drop

    across the back-contact for low frequencies C and

    GCGj case 2. The characteristic frequency C hasthe same activation energy as GC and this activation

    energy corresponds to the barrier height B of the

    back-contact.33

    For frequencies C the barrier at the

    FIG. 12. The band diagram shows a CdS/CIGS/Mo structure with a

    Schottky contact with the height B at the CIGS/Mo interface. The addi-

    tional junction at the back-contact causes a depletion width wC in addition to

    the main junction depletion region wj. The index c denotes the back-contact

    parameters whereas the junction parameters are labeled with j.

    FIG. 13. Equivalent circuit describing the double-diode behavior caused by

    the Schottky barrier at the back-contact.

    034509-8 Eisenbarth et al. J. Appl. Phys. 107, 034509 2010

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    back-contact impedes the electron transport over the bar-

    rier and the applied alternating voltage drops also across

    the back-contact case 1.

    The current across a semiconductor-metal Schottky bar-

    rier can be described by34

    J J0eqV/kT 1 = qNVhEe

    qB/kTeqV/kT 1, 13

    where the saturation current density J0

    is given by the effec-

    tive density of states NV of the valence band, the mobility hof holes, electric field E, and the barrier height B of the

    metal-semiconductor junction.

    In this model the activation energies derived from the

    Arrhenius diagram Fig. 5 have to be recalculated, as theseenergies were obtained using Eq. 3, which assumes a T2

    dependency of the thermal emission prefactor 0. For a ca-

    pacitance step caused by a Schottky contact, it is expected

    that the thermal emission prefactor 0 depends on qNVh /SEq. 13, where S denotes the dielectric constant of thesemiconductor. If one assumes a temperature independent

    mobility h in the measured temperature range 100200

    K35

    and a T1.5

    temperature dependence of the effective den-sity of states NV, the Arrhenius diagram should be plotted as

    ln0 /T1.5 versus T1 to obtain the correct temperature in-

    dependent prefactor.

    Considering the distribution of the current and bias

    within the equivalent circuit model Fig. 13 of the double-diode model, it was previously shown that a Schottky contact

    at the back-contact may be responsible for the crossover and

    rollover in the IV characteristic of CdTe solar cell

    devices.36,37

    For the purpose of this paper, we will restrict

    ourselves mainly to the discussion of the effect of a back-

    contact barrier on capacitance measurements. However, it

    should be mentioned that a non-Ohmic back-contact can give

    a natural explanation for the anomalous IV features com-monly observed in CIGS.

    C. Analysis of experimental data with the double-diode model

    If the N1-admittance step is caused by a back-contact

    barrier as proposed in Sec. V B, then the N1-activation en-

    ergy EA should reflect the barrier height B and the observed

    step x between CLf and CHf should reflect the back barrier

    depletion width. This depletion width can be related to the

    barrier height by

    wC =2SB

    e2NA, 14

    where NA is the carrier concentration of the CIGS absorber at

    the back-contact. Thus it is possible to obtain NA from plot-

    ting x vs EA. Such a plot is shown in Fig. 14 from whicha value ofNA = 2.80.410

    15 cm3 can be extracted. This

    value is in good agreement with the carrier concentration of

    the CIGS absorber in the relaxed state obtained from CHf in

    Sec. III Table II.The double-diode model can also provide a natural ex-

    planation for the behavior of defect concentration profiles

    observed in CV measurements. In Fig. 15 the reciprocal val-

    ues of the CV raw data from the carrier profile of Fig. 8 are

    shown. The profiling distance x=A /C0 is determined bythe small signal capacitance C0. In the double-diode model,

    the profiling distance xHf for high frequencies arises from aseries connection of the main and the back-contact junction

    whereas for low frequencies only the main junction contrib-

    utes. This is expected to cause a shift xCV in the profilingdistance in agreement with the experimental finding. As can

    be seen in Fig. 15 this difference between /CLf and /CHfstays constant at around 200 nm for Vdc+0.9 V, a value

    which corresponds to the open circuit voltage value VOC at

    150 K derived from IVT measurements and represents a

    good estimate for the built-in potential Vbi in the device. If

    the device is forward biased the situation becomes more

    complicated. For applied voltages larger than the built-in

    voltage VVbi of the main junction, the back diode startsto block also at low frequency and this is why the capaci-

    tance step or profiling distance step xCV is no longer ob-

    served as is shown in Fig. 15. Also, as the depletion width of

    the back diode widens for VVbi, the total capacitance of

    the device actually starts to decrease again, which causes the

    profiling distance to apparently roll over, as shown in Fig. 8.

    For Vdc+0.9 V the x value stays constant for the highfrequency range whereas x starts to increase for the lowfrequency range and approaches also the x values200 nm of the high frequencies. At the same time, sincein the CV-profiling measurement, and essentially also in the

    DLCP method, the defect concentration is computed from

    NCVC03/ dC/dV,38 the contribution of the back diode for

    FIG. 14. The admittance step x of the samples with varied CdS thickness,

    In2S3 buffer, and Schottky contact is plotted vs the root of the corresponding

    activation energy calculated from the N1 contribution in admittance. From

    the slope a carrier concentration can be determined.

    FIG. 15. The result from Fig. 8 is displayed for x in dependence of theapplied dc bias for high and low frequencies. For the low frequency mea-

    surement, the profiling distance x starts to increase with increasing dc biasfor bias voltages +0.9 V.

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    a large forward bias appears as a large virtual increase inthe defect profile, which seems to occur close to the hetero-

    junction. We note again that admittance measurements under

    such large forward bias conditions VVbi should lead to avery large dc junction current making the measurement of

    the capacitance contribution impossible39

    if no back diode

    is present. The fact that the measurement of a meaningful

    forward bias capacitance signal is possible at low T is an-

    other strong piece of evidence that a barrier at the back-

    contact influences the ac and dc measurements.

    Although the majority of the experimental data can be

    well explained by the model assuming a barrier at the back-

    contact, there are a number of results that appear more diffi-

    cult to be reconciled within this model. These are 1 theobserved change in activation energy of the N1 defect upon

    annealing,3 2 a weak dependence of the activation energy

    on the CdS thickness Table II, and 3 a typically observedminority carrier signature of the N1 response in DLTS

    measurements.4

    To explain the observations 1 and 2 within the backdiode model, a change in the back barrier height with anneal-

    ing has to be assumed. Since the CdS treatment is applied at

    elevated temperatures between 60 and 80 C and because

    the thicknesses of the buffer layers are a function of the

    dipping time in the chemical bath, a progressive annealing of

    the back junction with increasing deposition time may also

    occur. Previous investigations of CIGS heterostructures have

    shown a shift in the N1-activation energy upon annealing the

    device independent of whether CdS buffer layers were

    present in the devices.40

    This strongly indicates that the an-

    nealing induces changes in the device that are not related to

    the CdS/CIGS interface. Concerning point 3, the observa-

    tion of a minority trap signature in DLTS appears to be incontradiction to our assignment of the N1 response to a back

    barrier in the device. However, as was shown in Ref. 33, a

    minority or majority carrier signal may be obtained when the

    voltage pulse in the DLTS experiment drops across twoback-to-back connected junctions, depending on the specifics

    of the two junctions involved.

    D. Simulation of admittance and CV using a double-diode model

    Different models for the ac and dc responses of CIGS

    heterojunctions can be evaluated using numerical device

    simulation in which the Poisson equation and the continuity

    equations are solved in one dimension for the full device

    configuration. It will be shown in this section that numerical

    simulation can reproduce the experimental results by inclu-

    sion of a back-contact barrier. In Refs. 36 and 37 it was

    already shown for CdTe-solar cells that a barrier at the back-

    contact can explain the rollover and crossover effects in the

    IVT characteristics. A detailed analysis of the IVT character-

    istics in CIGS solar cells will be published elsewhere. The

    simulations were performed using the SCAPS1D program de-

    veloped at the University of Gent.41

    A barrier height ofB = 0.23 eV is assumed, defined by

    the distance between the Fermi level and the valence band at

    the CIGS/Mo interface. The parameters used for the CdS

    buffer, and i-ZnO and n-ZnO window layers are stated in

    Table III. In the double-diode model, both the depletion

    width of the main junction and the back-contact are affected

    by the carrier concentration within the absorber layer. To

    keep the model simple, one homogeneous absorber layer is

    defined. We note that in order to get good agreement betweenthe simulated and the experimental curves e.g., the admit-tance step height, an inhomogeneous carrier concentrationin the CIGS absorber could be assumed. Such a modification

    would require only small changes in the doping concentra-

    tion, which is reasonable to expect from the generally inho-

    mogeneous composition of the multinary semiconductor ab-

    sorber layer.

    Using the parameters stated in Table III, the simulated

    admittance spectra Fig. 16 show a step corresponding tothe experimental result found for the devices. As described

    above, for C, GC is not activated, causing the applied

    TABLE III. Simulation parameters of the device layers. The letter A/D denotes the type of doping, e.g.,

    acceptors/donors. The thermal velocity for holes and electrons equals 107 cm/s for all layers.

    Parameter CIGS CdS i-ZnO n-ZnO

    d m 1.8 0.06 0.12 0.2

    eV 4.5 4.45 4.55 4.55

    EG eV 1.15 2.45 3.4 3.4

    11.7 10 10 10

    NC cm3 21018 21018 11019 11019

    NV cm3 21018 1.51019 11019 11019

    n cm2/V s 50 50 50 50

    p cm2/V s 20 20 20 20

    NA/D cm3 2.31015 A 1.01015 D 5.01017 D 1.01018 D

    FIG. 16. Simulated C-f curves for different temperatures. An assumed back-

    contact barrier explains the capacitance step in the C-f spectra.

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    alternating voltage to drop also across the back-contact case1, that is, series connection of CC and Cj. For C thecapacitance signal is given by the junction capacitance Cjcase 2. The resulting capacitance step corresponds to theN1 step typically observed in CIGS as shown in Sec. IV.

    There is disagreement in the frequency axis between the ex-

    perimental and simulated curves concerning the temperature

    dependence. This is due to a discrepancy between the emis-

    sion prefactor derived from the experiment data and the

    emission prefactor contained in the numerical simulation.

    This discrepancy can be attributed to the assumption of a

    pure thermionic emission model for the majority carrier

    transport at the back-contact implemented in the SCAPS simu-

    lation code. Measured and simulated prefactors and activa-

    tion energies depend strongly on the specifics of the current

    transport through the back junction, including tunneling con-

    tributions and the effect of an inhomogeneous distribution of

    barrier heights.Using the same parameters as used for the C-f-T simu-

    lation Table III, CV profiles for 150 K can be calculatedFig. 17 with and without the presence of a barrier B at theback-contact. If a barrier at the back-contact is included, the

    profiles triangles and squares show an increase toward theheterointerface caused by an increase in the back barrier

    depletion region for large forward bias voltages. This in-

    crease disappears if the barrier B at the back-contact is

    eliminated in the simulation line. The shape of the simu-lated profiles does not change for low and high measurement

    frequencies with respect to the N1-resonance frequency in

    close agreement with the experimental data shown in Fig. 6.

    The simulation also confirms that the shift in capacitanceprofiles corresponds to the depletion width of the back-

    contact, which in turn depends on barrier height and net dop-

    ing density of the CIGS layer within the back diode deple-

    tion region.

    However, the simulated profiles shown in Fig. 17 do not

    exhibit an increase in the defect concentration toward the

    bulk of the sample. To reproduce such an increase in the

    defect concentration toward the bulk, as is often observed

    experimentally, a deep acceptor state Nt is introduced in the

    absorber layer energetically located at 0.55 eV above the

    valence band. For simplicity the defect is assumed to be

    uniformly distributed throughout the absorber layer with a

    defect concentration of 2.01016 cm3 and a capture cross

    section of 1.01015 cm2 for holes and electrons.

    In Fig. 18 the simulated profiles for a CIGS device with

    a back barrier are shown with and without the presence of

    the deep defects described above. It can be seen that the main

    effect of the deep defects is an apparent increase in defect

    concentration toward the bulk of the sample, although in the

    simulation this defect was assumed to be distributed homo-

    geneously throughout the sample. This apparent increase in

    the defect profile is caused by a quasistatic charge in the

    deep defect Nt close to the heterointerface, which cannotfollow the alternating voltage Vac dynamically but can re-

    spond to the much slower dc bias sweep, Vdc. As stated

    above we have kept the simulation parameters as simple as

    possible to show the possible effects of a back barrier and of

    deep defects on experimental capacitance profiling curves.

    However, it is well known that large compositional gradients

    are typically present in CIGS samples, such that a spatial

    variation of certain material properties such as doping level

    and deep defect density has to be expected. It was the inten-

    tion in this section to show that significant spatial variations

    in the measured defect profiles may already arise from as-

    suming completely uniform material properties.

    VI. CONCLUSIONS

    A systematic investigation of different CIGS thin film

    device structures was presented. The experimental results for

    devices with CdS buffer layers of different thicknesses,

    Schottky contacts, and alternative buffer layers cannot be

    reconciled with the previously discussed interpretation of the

    N1 response as a defect at or close to the heterointerface.It has been shown that a non-Ohmic back-contact can

    explain the N1 response in admittance and CV measure-

    ments. Such a barrier at the back-contact is consistent with

    the apparent increase in the defect concentration toward the

    heterointerface as observed in CV profiles. As known for

    CdTe based solar cells, a back barrier may also be respon-

    sible for the occurrence of the crossover and rollover effects

    in IV measurements.

    The alternative interpretation of the N1-admittance re-

    sponse in CIGS opens up new paths to explain the metasta-

    bility phenomena in these devices, because the model does

    not require Fermi level pinning at the heterointerface.

    FIG. 17. Capacitance profiles simulated with parameters from Table III. The

    profiles with a back barrier B are shown for 10 kHz squares and 1 MHztriangles. A shift between Hf and Lf is discernable without a qualitativechange in the curves. NCV profiles without a barrier B line show no shiftand no change in shape for low 10 kHz and high 1 MHz frequencies. Theincrease toward the interface disappears.

    FIG. 18. NCV profiles at Hf 1 MHz simulated with a back-contact barrierwith diamonds and without triangles an additional deep defect state Nt.

    034509-11 Eisenbarth et al. J. Appl. Phys. 107, 034509 2010

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    ACKNOWLEDGMENTS

    This work was funded by the European Commission,

    Athlet-project under Contract No. 019680. The authors

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