Internship @ Atrenta

Internship @ AtrentaExperience and Learning gained in six months training period Zamrath NizamIntern, Verification Engineer at AtrentaUniversity of MoratuwaInductionIntroduction to personnelWho? What? How?Products Environments

Pre intern periodGetting Started with SpyGlass - Sandun C Rajapakshe (11/21/2013)ASIC flow presentation - Sandun Rathnayake (11/21/2013)Verilog - Sandun Rathnayake (11/25/2013)Installed PCI Development Kit (11/27/2013)Synthesis tool- Thilini Susanka Peelikumbura (11/28/2013)

Pre intern periodPerl (11/29/2013)Simple Verilog task... - Aabid Rushdi (12/2/2013)Simple Protocol Decoder2 headers and tails

Design TaskUART - Sandun Rathnayake (12/10/2013)

UART

UART

UART

UART

Pre intern periodSessions on VHDL, DFT and CDCTraining on Low Power Susantha Mihiranga Wijesekara (12/12/2013)SystemVerilog Training - Lakmal Bandara Dissanayaka (12/12/2013)

Pre intern periodSystemVerilog Training - Nadun M Ellawala (12/13/2013)Design an ALUUsing SV constructs such as typedef, enum, structPre intern periodScripting Exercise.. - Charitha Deshapriya (12/15/2013)writing a scriptShell/perlFive entriesDuplicates

Pre intern periodBugScopeSoC design trends and challengesCompanys strengths and emerging productsGit online training session

Async FIFO ProjectUnderstand the codeCreate test casesSimulate using ModelSimFunctional Verification(Checklist) CDC Verification(Checklist)Pointer round trip should not exceed 8 clock cyclessmall test benches for demonstrating FIFO's functional verification ModulesWrite I/F(Front End)Read I/F(Back End)Wr to Rd SyncRd to Wr SyncStorage/memWr DataWr AddressWr clkWr EnRd DataRd AddressRd clkRd EnWr PointerRd Pointer SyncWr Pointer SyncRd Pointer asff_wrenasff_wrdataasff_wrrst_nasff_wrclkasff_fullasff_wravailasff_overflowasff_rddataasff_emptasff_rdavailasff_underflowasff_rdrst_nasff_rdenasff_rdclkasff_rdclkasff_wrclkSimulation

DFT inceptionSpyGlass DFT hands on labStuck at fault (test) lab

RegressionCondor setupCondor (parallel) - .list0, .list1, .listdCondor submissionsreport.pl file completion

ETCheckerMentorCustom Product

First validation 5.0.0.3 to 5.1.1.6 changesReport file changeCommon walk changeRule to detect .(*) usage in instantiation

Learnings on ETCheckerlv.walk

lv.walk -label-simValues TXFX | T1FX | TXF1 | T1F1 | TXF1C1 | T1F1C1, T1F1FC1,T1F1FC0, T1F1AX \ -startItemList Mod.Inst.pin | Mod.Inst.net [Mod.Inst.pin | Mod.Inst.net] \ -startRTLRegD Mod.Inst.reg | Mod.reg \ -startRTLRegCLK Mod.Inst.reg | Mod.reg \ -startRTLRegQ Mod.Inst.reg | Mod.reg \ -startRTLRegSetRst Mod.Inst.reg | Mod.reg \ -controllability connected | unblocked | Controlling \

-direction fanin | fanout \ (important: all lowercase letters) -stopPointTypeListELTIn ELTOut BLKIn BLKOut CombLoop TMCombLoop TMStopPoint ETCE TM CGD InputDI OutputDI DI(IS) DI(OS) ControlFlop ObservationFlop ClkEnPin CDB ICS TCI ECCI IntScanInst MultiInputGate IntTestclkSrc SFFClk memClk SeqCell MDrv ClkNet ArrayLatch, LACGC, NoAWTArrayLatch, ArrayLatchClock -hitPointTypeList PI PO ELTIn ELTOut BLKIn BLKOut CombLoop TMCombLoop TMStopPoint ETCE TM CGD InputDI OutputDI DI(IS) DI(OS) ControlFlop ObservationFlop ClkEnPin CDB ICS TCI ECCI IntScanInst MultiInputGate IntTestclkSrc SFFClk memClk SeqCell MDrv ClkNet ArrayLatch, LACGC, NoAWTArrayLatch, ArrayLatchClock -stopOnFirstHitYes | (No)DFTdftSGDCSTX_071 Sanity checkWithout -registerSame name forInstance and Module

Async_15 and Scan_38

Async_15Method

Scenarios1. Asynchronous FF 2. Synchronous FF3. With inversion delay of a same source for FF and L4. or two FFs and for a L5. Always @(-without rst-) in L6. One FFs reset is set for a L7. Always @(-with rst-) in L but not in the block (instead another rst)8. Same rst for two Ls

Scan_38Starting with positive edge flop

ScenariosNPP of orientationPNP of orientationNPPP of orientation with combinational circuits in betweenNo testclock is introduced in .sgdc fileChain of registers instead of Scan cell chain

Intel LSSD supportScan-able latchesInfer clock using GCEWith pipeline_depthWhy pipeline_depth_rangeIntel LSSD supportFunctional Latch scannability

FunctionalPipeline_depth & Pipeline_depth_range

gating_cell_enablepipeline_depthphased_clocksScenariosDefault case where -pipeline_depth is left without defining.There are two gating_cell_enable and one -pipeline_depth is left without defining.Normal operation of -pipeline_depth (two latches are placed before and after CGC)Normal operation of -pipeline_depth_range (two latches are placed before and after CGC)pipeline_depth_range 0 5 and placing a CGC after 6th floppipeline_depth_range 3 6 and placing a CGC before 2nd floppipeline_depth_range 0 5 and placing many CGCs in betweenCheck whether both are working togetherMoreNegative value for -pipeline_depthNegative values for -pipeline_depth_rangeMore valid values for -pipeline_depthMore valid values for -pipeline_depth_rangeOne valid value for -pipeline_depth_rangeZero valid values for -pipeline_depthZero valid values for -pipeline_depth_rangeTwo CGCs and -pipeline_depth for one CGC and -pipeline_depth_range for other one

Latch scannabilityShadow latchTransparent latchCGCScannability analysis dft_scannable_latches = on

Spread sheet validation1. Async_072. Async_083. Async_094. Async_135. Atpeed_206. Clock_11

7. Clock_11_capture8. Topology_109. Info_noScan10. Info_forcedScan11. Info_noAtspeed12. Async_11

Scan_39 and Scan_40Scan_39Bugs found scan_chain

Bug is fixed

Still underway

Scan_40Method

ScenariosNo violationSimple violationNegative to positiveMUX between FF_(L-1) and FF_LAfter rectifying what has been given in all_case_netlist_01Two ffs are in different scan chainsTwo negative edge scan chains More 8. Comb in between scan chains9. With two clocks10. With dftStrictTestClkDomains11. FF_(L-1)s and FF_Ls d pins are connected12. Above with inversion13. Two FF_(L-1) for FF_L14. Only two scans15. More in one scan chainMetric Possibilities for Robust TestsAsync_02_captureAsync_11Clock_04Clock_08Clock_16Clock_17Scan_07Async_02_capture

Async_02_captureScenarios:Two flip-flops out of 3 are affected due to violation Two flip-flops converge to a ffs resetTwo flip-flops asynchronous pins are driven by one flip-flops outputTwo flip-flops asynchronous pins are driven by flip-flops output but through different combinational logicOne flip-flop which is violating is no_scan and one which is violated is no_scanLatches come in place of violating flip-flopsBlack boxes come in place of violating flip-flopsAsync_11

Async_11Three flip-flops out of six are affected due to violationTwo flip-flops (out of above three reset) asynchronous pins are connected Two flip-flops (out of above three data) data pins are connected Two flip-flops (out of above three data) data pins are ANDed before feed in to a reset of one flopOne flops (FF3s) data and reset pins are connected together after removing one flip-flop (F3)

6. FF2s asynchronous pin to FF3s data pin and other way around.7. AND gate with FF3s asynchronous pin with F3s data pin8. Using MUXs between FF2 and F2 / FF3 and F39. DFF1s asynchronous pin fan-out and FF1s data pin fan-in of AND gate (still three violations)10. Two AND gates between DFF1 and FF1 connection (still three violations)

Clock_04

Clock_041. Two flip-flops (out of three) data pins are driven by two clocks2. Two flip-flops (out of three) data pins are driven by one clock in above (i) design3. Two clocks are converged so as to feed a data pin of one flop out of two flops4. Clock blocked by a flop (for the design in (i))5. Clock blocked by a MUX6. One flip-flop is defined to be no_scanClock_08

Clock_08Validation

1. Merging without a flip-flop Has covered in existing unit test cases.2. Merging at a MUX tested by an existing test case. i.e. check_in_shift_003. Clock from an inside a module and clock from top module merge4. Inferred clock tested by existing test cases such as case8 and check_in_shift_005. Converging at a flip-flop as clk and d Has covered in few existing unit test cases

48Bugs found in Clock_081. tm makes a Clock_08 violation. Is this a desired feature?

2. Few test cases in Clock_08, such as case6_max_violation, testcase_TI and vi-51635_reportOnUseOff produce incorrect results.

Constraint being,current_design topclock -testclock -name top.w1clock -testclock -name top.w2Clock_16

Clock_16Bugs found Incorrect robustness audit

Clock_17

Clock_171. Output to d pin of a flip-flop2. Using two test-clocks3. Using tri-state buffer at the merging point4. Flip-flops are at both parallel nets5. Flip-flop with no_scan constraint6. Interchange d and clk pins fan-ins of gating flip-flop (q1)7. Sequential two violations8. Sequential two violations with combinational logic in-between9. Sequential two violations with combinational logic in-between10. Two gating flip-flops with one being defined as clock_shaper11. Feeding more flip-flops from one merge pointScan_07

Scan_07Bug foundBug is fixedDone! But yet to review

Thank you