International Islamic University Chittagong Department of ... · PDF fileFamiliarization with...

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International Islamic University Chittagong

Department of Electrical and Electronic Engineering (EEE)

Digital Electronics Lab Manual

Md. Rifat Shariar

Mohammed Abdul kader

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Digital Electronics Lab Manual

Md. Rifat Shariar


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Preface

The basic idea of Digital electronics is mandatory for microprocessor & microcontroller and also

for computer architecture. So, any application which involves microprocessor or a computer has

digital electronics in it.Digital logic has brought “intelligence” to many products of our daily use.

So to understand the modern technology one must have the basic knowledge of digital

electronics.

The objective of this manual is to learn the use of different digital logic gate IC to design,

simulate and implement of different combinational and sequential logic circuit. Also to learn the

application of combinational and sequential circuits in practical field.

After completing this course student can design different useful circuit based on digital logic

design such as-

Project No Project Name

1 Design an automatic traffic control system.

2 Design an industrial product counter.

3 Developing a digital Dice

4 Design and implement a circuit to control Water level of a tank.

5 Design and implement a digital watch.

6 Digital Toshbi.

7 Counting the rotation of rotating parts.


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Contents

Experiment Name Page No.

Familiarization with necessary resources of Digital Electronics Sessional. 01

Verification of operation of different Logic Gate IC (AND, OR, NOT, NAND,

NOR and XOR).

13

Implementation of different logic gates by diodes, transistors and resistors. 16

Implementation of Boolean function by basic logic gates. 19

Implementation of a Half-adder and Full-adder. 21

Familiarization with Seven segment display and BCD to seven segment decoder IC. 24

Implementation of multiplexer and de-multiplexer. 29

Familiarization with flip-flops. 32

Design and implementation of synchronous counter. 37

Design and implementation of asynchronous counter. 40

Implementation of Shift Register 43

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Experiment List with necessary components

Exp.

No

Experiment Name Component/ Equipment List

1 Familiarization with necessary resources of Digital

Electronics Sessional.

Trainer Board IC tester

2 Verification of operation of different Logic Gate IC (AND,

OR, NOT, NAND, NOR and XOR).

Trainer Board IC Tester

IC 7400, IC 7402, IC 7404, IC 7408,

IC 7432, IC 7486 (1 pc of each IC)

3 Implementation of different logic gates by diodes, transistors and resistors.

Trainer Board Diode (2 pcs)

Transistor (1 pc)

Resistor 1K (1pc) 4 Implementation of Boolean function by basic logic gates. Trainer Board

IC Tester

IC 7404, IC 7408, IC 7432 (2 pcs of

each IC) 5 Implementation of a Half-adder and Full-adder. Trainer Board

IC Tester

IC (7408, 7432, 7486)- 1 pcs of each

6 Familiarization with Seven segment display and BCD to

seven segment decoder IC.

Trainer Board

7-segment Display (1 pcs) IC 7448 or IC 4511 (1 pcs)

Resistors : 10 K (4 pcs) and 470 ohm

(7 pcs)

7 Implementation of multiplexer and de-multiplexer. Trainer Board IC Tester

IC : 7408 (1 pcs), 7432 (1 pcs), 7404

(1pcs), 7411 (2 pcs) 8 Familiarization with flip-flops. Trainer Board

IC Tester

IC :7400, 7404, 7408, 7432 (1 pcs of each IC)

9 Design and implementation of synchronous counter. Trainer Board

IC Tester

IC 74107 or 7478 (2 pcs), IC :7408, 7432, 7448 (1 pcs of each)

10 Design and implementation of asynchronous counter. Trainer Board

IC Tester IC 74107 (2 pcs), IC 7400 (1 pcs)

11 Implementation of Shift Register Trainer Board

IC Tester

IC:4013

International Islamic University Chittagong (IIUC)


L a b M a n u a l E E E 2 4 0 8 D i g i t a l E l e c t r o n i c s S e s s i o n a l

Page 1

Experiment No. 01: Familiarization with necessary resources of Digital Electronics Sessional.

1.1 Objectives:

1. To familiarize with digital electronics trainer kit.

2. Familiarization with IC Tester.

3. To familiarize with digital ICs.

4. To learn the simulation of Digital Electronics circuit in Proteus.

1.2 Experiment Requirements:

1. Digital Electronics Trainer Kit.

2. Digital IC Tester.

3. DC power supply unit.

4. Digital ICs: 7408, 7432, 7404, 7400, 7402, 7486, 7410, 7420,74107

1.3 Experiment Procedures:

1. Observe the functionalities and operating procedures of trainer kit.

2. Observe the functionalities and operating procedures of dc power supply unit.

3. Observe the operating procedure of Digital IC Tester.

4. Familiarize with following digital ICs, their pin diagram and pin functions.

1.4 Digital IC’s:

a. Name of the IC: IC 7408, AND gate

PIN diagram PIN description

PIN no. Function PIN no. Function

7 Ground 14 +Vcc

1,2 Input 3 Output

4,5 Input 6 Output

13,12 Input 11 Output

10,9 Input 8 Output




Page 2

b. Name of the IC: IC 7432, OR gate



7 Ground 14 +Vcc

1,2 Input 3 Output

4,5 Input 6 Output


10,9 Input 8 Output

c. Name of the IC: IC 7404, NOT gate



7 Ground 14 +Vcc

1 Input 2 Output

3 Input 4 Output

5 Input 6 Output

13 Input 12 Output

11 Input 10 Output

9 Input 8 Output




Page 3

d. Name of the IC: IC 7400, NAND gate



7 Ground 14 +Vcc

1,2 Input 3 Output

4,5 Input 6 Output


10,9 Input 8 Output

e. Name of the IC: IC 7402, NOR gate



7 Ground 14 +Vcc

2,3 Input 1 Output

5,6 Input 4 Output


8,9 Input 10 Output

f. Name of the IC: IC 7486, XOR gate



7 Ground 14 +Vcc

1,2 Input 3 Out put

4,5 Input 6 Out put

13,12 Input 11 Out put

10,9 Input 8 Out put




Page 4

g. Name of the IC: IC 7410, 3-Input NAND gate


PIN no. Function PIN

no. Function

7 Ground 14 +Vcc

1,2,13 Input 12 Out put



h. Name of the IC: IC 7420, 4-Input NAND gate



no. Function

7 Ground 14 +Vcc

1,2,4,5 Input 6 Out put

9,10,12,13 Input 8 Out put

3,11 Not used - -




Page 5

i. HD74LS78A Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock

PIN description


no. Function

3,14 1J, 1K 1 CLK

13, 12 1Q, 1Q 4, 11 Vcc, Gnd

7, 10 2K, 2J 2, 6 1PR, 2PR

8, 9 2Q, 2Q 5 CLR

j. 74107 Dual Negative Edge triggered J-K Flip-Flops with Reset

PIN description


2,6

Output

(Q A, Q B) 3,5

Output

QA, QB

12,9 CLKA,

CLKB 13,10

Reset

(RA,RB)

1,8 Input

(JA,JB) 7 GND

4,11 Input

(KA,KB) 14 Vcc




Page 6

1.5 Simulation of Digital Circuit in Proteus:

1.5.1 Starting Simulation:

Install PROTEUS in your PC

Go to Start Manu> then Proteus 7 Professional> then open ISIS 7 Professional.

After opening ISIS 7 Professional, you will see the following window.




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1.5.2 Circuit Construction & Assembly:

Select component mode

Click on Pick Device/Symbol or just click on “P” to pick component or device.

Write down the name of your component in the dialogue box known as “Keywords”.

All steps are shown in the following figure-

The selected component can be located on the left side window of the design diagram.

To put the component to the design sheet, just left click the component and put it to the

sheet.

To move the components, simply right click on the component (the component will be

red-lighted), and left click and drag the component to the desired location.

Selection of power and ground terminals: For power terminal and ground, the

component is NOT selected from the library. Select the “terminals mode” icon at the left-

side toolbar. Select POWER and GROUND terminals.




Page 8

Component Parameter Settings: To edit the component, select the component (right-

click) and left-click to open the Edit Component dialog. The dialog is different according

to the devices. Set the parameters as your circuit requirement.

Power source and signal input: To supply circuit power and different input signals such

as DC, SIN, PULSE, Clock and Audio etc select Generator Mode. You can also select

voltage and current sources from library.

Fig: Piecewise Linear Generator Type.

Measuring Instruments: To measure different parameters of the designed circuit select

Virtual Instrument Mode. You will get oscilloscope, ammeter, voltmeter, signal generator

etc in virtual instrument mode.




Page 9

Graphs: To trace the graphs the following three modes are required.

a) Graph Mode.

b) Voltage Probe Mode.

c) Current Probe Mode.

Having drawn the schematic, you choose the type of circuit analysis you require (transient,

frequency, noise, etc.) by placing a Graph of the appropriate type on the schematic. You can

place as many graphs as you want and can even have several graphs of the same type if you

wish. Graph types supported include: Analogue, Digital and Mixed transient graphs as well as

Frequency, Transfer, Noise, Distortion, Fourier, AC Sweep and DC Sweep and Audio graphs.

Set voltage probe or current probe to the circuit node or branch in which you want to see the

graphs. Then drag the probe to graph box or right click the graph box to add probe parameter by

“Add Traces” option. Finally right click the graph box and select “Simulate Graph” option.




Page 10

1.5.3 Simulation Example

Example1. Simulation of different logic gates.

Step1: Pick the following components from component library.

7408,7432,7404, Logic Probe, Logic State

Step2: Place and connect the component according to circuit diagram.

Step3: Play and observe the output logic for different combination of input logic.




Page 11

Example 2: Simulation of 4X1 Multiplexer.

Pick and place the component according to circuit diagram and enjoy simulation.

Lab Report:

You are responsible for documenting your work and your report must include (at minimum) the

following:

1. Cover sheet (Showing your Name, ID, Semester, Section, Exp. Name, Course Title,

Course Code at least)

2. Objectives of the experiment.

3. List of Components.

4. Describe different parts (Logic input switch, logic output display, power supply, Push

switch, 7-segment display, Bread Board etc.) of Trainer Kit.




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5. Describe the procedure of Testing Digital IC.

6. Pin description and pin functions at least 4 digital IC.

7. Also, answer the following questions :

(a) Write down some popular logic families of digital integrated circuits.

(b) Define the given parameters of digital logic families: Fan out, Propagation delay,

Dissipation, Noise Margin.

(c) Make a table presenting various series of TTL logic family with example.

(d) Can you drive a DC motor connecting directly with digital IC’s output pin?

(e) How can you differentiate between digital and analog ICs?

Answer these questions carefully. The answer of these questions is available under the topic

“Integrated circuit”, chapter 2 [Digital logic and computer Design by Morris Mano].

The answer of a question is given for you:

Answer of Question (c)




Page 13

Experiment No. 02: Verification of operation of different Logic Gate IC (AND, OR, NOT,

NAND, NOR and XOR).

2.1 Objectives:

1. To examine the operation of fundamental logic gates AND, OR, NOT, NAND, NOR,

XOR and determine their logical properties.

2. To derive the truth tables of logic gates and verify their logic equations.

2.2 Circuit Diagrams:

Figure 2.1: AND, OR and NOT gates

Figure 2.2: NAND, NOR and XOR gates




Page 14



2. IC Tester

3. IC (7404, 7408, 7432, 7400, 7402, 7486).

4. Multimeter.


1. Place the components of the circuit shown in figure 2.1 on the trainer board and link

the connections correctly.

2. Use the data switches for input and LEDs for output.

3. Power on the trainer board.

4. Observe the outputs for different input configurations and fill in the data table.

5. Follow procedure 1 to 4 for circuit of figure 2.2.

6. Verify the truth tables and output equations obtained for different logic gates.

2.5 Data Table:

A B Y1 (Fig.

2.1)

Y2 (Fig.

2.1)

Y3 (Fig.

2.1)

Y1 (Fig.

2.2)

Y2 (Fig.

2.2)

Y3 (Fig.

2.2)

0 0

0 1

1 0

1 1

Output

Equations




Page 15

2.6 Lab Report:


following:





4. Draw proper circuit diagrams and figures.

5. List the output of the circuit and include it with your report.

6. The circuit is working properly or not. If not, where did you think the errors lie?

7. Simulate the circuit in PROTEUS and attach simulation result in lab report.

8. Answer the following questions:

a. Why we use a series resistance to connect LED with the output pin of digital IC?

b. How you can construct NAND and NOR gates using the basic logic gates AND, OR,

NOT?

c. Why NAND and NOR gates are called universal gate?

d. Construct AND, OR and NOT gate by using NAND gate only. Also, construct these

gates by using NOR gate only.




Page 16

Experiment No. 03: Implementation of basic logic gates by diodes, transistors and resistors.

3.1 Objectives:

1. To examine the operation of diode-resistor (AND, OR) and transistor-resistor (NOT)

logic gates and determine their logical properties.

2. To derive the truth tables of logic gates and verify their logic equations.

3.2 Circuit Diagrams:

A

YB

D1

D2

Figure 3.1: OR gate (Y=A+B)

R= 1KΩ

5V

A

BY

D1

D2

Figure 3.2: AND gate (Y=A∙B)

+Vcc

A

YR1= 1KΩ

Q

R2= 1KΩ

Figure 3.3: NOT gate ( AY )




Page 17



2. IC Tester.

3. Diodes.

4. Transistors.

5. Resistor (1KΩ).






4. Observe the outputs for different input configurations and fill in the data table.



7. Verify the truth tables and output equations obtained for different logic gates.

3.5 Data Table:

A B Y (Fig. 3.1) Y (Fig. 3.2) Y (Fig. 3.3)

0 0

0 1

1 0

1 1

Output Equations




Page 18

3.6 Lab Report:


following:






5. Discuss the function of every component that you have used to make the circuit.




9. Answer the following questions :

a) Draw the circuit diagram of a NOR gate using diodes, transistors and resistors.

b) Draw the circuit diagram of a NAND gate using diodes, transistors and resistors.




Page 19

Experiment No. 04: Implementation of Boolean function by basic logic gates.

4.1 Objectives:

1. To implement the given Boolean function and develop the truth table.

F = ́ ́ ́ ́

2. To simplify the function and develop the truth table and verify it.

4.2 Logic Diagrams:

Figure 4.1: Logic diagram for F = ́ ́ ́ ́



2. IC Tester

3. IC (7404, 7432, 7411, 7408).

4. Multimeter.






4. Observe the outputs for different input configurations and fill up the truth table.

5. Simplify the function to minimum number of literals.

6. Draw the logic diagram for simplified function.

7. Follow procedure 1 to 4 for the simplified logic diagram.

X

Y

F = �́��́�𝑍 �́�𝑌𝑍 𝑋�́�




Page 20

8. Verify the truth table obtained from the simplified logic diagram.

4.6 Truth Table:

X Y Z F

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Output Equations

4.7 Lab Report:


following:










a) Draw the logic diagram for given Boolean function:

b) Discuss some important postulates of Boolean algebra.




Page 21

Experiment No. 05: Implementation of a Half-adder and Full-adder.

5.1 Objectives:

1. To implement a Half-adder.

2. To implement a Full-adder by the help of Half-adders.

5.2 Logic Diagrams:

S

C

S = X Y and C = XY

Figure 5.1: Implementation of a Half-adder

Figure 5.2: Implementation of a Full-adder with two half adder and an OR gate.



2. IC Tester

3. IC (7408, 7432, 7486).

4. Multimeter.





X

Y S = X Y Z

C = Z(X Y) + XY




Page 22



5. Follow procedure 1 to 4 for the circuits shown in figure 5.2.

6. Verify the obtained truth tables with output Boolean functions.

5.5 Truth Tables:

For figure 5.1. (Half-adder)

X Y S C

0 0

0 1

1 0

1 1

Output Equations

For figure 5.2. (Full-adder)

X Y Z S C

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Output Equations




Page 23

5.6 Lab Report:


following:










a. What do you mean by combinational circuit? Write down the procedure to design a

combinational circuit.

b. Mention some application of combinational circuit.

c. Design a combinational circuit to control the traffic at “Tiger Pass Circle,

Chittagong”




Page 24

Name of Experiment 6: Familiarization with Seven segment display and BCD to seven segment

decoder IC.

6.1 Objective:

(a) To know about 7-segment display

(b) To know how to design a BCD to 7-segment decoder

(c) To verify the operation of 7-segment display and decoder


(i) Seven segment common cathode display.

(ii) BCD to seven segment decoder (IC 7448 or IC 4511)

(iii) Resistors (10 K and 470 ohm)

(iv) 5 V DC power supply

(v) Connecting wires

6.3 Circuit Diagram:

Fig 6.1 : Interfacing with 7-segment display using

7448 decoder




Page 25

6.4 Pin Diagram of IC 7448:

Fig 6.2 : Interfacing with 7-segment display using

4511 decoder

Fig6.3: Pin Diagram of 7-segment decoder IC 7448




Page 26

This package accepts a 1-2-4-8 positive-logic Binary Coded Decimal (BCD) input and converts

it to the proper pattern necessary to illuminate a 7 segment display. A high output is intended to

light the segment. (Common cathode), meaning the negative connection of all of the LEDs is tied

together.

The outputs are open-collector but have internal 2K ohm pull-up resistors and have a maximum

low-level output sink current of 6 milliamperes (6mA).

For normal operation the Lamp Test pin and BI/RBO (OUT) must be pulled high (connected to

the positive supply).

All segments are extinguished when a low (logical zero) signal is applied to pin 4 (OUT). A

PWM (pulse-width modulated) signal can be applied to this pin to provided varying brightness to

the LED display being driven, allowing user control of LED dimming for applications such as

power saving by decreasing the brightness during times of low ambient light.

6.5 Pin Diagram of 7-segment Display:

a

f b

g e c

d dp

Com Cathode

e c dp d

g Com

Cathode b f a

Fig 6.4: 7-segment Display




Page 27

6.6 Data Table:

6.7 Lab Report:


following:






5. Discuss the function of every component that you have used to make the circuit.








Page 28

a) What is the difference between common cathode and common anode 7 segment

display?

b) What is pull-up and pull-down resistor? What is the purpose of pull-up and pull-down

resistor?

c) A BCD to seven-segment decoder is a combinational circuit that accepts a decimal

digit in BCD and generates the appropriate outputs for the selection of segments in a

display indicator used for displaying the decimal digit. The seven output of the

decoder (a,b,c,d,e,f,g) select the corresponding segments in the display as shown in

figure 6a. The numeric designation chosen to represent the decimal digit is shown in

figure 6b. Design the BCD to seven segment decoder circuit.

6a: Segment

designation 6b: Numerical designation for display




Page 29

Experiment No. 07: Implementation of multiplexer and de-multiplexer.

7.1 Objectives:

1. To implement a de-multiplexer.

2. To implement a multiplexer.

7.2 Logic Diagrams:

Figure 7.1: Implementation of a De-multiplexer

Figure 7.2: Implementation of a Multiplexer




Page 30



2. IC (7408, 7432, 7404, 7411).

3. Multimeter.







5. Follow procedure 1 to 4 for the circuits shown in figure 7.2.

6. Verify the obtained truth tables output Boolean functions.

7.5 Truth Tables:

For figure 7.1. (De-multiplexer)

E S1 S0 D0 D1 D2 D3

0 0 0

1 0 0

0 0 1

1 0 1

0 1 0

1 1 0

0 1 1

1 1 1

Output Equations




Page 31

For figure 7.2. (Multiplexer)

S1 S0 I0 I1 I2 I3 Y (In terms of affecting

Input)

0 0 0 0 0 0

1 1 1 1

0 1 0 0 0 0

1 1 1 1

1 0 0 0 0 0

1 1 1 1

1 1 0 0 0 0

1 1 1 1

Output Equations

7.6 Lab Report:


following:










a) Implement a Quadruple 2-to-1 line multiplexer.

b) Write down an application of Multiplexer and Demultiplexer.

c) Implement a full adder circuit with multiplexer.




Page 32

Experiment No. 08: Familiarization with flip-flops.

8.1 Objectives:

1. To implement a R-S Flip-Flop.

2. To implement a D Flip-Flop.

3. To implement a JK Flip-Flop.

4. To implement a T Flip-Flop.

8.2 Logic Diagrams:

Figure 8.1: R-S Flip Flop

Figure 8.2: D Flip-Flop




Page 33

Figure 8.3: J-K Flip Flop

Figure 8.4: T Flip Flop



2. IC Tester

3. IC (7400, 7404, 7408, 7432).

4. Multimeter.




Page 34







5. Follow procedures 1 to 4 for the circuits shown in figure 8.2.

6. Follow procedures 1 to 4 for the circuits shown in figure 8.3.

7. Verify the obtained truth tables output Boolean functions.

8.5 Truth Tables:

For figure 8.1 (R-S Flip Flop)

Q(t) C S R Q(t+1) Q´(t+1) Remarks

0 0 0

0 0 1

0 1 0

0 1 1

1 0 1

1 0 0

1 1 1

1 1 0

1 0 0

1 1 1

Output Equations

For figure 8.2. (D Flip-Flop)

Q(t) C D Q(t+1) Q´(t+1) Remarks

0 0

0 1

1 1

1 0

1 1

1 0

Output Equations




Page 35

For figure 8.3. (JK Flip-Flop)

Q(t) C J K Q(t+1) Q´(t+1) Remarks

0 0 0

0 0 1

0 1 0

0 1 1

1 0 1

1 0 0

1 1 1

1 1 0

1 0 0

1 1 1

Output Equations

For figure 8.4. (T Flip-Flop)

Q(t) C T Q(t+1) Q´(t+1) Remarks

0 0

0 1

1 1

1 1

1 1

1 0

1 0

Output Equations

8.6 Lab Report:


following:








7. Simulate the circuits in PROTEUS and attach simulation result in lab report.





Page 36

a) What is sequential circuit? Differentiate between combinational and sequential

circuit.

b) What is the difference between latch and flip-flop?

c) How can you convert a D flip-flop into J-K Flip-flop and T Flip Flop?

d) How can you convert a J-K flip-flop into D and T flip-flop?

e) Suppose that there are 4 floors in a building. There is a light in the main gate of the

building. Design a digital logic circuit such that persons from any floor will be able to

ON or OFF the light.

Figure 8.5: Implement a T Flip-Flop by the help of a D Flip-Flop and other necessary gates




Page 37

Experiment No. 9: Design and implementation of synchronous counter.

9.1 Objectives:

Implementation of a 3-bit synchronous up counter using T Flip-Flop.

9.2 Logic Diagram:

Figure 9.1: Implementation of a 3-bit synchronous up counter.



2. IC Tester

3. IC (7408, 7448, 74107 or, 7478).

4. 7-segment Display (Common Cathode)

5. Multi-meter.




Page 38




2. Connect data switch line to trainer board data switch (for normal operation it should be

5V, and to reset the counter make it 0V) and CLK to clock input.

3. Connect outputs of three JK Flip-Flops Qa, Qb and Qc to three LEDs or, 7-segment

Display. Consider Qc as MSB and Qa as LSB.


5. Observe the outputs sequence and fill up the truth table.

6. Verify obtained truth tables.

9.5 Data Table:

Clock Pulse

sequence

Qc Qb Qa Decimal Value

at display

1

2

3

4

5

6

7

8

9

10

9.6 Lab Report:


following:











Page 39



a) What do you mean by synchronous and asynchronous counter?

b) Design a 3-bit synchronous down counter (Use J-K Flip flop).

c) Write down some application of counter.

d) Write down the IC number of a counter IC with pin diagram.

e) Design and simulate a 0 to 99 counter.

Note:

If IC 74107 is not available in Lab, you can use IC 7478. IC 7478 has an additional pin than

74107 called Preset. But it has only one clock pin for two flip-flop’s, for this reason IC 7478 is

not suitable for asynchronous counter.

Figure 9.2: Implementation of a MOD-8 synchronous up counter (Using IC 7478).

Connect W of Fig.1 to +5V (Logic 1), X to a data switch and CLK to clock input.

Connect outputs of three JK Flip-Flops QA, QB and QC to three LEDs. Consider QC as

MSB and QA as LSB.




Page 40

Experiment No. 10: Design and implementation of asynchronous counter.

10.1 Objectives:

(a) Design and Implementation of a MOD-16 asynchronous up counter.

(b) Design and Implementation of a MOD-16 down counter.

10.2 Logic Diagram:

Figure 10.1 : MOD-16 asynchronous up counter

Figure 10.2 : MOD-16 Asynchronous down counter




Page 41

10.3 Experiment Requirement:


2. IC Tester

3. IC 74107 (2 pcs)


1. Place the components of the circuit shown in figure 10.1 on the trainer board and link the

connections correctly.

2. Connect data switch line to trainer board data switch (for normal operation it should be

5V, and to reset the counter make it 0V) and CLK to clock input.

3. Connect outputs of three JK Flip-Flops Qa, Qb,Qc and Qd to four LED’s of trainer board.

Consider Qd as MSB and Qa as LSB.


5. Observe the outputs sequence and fill up the truth table.

6. Verify obtained truth tables.

7. Don’t disconnect the circuit. Figure 10.1 and 10.2 is almost similar; only rearrange the 3-

connections (Clock input of flip-flop B, C and D should be connected with complement

output of flip-flop A, B and C respectively). Other connections remain same.

8. Repeat step 4, 5 and 6.

10.5 Data Table:

Clock Pulse

sequence

For figure 10.1 For Figure 10.2

Qd Qc Qb Qa Qd Qc Qb Qa

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18




Page 42

10.6 Lab Report:


following:










a) Define MOD number. Design an asynchronous BCD counter.

b) What is the difference between BCD and decade counter?

c) What is the function of Preset Pin of a Flip-Flop IC? Design an asynchronous counter

that will count from 3 to 7.

d) Suppose the frequency of input clock of figure 10.1 is 32 KHz. Find out the

frequency of Qd output. [Hints: output of last (MSB) FF = (input frequency/MOD

No) ]

e) How many flip-flops are required for MOD-60 counter? [Hints: 2N=MOD No]

f) A counter is needed that will count the number of items passing on a conveyor belt. A

photo cell and light source combination is used to generate a single pulse each time

an item cross its path. The counter must be able to count as many as one thousand

items. How many flip-flops are required?




Page 43

Experiment No. 11: Implementation of Shift Register

11.1 Objective:

Observing the operation of a serial in/serial out shift register.

11.2 Logic Diagram:

Figure 11.1: Serial in/ serial out shift register.

11.3 Experiment Requirement:

1) Digital Electronics Trainer Kit

2) IC 4013

3) IC Tester.


1. Place the components of the circuit shown in figure 10.1 on the trainer board and link the

connections correctly.

2. Connect Y1 and Y2 line to trainer board data switch. Normally Y1 and Y2 should be

low. To set the flip-flop output, make it high for a while. Y1 can set left two flip-flops

and Y2 can set right two flip-flops.

3. Connect Y3 line to trainer board data switch (for normal operation it should be 0V, and to

reset the counter make it 5V) and CLK to clock input (Push Switch).

4. Connect data input line to trainer board data switch.





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6. Observe the outputs sequence and fill up the data table.

7. Verify obtained data tables.

11.5 Data Table:

Clock

Sequence

Y1 Y2 Y3 Data

Input

D1 D2 D3 D4

(Data Out)

0 1 0 0 1

1 0 0 0 1

2 0 0 0 0

3 0 0 0 0

4 0 0 0 1

5 0 0 0 0

6 0 0 0 0

7 1 0 0 0

8 0 1 0 1

9 0 0 1 0

10 0 0 0 0

11 0 0 0 1

12 0 0 0 1

11.6 Lab Report:


following:










a) Write down the basic functions of shift register.

b) Discuss the importance of register in microprocessor architecture.

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